Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt

   1 Rockchip RK3288 LVDS interface
   2 ================================
   3
   4 Required properties:
   5 - compatible: matching the soc type, one of
   6         - "rockchip,rk3288-lvds";
   7
   8 - reg: physical base address of the controller and length
   9         of memory mapped region.
  10 - clocks: must include clock specifiers corresponding to entries in the
  11         clock-names property.
  12 - clock-names: must contain "pclk_lvds"
  13
  14 - avdd1v0-supply: regulator phandle for 1.0V analog power
  15 - avdd1v8-supply: regulator phandle for 1.8V analog power
  16 - avdd3v3-supply: regulator phandle for 3.3V analog power
  17
  18 - rockchip,grf: phandle to the general register files syscon
  19 - rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface
  20
  21 Optional properties:
  22 - pinctrl-names: must contain a "lcdc" entry.
  23 - pinctrl-0: pin control group to be used for this controller.
  24
  25 Required nodes:
  26
  27 The lvds has two video ports as described by
  28         Documentation/devicetree/bindings/media/video-interfaces.txt
  29 Their connections are modeled using the OF graph bindings specified in
  30         Documentation/devicetree/bindings/graph.txt.
  31
  32 - video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
  33 - video port 1 for either a panel or subsequent encoder
  34
  35 Example:
  36
  37 lvds_panel: lvds-panel {
  38         compatible = "auo,b101ean01";
  39         enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
  40         data-mapping = "jeida-24";
  41
  42         ports {
  43                 panel_in_lvds: endpoint {
  44                         remote-endpoint = <&lvds_out_panel>;
  45                 };
  46         };
  47 };
  48
  49 For Rockchip RK3288:
  50
  51         lvds: lvds@ff96c000 {
  52                 compatible = "rockchip,rk3288-lvds";
  53                 rockchip,grf = <&grf>;
  54                 reg = <0xff96c000 0x4000>;
  55                 clocks = <&cru PCLK_LVDS_PHY>;
  56                 clock-names = "pclk_lvds";
  57                 pinctrl-names = "lcdc";
  58                 pinctrl-0 = <&lcdc_ctl>;
  59                 avdd1v0-supply = <&vdd10_lcd>;
  60                 avdd1v8-supply = <&vcc18_lcd>;
  61                 avdd3v3-supply = <&vcca_33>;
  62                 rockchip,output = "rgb";
  63                 ports {
  64                         #address-cells = <1>;
  65                         #size-cells = <0>;
  66
  67                         lvds_in: port@0 {
  68                                 reg = <0>;
  69
  70                                 lvds_in_vopb: endpoint@0 {
  71                                         reg = <0>;
  72                                         remote-endpoint = <&vopb_out_lvds>;
  73                                 };
  74                                 lvds_in_vopl: endpoint@1 {
  75                                         reg = <1>;
  76                                         remote-endpoint = <&vopl_out_lvds>;
  77                                 };
  78                         };
  79
  80                         lvds_out: port@1 {
  81                                 reg = <1>;
  82
  83                                 lvds_out_panel: endpoint {
  84                                         remote-endpoint = <&panel_in_lvds>;
  85                                 };
  86                         };
  87                 };
  88         };