1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CPUs bindings
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
19 https://www.devicetree.org/specifications/
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
23 ================================
24 Convention used in this document
25 ================================
27 This document follows the conventions described in the Devicetree
28 Specification, with the addition:
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
33 =====================================
34 cpus and cpu node bindings definition
35 =====================================
37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be present and contain the properties
45 Usage and definition depend on ARM architecture version and
48 On uniprocessor ARM architectures previous to v7
49 this property is required and must be set to 0.
51 On ARM 11 MPcore based systems this property is
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
59 On 32-bit ARM v7 or later systems this property is
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
66 All other bits in the reg cell must be set to 0.
68 On ARM v8 64-bit systems this property is required
69 and matches the MPIDR_EL1 register affinity bits.
71 * If cpus node's #address-cells property is set to 2
73 The first reg cell bits [7:0] must be set to
74 bits [39:32] of MPIDR_EL1.
76 The second reg cell bits [23:0] must be set to
77 bits [23:0] of MPIDR_EL1.
79 * If cpus node's #address-cells property is set to 1
81 The reg cell bits [23:0] must be set to bits [23:0]
84 All other bits in the reg cells must be set to 0.
118 - arm,armv8 # Only for s/w models
153 - nvidia,tegra132-denver
154 - nvidia,tegra186-denver
155 - nvidia,tegra194-carmel
164 - $ref: '/schemas/types.yaml#/definitions/string'
166 # On ARM v8 64-bit this property is required
170 # On ARM 32-bit systems this property is optional
173 - allwinner,sun6i-a31
174 - allwinner,sun8i-a23
175 - allwinner,sun9i-a80-smp
176 - allwinner,sun8i-a83t-smp
178 - amlogic,meson8b-smp
181 - brcm,bcm11351-cpu-method
187 - marvell,armada-375-smp
188 - marvell,armada-380-smp
189 - marvell,armada-390-smp
190 - marvell,armada-xp-smp
191 - marvell,98dx3236-smp
192 - mediatek,mt6589-smp
193 - mediatek,mt81xx-tz-smp
198 - renesas,r9a06g032-smp
199 - rockchip,rk3036-smp
200 - rockchip,rk3066-smp
201 - socionext,milbeaut-m10v-smp
205 $ref: '/schemas/types.yaml#/definitions/uint64'
208 Required for systems that have an "enable-method"
209 property value of "spin-table".
210 On ARM v8 64-bit systems must be a two cell
211 property identifying a 64-bit zero-initialised
215 $ref: '/schemas/types.yaml#/definitions/phandle-array'
217 List of phandles to idle state nodes supported
218 by this cpu (see ./idle-states.txt).
221 $ref: '/schemas/types.yaml#/definitions/uint32'
223 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
224 DMIPS/MHz, relative to highest capacity-dmips-mhz
227 dynamic-power-coefficient:
228 $ref: '/schemas/types.yaml#/definitions/uint32'
230 A u32 value that represents the running time dynamic
231 power coefficient in units of uW/MHz/V^2. The
232 coefficient can either be calculated from power
233 measurements or derived by analysis.
235 The dynamic power consumption of the CPU is
236 proportional to the square of the Voltage (V) and
237 the clock frequency (f). The coefficient is used to
238 calculate the dynamic power as below -
240 Pdyn = dynamic-power-coefficient * V^2 * f
242 where voltage is in V, frequency is in MHz.
245 $ref: '/schemas/types.yaml#/definitions/phandle'
247 Specifies the SAW* node associated with this CPU.
249 Required for systems that have an "enable-method" property
250 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
252 * arm/msm/qcom,saw2.txt
255 $ref: '/schemas/types.yaml#/definitions/phandle'
257 Specifies the ACC* node associated with this CPU.
259 Required for systems that have an "enable-method" property
260 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
262 * arm/msm/qcom,kpss-acc.txt
265 $ref: '/schemas/types.yaml#/definitions/phandle'
267 Specifies the syscon node controlling the cpu core power domains.
269 Optional for systems that have an "enable-method"
270 property value of "rockchip,rk3066-smp"
271 While optional, it is the preferred way to get access to
272 the cpu-core power-domains.
280 rockchip,pmu: [enable-method]
286 #address-cells = <1>;
290 compatible = "arm,cortex-a15";
296 compatible = "arm,cortex-a15";
302 compatible = "arm,cortex-a7";
308 compatible = "arm,cortex-a7";
314 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
317 #address-cells = <1>;
321 compatible = "arm,cortex-a8";
327 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
330 #address-cells = <1>;
334 compatible = "arm,arm926ej-s";
340 // Example 4 (ARM Cortex-A57 64-bit system):
343 #address-cells = <2>;
347 compatible = "arm,cortex-a57";
349 enable-method = "spin-table";
350 cpu-release-addr = <0 0x20000000>;
355 compatible = "arm,cortex-a57";
357 enable-method = "spin-table";
358 cpu-release-addr = <0 0x20000000>;
363 compatible = "arm,cortex-a57";
365 enable-method = "spin-table";
366 cpu-release-addr = <0 0x20000000>;
371 compatible = "arm,cortex-a57";
373 enable-method = "spin-table";
374 cpu-release-addr = <0 0x20000000>;
379 compatible = "arm,cortex-a57";
381 enable-method = "spin-table";
382 cpu-release-addr = <0 0x20000000>;
387 compatible = "arm,cortex-a57";
389 enable-method = "spin-table";
390 cpu-release-addr = <0 0x20000000>;
395 compatible = "arm,cortex-a57";
397 enable-method = "spin-table";
398 cpu-release-addr = <0 0x20000000>;
403 compatible = "arm,cortex-a57";
405 enable-method = "spin-table";
406 cpu-release-addr = <0 0x20000000>;
411 compatible = "arm,cortex-a57";
413 enable-method = "spin-table";
414 cpu-release-addr = <0 0x20000000>;
419 compatible = "arm,cortex-a57";
421 enable-method = "spin-table";
422 cpu-release-addr = <0 0x20000000>;
427 compatible = "arm,cortex-a57";
429 enable-method = "spin-table";
430 cpu-release-addr = <0 0x20000000>;
435 compatible = "arm,cortex-a57";
437 enable-method = "spin-table";
438 cpu-release-addr = <0 0x20000000>;
443 compatible = "arm,cortex-a57";
445 enable-method = "spin-table";
446 cpu-release-addr = <0 0x20000000>;
451 compatible = "arm,cortex-a57";
453 enable-method = "spin-table";
454 cpu-release-addr = <0 0x20000000>;
459 compatible = "arm,cortex-a57";
461 enable-method = "spin-table";
462 cpu-release-addr = <0 0x20000000>;
467 compatible = "arm,cortex-a57";
469 enable-method = "spin-table";
470 cpu-release-addr = <0 0x20000000>;