1 * ARM architected timer
3 ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which
4 provides per-cpu timers.
6 The timer is attached to a GIC to deliver its per-processor interrupts.
8 ** Timer node properties:
10 - compatible : Should at least contain "arm,armv7-timer".
12 - interrupts : Interrupt list for secure, non-secure, virtual and
13 hypervisor timers, in that order.
15 - clock-frequency : The frequency of the main counter, in Hz. Optional.
20 compatible = "arm,cortex-a15-timer",
22 interrupts = <1 13 0xf08>,
26 clock-frequency = <100000000>;