target/linux/ramips/patches-4.4/0902-mediatek-4-byte-spi-reset.patch

   1 diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
   2 index fe9ceb7..2151975 100644
   3 --- a/drivers/mtd/devices/m25p80.c
   4 +++ b/drivers/mtd/devices/m25p80.c
   5 @@ -27,6 +27,9 @@
   6  #include <linux/spi/flash.h>
   7  #include <linux/mtd/spi-nor.h>
   8
   9 +#define OPCODE_RESET_ENABLE    0x66
  10 +#define OPCODE_RESET           0x99
  11 +
  12  #define        MAX_CMD_SIZE            6
  13  struct m25p {
  14         struct spi_device       *spi;
  15 @@ -168,6 +171,17 @@ static int m25p80_erase(struct spi_nor *nor, loff_t offset)
  16         return 0;
  17  }
  18
  19 +void m25p80_reboot(struct mtd_info *mtd)
  20 +{
  21 +       struct spi_nor *nor = container_of(mtd, struct spi_nor, mtd);
  22 +       struct m25p *flash = nor->priv;
  23 +
  24 +       flash->command[0] = OPCODE_RESET_ENABLE;
  25 +       spi_write(flash->spi, flash->command, 1);
  26 +       flash->command[0] = OPCODE_RESET;
  27 +       spi_write(flash->spi, flash->command, 1);
  28 +}
  29 +
  30  /*
  31   * board specific setup should have ensured the SPI clock used here
  32   * matches what the READ command supports, at least until this driver
  33 @@ -197,6 +211,7 @@ static int m25p_probe(struct spi_device *spi)
  34         nor->erase = m25p80_erase;
  35         nor->write_reg = m25p80_write_reg;
  36         nor->read_reg = m25p80_read_reg;
  37 +       nor->mtd._reboot = m25p80_reboot;
  38
  39         nor->dev = &spi->dev;
  40         nor->flash_node = spi->dev.of_node;
  41 --
  42 2.9.3
  43