oweals/u-boot.git
5 years agox86: samus: Add a target to boot through TPL
Simon Glass [Wed, 8 May 2019 03:41:16 +0000 (21:41 -0600)]
x86: samus: Add a target to boot through TPL

Add a version of samus which supports booting from TPL to SPL and then
to U-Boot. This allows TPL to select from an A or B SPL to support
verified boot with field upgrade.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: samus: Update device tree for verified boot
Simon Glass [Wed, 8 May 2019 03:41:14 +0000 (21:41 -0600)]
x86: samus: Update device tree for verified boot

Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: samus: Update device tree for SPL
Simon Glass [Wed, 8 May 2019 03:41:13 +0000 (21:41 -0600)]
x86: samus: Update device tree for SPL

Add tags to allow required nodes to be present in SPL / TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add a simple TPL implementation
Simon Glass [Thu, 2 May 2019 16:52:12 +0000 (10:52 -0600)]
x86: Add a simple TPL implementation

Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add a way to jump from TPL to SPL
Simon Glass [Thu, 2 May 2019 16:52:27 +0000 (10:52 -0600)]
x86: Add a way to jump from TPL to SPL

When TPL finishes it needs to jump to SPL with the stack set up correctly.
Add a function to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: samus: Increase the pre-reloc memory again
Simon Glass [Thu, 2 May 2019 16:52:22 +0000 (10:52 -0600)]
x86: samus: Increase the pre-reloc memory again

This is again too small, so increase it slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Update PCH to work in TPL
Simon Glass [Thu, 2 May 2019 16:52:26 +0000 (10:52 -0600)]
x86: broadwell: Update PCH to work in TPL

The early init should only happen once. Update the probe method to
deal with TPL, SPL and U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Enable the RTC on all boards
Simon Glass [Thu, 2 May 2019 16:52:24 +0000 (10:52 -0600)]
x86: Enable the RTC on all boards

With the move to Kconfig this option should be set in Kconfig, not in the
config header file. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Fix device-tree indentation
Simon Glass [Thu, 2 May 2019 16:52:21 +0000 (10:52 -0600)]
x86: Fix device-tree indentation

With the use of a phandle we can outdent the device tree nodes a little.
Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Update device tree for Chromium OS verified boot
Simon Glass [Thu, 2 May 2019 16:52:20 +0000 (10:52 -0600)]
x86: Update device tree for Chromium OS verified boot

The standard image generated by U-Boot on x86 is u-boot.rom. Add a
separate image called image.bin for verified boot. This supports
verification in TPL of which SPL/U-Boot to start, then jumping to the
correct one, with SPL setting up the SDRAM and U-Boot proper providing
the user interface if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Update device tree for TPL
Simon Glass [Thu, 2 May 2019 16:52:19 +0000 (10:52 -0600)]
x86: Update device tree for TPL

Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add documentation on the samus flashmap
Simon Glass [Thu, 2 May 2019 16:52:16 +0000 (10:52 -0600)]
x86: Add documentation on the samus flashmap

There are quite a few variables which control where things appear in the
final ROM image. Add a flashmap in the documentation to make this easier
to figure out.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: squashed "x86: Update the memory map a little" in]
[bmeng: fixed typo of 'documentation' in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Support PCI VGA ROM when TPL is used
Simon Glass [Fri, 26 Apr 2019 03:59:08 +0000 (21:59 -0600)]
x86: Support PCI VGA ROM when TPL is used

When TPL is in use, U-Boot proper should support initing the VGA ROM even
though the 32-bit init portion is in SPL. Update the condition to handle
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Don't generate a bootstage report in SPL
Simon Glass [Fri, 26 Apr 2019 03:59:07 +0000 (21:59 -0600)]
x86: Don't generate a bootstage report in SPL

This report is normally generated by U-Boot proper. Correct the condition
here so that it respects the Kconfig options for bootstage.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Don't set up MTRRs in SPL
Simon Glass [Fri, 26 Apr 2019 03:59:06 +0000 (21:59 -0600)]
x86: Don't set up MTRRs in SPL

The MTRRs are normally set up in U-Boot proper, so avoid setting them up
in SPL as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Support TPL in Intel common code
Simon Glass [Fri, 26 Apr 2019 03:59:05 +0000 (21:59 -0600)]
x86: Support TPL in Intel common code

Update the Makefie rules to ensure that the correct files are built when
TPL is being used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: sysreset: Implement the get_last() method
Simon Glass [Thu, 2 May 2019 16:52:15 +0000 (10:52 -0600)]
x86: sysreset: Implement the get_last() method

Add a default implementation of this method which always indicates that
the last reset was a power-on reset. This is the most likely type of reset
and without a PCH-specific driver we cannot determine any other type.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: sysreset: Implement power-off if available
Simon Glass [Thu, 2 May 2019 16:52:14 +0000 (10:52 -0600)]
x86: sysreset: Implement power-off if available

On modern x86 devices we can power the system off using the power-
management features of the PCH. Add an implementation for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: sysreset: Separate out the EFI code
Simon Glass [Thu, 2 May 2019 16:52:13 +0000 (10:52 -0600)]
x86: sysreset: Separate out the EFI code

The EFI implementation of reset sits inside the driver and is called
directly from outside the driver, breaking the normal driver-model
conventions. Worse, it passed NULL as the device pointer, hoping that
the called function won't use it, which breaks as soon as code is added
to use it.

Separate out the implementation to improve the situation enough to allow
a future patch to add new sysreset features.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Implement PCH_REQ_PMBASE_INFO
Simon Glass [Fri, 26 Apr 2019 03:59:03 +0000 (21:59 -0600)]
x86: broadwell: Implement PCH_REQ_PMBASE_INFO

Implement this ioctl() to support power off.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: ivybridge: Implement PCH_REQ_PMBASE_INFO
Simon Glass [Fri, 26 Apr 2019 03:59:02 +0000 (21:59 -0600)]
x86: ivybridge: Implement PCH_REQ_PMBASE_INFO

Implement this ioctl() to support power off.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: pch: Add an ioctl to read power-management info
Simon Glass [Fri, 26 Apr 2019 03:59:01 +0000 (21:59 -0600)]
x86: pch: Add an ioctl to read power-management info

Add a new ioctl() request to read information about the power-management
system. This can be used to power off the device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: mrccache: Add more debugging
Simon Glass [Fri, 26 Apr 2019 03:58:59 +0000 (21:58 -0600)]
x86: mrccache: Add more debugging

When the MRC cache fails to save it is useful to have some debugging info
to indicate what when wrong. Add some more debug() calls.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Support saving MRC data from SPL
Simon Glass [Fri, 26 Apr 2019 03:58:57 +0000 (21:58 -0600)]
x86: Support saving MRC data from SPL

When SPL is used to set up the memory controller we want to save the MRC
data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a
function to handle that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add common Intel code for SPL
Simon Glass [Fri, 26 Apr 2019 03:58:56 +0000 (21:58 -0600)]
x86: Add common Intel code for SPL

Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds
and identifies the CPU.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Select refcode and CPU code for SPL
Simon Glass [Fri, 26 Apr 2019 03:58:55 +0000 (21:58 -0600)]
x86: broadwell: Select refcode and CPU code for SPL

Allow broadwell to build for SPL and include the reference code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Allow booting from SPL
Simon Glass [Fri, 26 Apr 2019 03:58:54 +0000 (21:58 -0600)]
x86: broadwell: Allow booting from SPL

At present broadwell only supports booting straight into U-Boot proper.
Add a separate init file to boot from SPL into U-Boot proper, and select
it when SPL is in use.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Allow 16-bit init to be in TPL
Simon Glass [Fri, 26 Apr 2019 03:58:53 +0000 (21:58 -0600)]
x86: Allow 16-bit init to be in TPL

At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add support for starting from SPL/TPL
Simon Glass [Fri, 26 Apr 2019 03:58:52 +0000 (21:58 -0600)]
x86: Add support for starting from SPL/TPL

When a previous phase of U-Boot has run we need to adjust the init of
subsequent states to avoid messing up the CPU state.

Add a new version of the start logic for SPL, when it boots from TPL
(start_from tpl.c) and a new version for U-Boot when it boots from SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Split CPU init
Simon Glass [Fri, 26 Apr 2019 03:58:51 +0000 (21:58 -0600)]
x86: broadwell: Split CPU init

Split the CPU init into two parts - the 'full' init which happens in the
first U-Boot phase, and the rest of the init that happens on subsequent
stages.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Move init of debug UART to cpu.c
Simon Glass [Fri, 26 Apr 2019 03:58:50 +0000 (21:58 -0600)]
x86: broadwell: Move init of debug UART to cpu.c

At present the debug UART is set up in sdram.c which is not the best place
since it has nothing in particular to do with SDRAM. Since we want to
support initing this in SPL too, move it to a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: added 'broadwell' tag in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Allow SDRAM init from SPL
Simon Glass [Fri, 26 Apr 2019 03:58:49 +0000 (21:58 -0600)]
x86: broadwell: Allow SDRAM init from SPL

At present, for broadwell, SDRAM is always set up in U-Boot proper since
the 64-bit mode (which uses SDRAM init in SPL) is not supported.

Update the code to allow SDRAM init in SPL instead so that U-Boot proper
can be loaded into SDRAM and run from there. This allows U-Boot to be
compressed to reduce space, since it is not necessary to run it directly
from flash. It could later allow us to support 64-bit U-Boot on broadwell.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: broadwell: Improve SDRAM debugging output
Simon Glass [Fri, 26 Apr 2019 03:58:48 +0000 (21:58 -0600)]
x86: broadwell: Improve SDRAM debugging output

Add debugging during SDRAM init so that problems are easier to
diagnose.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add a handoff header file
Simon Glass [Fri, 26 Apr 2019 03:58:47 +0000 (21:58 -0600)]
x86: Add a handoff header file

Add an arch-specific handoff header so that we can use the HANDOFF feature
on x86 devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Support booting with TPL
Simon Glass [Fri, 26 Apr 2019 03:58:46 +0000 (21:58 -0600)]
x86: Support booting with TPL

Some boards want to use TPL as the first phase of U-Boot. This allows
selection of A or B SPL phases, thus allowing the memory init to be
upgraded in the field.

Add a new Kconfig option for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Support SPL and TPL
Simon Glass [Fri, 26 Apr 2019 03:58:45 +0000 (21:58 -0600)]
x86: Support SPL and TPL

At present only chromebook_link64 supports SPL. It is useful to eb able to
support both TPL and SPL to implement verified boot on x86.

Enable the options for both along with some suitable default options
needed to boot through these phases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: dts: Add device-tree labels for rtc and reset
Simon Glass [Fri, 26 Apr 2019 03:58:43 +0000 (21:58 -0600)]
x86: dts: Add device-tree labels for rtc and reset

Add labels for these nodes so that board DT files can reference them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Add a way to reinit the cpu
Simon Glass [Fri, 26 Apr 2019 03:58:42 +0000 (21:58 -0600)]
x86: Add a way to reinit the cpu

We cannot init the CPU fully both than once during a boot. Add a new
function which can be called to figure out the CPU identity, but which
does not change anything. For x86_64, this is empty for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: mp_init: Use proper error numbers
Simon Glass [Fri, 26 Apr 2019 03:58:41 +0000 (21:58 -0600)]
x86: mp_init: Use proper error numbers

At present many of the functions in this file return -1 as an error
number. which is -EPERM. Update the code to use real error numbers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: Update a stale comment about ifdtool
Simon Glass [Fri, 26 Apr 2019 03:58:44 +0000 (21:58 -0600)]
x86: Update a stale comment about ifdtool

We use binman to build the x86 image now. Update a comment which still
refers to ifdtool.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agox86: start64: Fix copyright message
Simon Glass [Fri, 26 Apr 2019 03:58:40 +0000 (21:58 -0600)]
x86: start64: Fix copyright message

There is a typo in this header. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoRevert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
Simon Glass [Wed, 8 May 2019 03:41:15 +0000 (21:41 -0600)]
Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"

This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d.

Unfortunately this has a dramatic impact on the pre-relocation memory
used on x86 platforms (increasing it by 2KB) since it increases the
overhead for each PCI device from 220 bytes to 412 bytes.

The offending line is in UCLASS_DRIVER(pci):

.per_device_auto_alloc_size = sizeof(struct pci_controller),

This means that all PCI devices have the controller struct associated
with them. The solution is to move the regions[] member out of the array,
makes its size dynamic, or split UCLASS_PCI into controllers and
non-controllers, as the comment suggests.

For now, revert the commit to get things running again.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agocros_ec: Use a hyphen in the uclass name
Simon Glass [Thu, 2 May 2019 16:52:11 +0000 (10:52 -0600)]
cros_ec: Use a hyphen in the uclass name

Device-tree rules require that aliases use a hyphen rather than a
underscore. Update the uclass name to fit with this.

This allows device-tree aliases to be used to refer to cros-ec devices,
for example:

aliases {
    cros-ec0 = &ec;
    cros-ec1 = &pd;
};

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agospl: Allow sandbox to build a device-tree file
Simon Glass [Fri, 26 Apr 2019 03:58:38 +0000 (21:58 -0600)]
spl: Allow sandbox to build a device-tree file

At present only OF_SEPARATE is considered valid for building a device-tree
file in SPL. However sandbox uses OF_HOSTFILE instead. Update the logic to
handle this and make it easier to understand.

Note that the new logic is not quite the same as the old logic. It was
previously assumed that checking for:

   $(CONFIG_$(SPL_TPL_)OF_CONTROL)
   $(CONFIG_OF_SEPARATE)
   $(CONFIG_$(SPL_TPL_)OF_PLATDATA)

producing 'yy' meant that the first two were 'y' and the last was empty.
Strictly speaking it would be possible for any two of the three to be 'y'
and still yield the same result. However, that was not the intention of
the new logic, since OF_PLATDATA always ensures that no device-tree file
is included. So in effect the new logic is the same, with the addition of
OF_HOSTFILE as an option for OP_SEPARATE.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agodm: core: Fix translate condition in ofnode_get_addr_size()
Simon Glass [Fri, 26 Apr 2019 03:58:36 +0000 (21:58 -0600)]
dm: core: Fix translate condition in ofnode_get_addr_size()

Update the condition to translate only if this is enabled for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agobinman: Allow sections to have an offset
Simon Glass [Fri, 26 Apr 2019 03:58:39 +0000 (21:58 -0600)]
binman: Allow sections to have an offset

At present sections are always placed automatically. Even if an 'offset'
property is provided it is ignored. Update the logic to support an offset
for sections.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agobinman: Add a missing comment in Entry_vblock
Simon Glass [Fri, 26 Apr 2019 03:58:35 +0000 (21:58 -0600)]
binman: Add a missing comment in Entry_vblock

An important property is missing. Update the entry comment to include
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agobinman: Don't show image-skip message by default
Simon Glass [Fri, 26 Apr 2019 03:58:34 +0000 (21:58 -0600)]
binman: Don't show image-skip message by default

This message is not very important since it is simply indicating that the
user's instructions are being followed. Only show it when the verbosity
level is above the default.

Also drop the unnecessary extra newline on this message, which causes two
line breaks.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agobinman: Don't generate an error in 'text' entry constructor
Simon Glass [Fri, 26 Apr 2019 03:58:33 +0000 (21:58 -0600)]
binman: Don't generate an error in 'text' entry constructor

It is not good practice to raise an exception in a constructor. In this
case the 'text' entry may not actually be used, if -i is used to filter
out the images that get built.

Move the exception to where the data is actually used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Tue, 7 May 2019 13:38:00 +0000 (09:38 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

- RZ/A1 addition.
- Old board removal.

5 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Tue, 7 May 2019 13:37:11 +0000 (09:37 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- Assorted stratix10 fixes.
- DDR driver DM migration.

5 years agoARM: dts: renesas: Add RZ/A1 GR-Peach board
Chris Brandt [Wed, 23 Aug 2017 19:53:59 +0000 (14:53 -0500)]
ARM: dts: renesas: Add RZ/A1 GR-Peach board

Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach,
which is a cheap development platform with RZ/A1H SoC. The
DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Currently supported are UART, ethernet and RPC SPI. The board
can be booted from RPC SPI by writing the u-boot.bin binary
to the beginning of the SPI NOR, e.g. using the "sf" command.
The board can also be booted via JTAG by setting text base to
0x20020000, loading u-boot.bin there via JTAG and executing it
from that address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agoARM: dts: renesas: Add RZ/A1 platform code
Chris Brandt [Wed, 23 Aug 2017 19:53:59 +0000 (14:53 -0500)]
ARM: dts: renesas: Add RZ/A1 platform code

Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC.
Distinguishing feature of this SoC is that it has up to
10 MiB of on-SoC static RAM (SRAM).

The DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agospi: rpc: Add support for operation without clock framework
Marek Vasut [Sat, 4 May 2019 16:52:33 +0000 (18:52 +0200)]
spi: rpc: Add support for operation without clock framework

Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agonet: sh_eth: Add support for operation without clock framework
Marek Vasut [Wed, 1 May 2019 22:03:26 +0000 (00:03 +0200)]
net: sh_eth: Add support for operation without clock framework

Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agonet: sh_eth: Add RZ/A1 support
Marek Vasut [Wed, 1 May 2019 16:20:48 +0000 (18:20 +0200)]
net: sh_eth: Add RZ/A1 support

Add support for RZ/A1 SoC specifics.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agoserial: sh: Add RZ/A1 support
Marek Vasut [Wed, 1 May 2019 16:20:00 +0000 (18:20 +0200)]
serial: sh: Add RZ/A1 support

Add support for RZ/A1 SoC specifics.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agotimer: renesas: Add RZ/A1 R7S72100 OSTM timer driver
Marek Vasut [Sat, 4 May 2019 15:30:58 +0000 (17:30 +0200)]
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver

Add OSTM timer driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agopinctrl: renesas: Add RZ/A1 R7S72100 pin control driver
Marek Vasut [Sat, 4 May 2019 12:17:10 +0000 (14:17 +0200)]
pinctrl: renesas: Add RZ/A1 R7S72100 pin control driver

Add pin control driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agogpio: renesas: Add RZ/A1 R7S72100 GPIO driver
Marek Vasut [Sat, 4 May 2019 14:00:17 +0000 (16:00 +0200)]
gpio: renesas: Add RZ/A1 R7S72100 GPIO driver

Add GPIO driver for RZ/A1 SoC. The IP is very different from the
R-Car Gen2/Gen3 one already present in the tree, hence a custom
driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 years agosh: 7785: Remove CPU support
Marek Vasut [Sat, 4 May 2019 11:28:04 +0000 (13:28 +0200)]
sh: 7785: Remove CPU support

There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 years agosh: sh7785lcr: Remove the board
Marek Vasut [Sat, 4 May 2019 11:21:07 +0000 (13:21 +0200)]
sh: sh7785lcr: Remove the board

Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 years agosh: 7724: Remove CPU support
Marek Vasut [Sat, 4 May 2019 11:31:06 +0000 (13:31 +0200)]
sh: 7724: Remove CPU support

There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 years agosh: ecovec: Remove the board
Marek Vasut [Sat, 4 May 2019 11:24:51 +0000 (13:24 +0200)]
sh: ecovec: Remove the board

Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 years agosh: sh7757lcr: Fix copy-paste error in README
Marek Vasut [Sat, 4 May 2019 11:30:05 +0000 (13:30 +0200)]
sh: sh7757lcr: Fix copy-paste error in README

Update the README to use the correct defconfig.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Mon, 6 May 2019 11:18:51 +0000 (07:18 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

- Various pinctrl / gpio fixes for R-Car

5 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Mon, 6 May 2019 11:18:28 +0000 (07:18 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

- Important spi-mem fix

5 years agoARM: socfpga: stratix10: Probe FPGA status before bridge enable
Ang, Chee Hong [Fri, 3 May 2019 08:18:27 +0000 (01:18 -0700)]
ARM: socfpga: stratix10: Probe FPGA status before bridge enable

Send CONFIG_STATUS and RECONFIG_STATUS mailbox commands to Secure
Device Manager (SDM) to get the status of FPGA and make sure the
FPGA is in user mode before enable the bridge.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
5 years agoARM: socfpga: stratix10: Disable FPGA2SOC reset
Ang, Chee Hong [Fri, 3 May 2019 08:19:08 +0000 (01:19 -0700)]
ARM: socfpga: stratix10: Disable FPGA2SOC reset

Software must never reset FPGA2SOC bridge. This bridge must only be
reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software
can cause the SoC to lock-up if there are traffics being drived into
FPGA2SOC bridge.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
5 years agoarm: socfpga: Move Stratix 10 SDRAM driver to DM
Ley Foon Tan [Mon, 6 May 2019 01:56:01 +0000 (09:56 +0800)]
arm: socfpga: Move Stratix 10 SDRAM driver to DM

Convert Stratix 10 SDRAM driver to device model.

Get rid of call to socfpga_per_reset() and use reset
framework.

SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.

Move sdram_s10.h from arch to driver/ddr/altera directory.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
5 years agoarm: dts: Stratix10: Add SDRAM node
Ley Foon Tan [Mon, 6 May 2019 01:56:00 +0000 (09:56 +0800)]
arm: dts: Stratix10: Add SDRAM node

Add SDRAM device tree node.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
5 years agoddr: altera: Compile ALTERA SDRAM in SPL only
Ley Foon Tan [Mon, 6 May 2019 01:55:59 +0000 (09:55 +0800)]
ddr: altera: Compile ALTERA SDRAM in SPL only

Compile ALTERA_SDRAM driver in SPL only.
Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
5 years agoMerge branch '2019-05-05-master-imports'
Tom Rini [Sun, 5 May 2019 16:25:39 +0000 (12:25 -0400)]
Merge branch '2019-05-05-master-imports'

- Various assorted fixes
- btrfs zstd compression support
- Enable hardware DDR levelling on am43xx platforms.
- pl310 cache controller driver

5 years agoenv: add missing newline
Philip Molloy [Sun, 31 Mar 2019 03:44:57 +0000 (03:44 +0000)]
env: add missing newline

Signed-off-by: Philip Molloy <philip@philipmolloy.com>
5 years agoboard: toradex: drop support.arm maintainer email
Marcel Ziswiler [Thu, 2 May 2019 15:14:30 +0000 (17:14 +0200)]
board: toradex: drop support.arm maintainer email

Drop Toradex ARM Support <support.arm@toradex.com> from maintainer email
list as this just clogs our support ticketing system.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
5 years agocmd: pxe: add board specific PXE default path
Marek Behún [Thu, 2 May 2019 13:29:12 +0000 (15:29 +0200)]
cmd: pxe: add board specific PXE default path

The list of PXE default paths contains ARCH and SOC specific paths, but
one PXE server can serve different board with the same ARCH and SOC.
This is the case for Turris Omnia and Turris Mox, where ARCH=arm and
SOC=mvebu.

If CONFIG_SYS_BOARD is defined, also try "default-$ARCH-$SOC-$BOARD"
path.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
5 years agoARM: da850evm: Enable da850-ohci USB host controller
Adam Ford [Tue, 30 Apr 2019 10:21:42 +0000 (05:21 -0500)]
ARM: da850evm: Enable da850-ohci USB host controller

The DA850 EVM has one USB 1.1 OHCI Host controller.  With the
host controller now support DM_USB, this patch enables
the respective functions for the da850evm.

Signed-off-by: Adam Ford <aford173@gmail.com>
5 years agousb: ohci: ohci-da8xx: Enable da850-ohci driver with DM support
Adam Ford [Tue, 30 Apr 2019 10:21:41 +0000 (05:21 -0500)]
usb: ohci: ohci-da8xx: Enable da850-ohci driver with DM support

This patch reuses some former code for the hawkboard, combines it
with some some similar DM_USB compatible code for the OHCI driver,
and enables the use of the da850's OHCI controller with DM_USB
compatibility.

Signed-off-by: Adam Ford <aford173@gmail.com>
5 years agofs: btrfs: add zstd decompression support
Marek Behún [Mon, 29 Apr 2019 20:40:45 +0000 (22:40 +0200)]
fs: btrfs: add zstd decompression support

This adds decompression support for Zstandard, which has been included
in Linux btrfs driver for some time.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
5 years agolib: add Zstandard decompression support
Marek Behún [Mon, 29 Apr 2019 20:40:44 +0000 (22:40 +0200)]
lib: add Zstandard decompression support

Add the zstd library from Linux kernel (only decompression support).
There are minimal changes to build with U-Boot, otherwise the files are
identical to Linux commit dc35da16 from March 2018, the files had not
been touched since in kernel. Also SPDX lincese tags were added.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
5 years agolib: Add xxhash support
Marek Behún [Mon, 29 Apr 2019 20:40:43 +0000 (22:40 +0200)]
lib: Add xxhash support

This adds the xxhash support from Linux. Files are almost identical to
those added to Linux in commit 5d240522 ("lib: Add xxhash module") (they
haven't been touched since in Linux). The only difference is to add some
includes to be compatible with U-Boot. Also SPDX lincese tags were
added.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
5 years agoboard: ti: am43xx: Enable hardware leveling
Brad Griffis [Mon, 29 Apr 2019 04:29:33 +0000 (09:59 +0530)]
board: ti: am43xx: Enable hardware leveling

Remove the RDLVL_MASK, RDLVLGATE_MASK, WRLVL_MASK & enable
PHY_INVERT_CLKOUT to enable Hardware leveling for am437x
as recommended by EMIF Tools app note:

http://www.ti.com/lit/an/sprac70/sprac70.pdf

Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
5 years agoarm: mach-omap2: am33xx: ddr: update value for ext_phy_ctrl_36
Brad Griffis [Mon, 29 Apr 2019 04:29:32 +0000 (09:59 +0530)]
arm: mach-omap2: am33xx: ddr: update value for ext_phy_ctrl_36

for suspend/resume robustness

update value for ext_phy_ctrl_36 for suspend/resume robustness
with hardware leveling enabled.

Match recommended values from EMIF Tools app note:

http://www.ti.com/lit/an/sprac70/sprac70.pdf

Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
5 years agoarm: mach-omap2: am33xx: Disable EMIF_DEVOFF immediately before hw leveling
Brad Griffis [Mon, 29 Apr 2019 04:29:31 +0000 (09:59 +0530)]
arm: mach-omap2: am33xx: Disable EMIF_DEVOFF immediately before hw leveling

In case of RTC+DDR resume, need to restore EMIF context
before initiating hardware leveling.

Signed-off-by: Brad Griffis <bgriffis@ti.com>
[j-keerthy@ti.com Fixed the am335x build issues]
Signed-off-by: Keerthy <j-keerthy@ti.com>
5 years agoarm: mach-omap2: am33xx: Enable HW Leveling in the rtc+ddr path
Brad Griffis [Mon, 29 Apr 2019 04:29:30 +0000 (09:59 +0530)]
arm: mach-omap2: am33xx: Enable HW Leveling in the rtc+ddr path

Enable HW leveling in RTC+DDR path. The mandate is to enable
HW leveling bit and then wait for 1 ms before accessing any
register.

Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
5 years agoarm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 error
Brad Griffis [Mon, 29 Apr 2019 04:29:29 +0000 (09:59 +0530)]
arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 error

Add 1ms delay to avoid L3 timeout error during suspend resume.

Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
5 years agoarm: mach-omap2: am33xx: ddr: programming of EXT_PHY_CTRL1 and EXT_PHY_CTRL1_SHADOW
Brad Griffis [Mon, 29 Apr 2019 04:29:28 +0000 (09:59 +0530)]
arm: mach-omap2: am33xx: ddr: programming of EXT_PHY_CTRL1 and EXT_PHY_CTRL1_SHADOW

Adjust DQS skew in case where invert_clkout=1 is used.
Match recommended values from EMIF Tools app note:

http://www.ti.com/lit/an/sprac70/sprac70.pdf

Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
5 years agolib/display_options: avoid illegal memory access
Heinrich Schuchardt [Fri, 26 Apr 2019 16:39:00 +0000 (18:39 +0200)]
lib/display_options: avoid illegal memory access

display_options_get_banner_priv() overwrites bytes before the start of the
buffer if the buffer size is less then 3. This case occurs in the Sandbox
when executing the `ut_print` command.

Correctly handle small buffer sizes. Adjust the print unit test to catch
when bytes before the buffer are overwritten.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agoconfigs: am335x_evm: enable SPL_FIT_IMAGE_TINY
Jean-Jacques Hiblot [Fri, 26 Apr 2019 13:21:26 +0000 (15:21 +0200)]
configs: am335x_evm: enable SPL_FIT_IMAGE_TINY

The size of the SPL for the am335x_evm is constrained. There is no need
to have advanced SPL FIT features, so keep the SPL FIT support tiny.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
5 years agospl: fit: Always enable tracking of os-type if SPL_OS_BOOT is enabled
Jean-Jacques Hiblot [Fri, 26 Apr 2019 13:21:25 +0000 (15:21 +0200)]
spl: fit: Always enable tracking of os-type if SPL_OS_BOOT is enabled

FIT_IMAGE_TINY is used to reduce the size of the SPL by removing os-type
tracking and recording the loadables into the loaded FDT. When this option
is enabled, it is assumed that the next stage firmware is u-boot.
However this does not play well with the SPL_OS_BOOT option that enables
loading different type of next stage firmware, like the OS itself.

When SPL_OS_BOOT is used, do not disable os-tracking. The added footprint
is about 300 Bytes.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
5 years agospl: fix linker size check off-by-one errors
Simon Goldschmidt [Thu, 25 Apr 2019 19:22:39 +0000 (21:22 +0200)]
spl: fix linker size check off-by-one errors

This fixes SPL linker script size checks for 3 lds files where the size
checks were implemented as "x < YYY_MAX_SIZE".

Fix the size checks to be "x <= YYY_MAX_SIZE" instead.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
5 years agoconfigs: socfpga: add imply pl310 cache controller
Dinh Nguyen [Tue, 23 Apr 2019 21:55:06 +0000 (16:55 -0500)]
configs: socfpga: add imply pl310 cache controller

Select the PL310 UCLASS_CACHE driver for SoCFPGA.

Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
5 years agoARM: socfpga: use the pl310 driver to configure the cache
Dinh Nguyen [Tue, 23 Apr 2019 21:55:05 +0000 (16:55 -0500)]
ARM: socfpga: use the pl310 driver to configure the cache

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
5 years agodm: cache: add the pl310 cache controller driver
Dinh Nguyen [Tue, 23 Apr 2019 21:55:04 +0000 (16:55 -0500)]
dm: cache: add the pl310 cache controller driver

Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.

This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
5 years agodm: cache: Create a uclass for cache
Dinh Nguyen [Tue, 23 Apr 2019 21:55:03 +0000 (16:55 -0500)]
dm: cache: Create a uclass for cache

The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
5 years agoARM: pl310: Add macro's for handling tag and data latency mask
Dinh Nguyen [Tue, 23 Apr 2019 21:55:02 +0000 (16:55 -0500)]
ARM: pl310: Add macro's for handling tag and data latency mask

Add the PL310 macros for latency control setup, read and write bits.

Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
5 years agoDocumentation: dts: Add pl310 cache controller dts documentation
Dinh Nguyen [Tue, 23 Apr 2019 21:55:01 +0000 (16:55 -0500)]
Documentation: dts: Add pl310 cache controller dts documentation

Linux commit 8ecd7f5970c5 ("ARM: 8483/1: Documentation: l2c: Rename
l2cc to l2c2x0")

Linux docs:
Documentation/devicetree/bindings/arm/l2c2x0.txt

Copied from Linux kernel v5.0.

"The documentation in the l2cc.txt is specific to the L2 cache
controllers L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310
and variants) and not generic as the file name implies. It's not
valid for integrated L2 controllers as found in e.g.
Cortex-A15/A7/A57/A53."

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
5 years agoboard: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build
Vignesh Raghavendra [Mon, 22 Apr 2019 16:13:33 +0000 (21:43 +0530)]
board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build

AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
5 years agoarch: armv8: Provide a way to disable cache maintenance ops
Vignesh Raghavendra [Mon, 22 Apr 2019 16:13:32 +0000 (21:43 +0530)]
arch: armv8: Provide a way to disable cache maintenance ops

On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache
maintenance operations being done to support non-coherent platforms
causes issues.

For example, here is how U-Boot prepares/handles a buffer to receive
data from a device (DMA Write). This may vary slightly depending on the
driver framework:

Start DMA to write to destination buffer
Wait for DMA to be done (dma_receive()/dma_memcpy())
Invalidate destination buffer (invalidate_dcache_range())
Read from destination buffer

The invalidate after the DMA is needed in order to read latest data from
memory that’s updated by DMA write. Also, in case random prefetch has
pulled in buffer data during the “wait for DMA” before the DMA has
written to it. This works well for non-coherent architectures.

In case of coherent architecture with L3 cache, DMA write would directly
update L3 cache contents (assuming cacheline is present in L3) without
updating the DDR memory. So invalidate after “wait for DMA” in above
sequence would discard latest data and read will cause stale data to be
fetched from DDR. Therefore invalidate after “wait for DMA” is not
always correct on coherent architecture.

Therefore, provide a Kconfig option to disable cache maintenance ops on
coherent architectures. This has added benefit of improving the
performance of DMA transfers as we no longer need to invalidate/flush
individual cache lines(especially for buffer thats several KBs in size).

In order to facilitate use of same Kconfig across different
architecture, I have added the symbol to top level arch/Kconfig file.
Patch currently disables cache maintenance ops for arm64 only.
flush_dcache_all() and invalidate_dcache_all() are exclusively used
during enabling/disabling dcache and hence are not disabled.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
5 years agoRefactor IMAGE_ENABLE_VERIFY to handle builds without SPL verification
Alex Kiernan [Thu, 18 Apr 2019 20:34:55 +0000 (20:34 +0000)]
Refactor IMAGE_ENABLE_VERIFY to handle builds without SPL verification

If building with SPL_LOAD_FIT_FULL and FIT_SIGNATURE, but without
SPL_FIT_SIGNATURE then the build fails with:

  common/built-in.o: In function `fit_image_verify_with_data':
  common/image-fit.c:1220: undefined reference to `fit_image_verify_required_sigs'
  common/image-fit.c:1244: undefined reference to `fit_image_check_sig'
  common/built-in.o: In function `fit_image_load':
  common/image-fit.c:1857: undefined reference to `fit_config_verify'

Refactor so that host builds still depend on FIT_SIGNATURE, but target
builds check FIT_SIGNATURE/SPL_FIT_SIGNATURE dependent on the build.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>