oweals/u-boot.git
9 years agodrivers/qe: transform parameter to compatible type
Zhao Qiang [Tue, 5 May 2015 07:53:32 +0000 (15:53 +0800)]
drivers/qe: transform parameter to compatible type

when using printf, the parameter type need to be compatible
type, so transform them to compatible type

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoarmv7/ls1021a: Reserve secure code into RAM instead of OCRAM
Zhuoyu Zhang [Tue, 24 Mar 2015 09:27:37 +0000 (17:27 +0800)]
armv7/ls1021a: Reserve secure code into RAM instead of OCRAM

For ls1021a, Reserve secure code in to memory in case OCRAM
is needed by other usage.

Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoPrepare v2015.10-rc1 v2015.10-rc1
Tom Rini [Mon, 3 Aug 2015 14:52:14 +0000 (10:52 -0400)]
Prepare v2015.10-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>
9 years agofsl_esdhc.c: Always make check_and_invalidate_dcache_range available
Tom Rini [Sun, 2 Aug 2015 14:27:52 +0000 (10:27 -0400)]
fsl_esdhc.c: Always make check_and_invalidate_dcache_range available

This function is called from esdhc_send_cmd so we need it available to
everyone.

Signed-off-by: Tom Rini <trini@konsulko.com>
9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-imx
Tom Rini [Sun, 2 Aug 2015 11:40:37 +0000 (07:40 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-imx

9 years agoarm: mx6: tqma6: fix build for WRU-IV baseboard
Stefano Babic [Sun, 26 Jul 2015 12:28:25 +0000 (14:28 +0200)]
arm: mx6: tqma6: fix build for WRU-IV baseboard

Fix:
 undefined reference to `spi_flash_free'
 undefined reference to `spi_flash_probe'

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Stefan Roese <sr@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Stefan Roese <sr@denx.de>
9 years agoimx: mx6ul_14x14_evk add basic board support
Peng Fan [Mon, 20 Jul 2015 11:28:35 +0000 (19:28 +0800)]
imx: mx6ul_14x14_evk add basic board support

1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
2. Support SPL
3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
   supports sd for usdhc2, but can do hardware rework to make usdhc2 support
   emmc.

Boot Log:
U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
reading u-boot.img
reading u-boot.img

U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C)CPU:   Thermal invalid data, fuse: 0x0
 - invalid sensor device
 Reset cause: POR
 Board: MX6UL 14x14 EVK
 I2C:   ready
 DRAM:  512 MiB
 MMC:   FSL_SDHC: 0, FSL_SDHC: 1
 *** Warning - bad CRC, using default environment

 In:    serial
 Out:   serial
 Err:   serial
 Net:   CPU Net Initialization Failed
 No ethernet found.
 Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: imx6_spl add mx6ul support
Peng Fan [Mon, 20 Jul 2015 11:28:34 +0000 (19:28 +0800)]
imx: imx6_spl add mx6ul support

i.MX6UL's DRAM space starts from 0x80000000, same to i.MX6SX, so use
same address with i.MX6SX.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx:mx6ul add dram spl configuration and header file
Peng Fan [Mon, 20 Jul 2015 11:28:33 +0000 (19:28 +0800)]
imx:mx6ul add dram spl configuration and header file

1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
   only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
   runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
   IO configuration.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agomx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL
Peng Fan [Mon, 20 Jul 2015 11:28:32 +0000 (19:28 +0800)]
mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL

DRAM space starts from 0x80000000 for i.MX6UL, so need to
fix LOADADDR, SYS_TEXT_BASE.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agomxc: gpio add i.MX6UL support
Peng Fan [Mon, 20 Jul 2015 11:28:31 +0000 (19:28 +0800)]
mxc: gpio add i.MX6UL support

i.MX6UL does not have GPIO6/7, so do not include them for i.MX6UL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL
Peng Fan [Mon, 20 Jul 2015 11:28:30 +0000 (19:28 +0800)]
imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL

PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6)

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6ul update soc related settings
Peng Fan [Mon, 20 Jul 2015 11:28:29 +0000 (19:28 +0800)]
imx: mx6ul update soc related settings

1.Update WDOG settings.
2.No need to gate/ungate all PFDs for i.MX6UL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
9 years agoimx: mx6ul select SYS_L2CACHE_OFF
Peng Fan [Mon, 20 Jul 2015 11:28:28 +0000 (19:28 +0800)]
imx: mx6ul select SYS_L2CACHE_OFF

i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx:mx6ul add clock support
Peng Fan [Mon, 20 Jul 2015 11:28:27 +0000 (19:28 +0800)]
imx:mx6ul add clock support

1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
   MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
   but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
   sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
   || defined....", only need one CONFIG_PCIE_IMX in header file.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6ul remove errata for i.MX6UL
Peng Fan [Mon, 20 Jul 2015 11:28:26 +0000 (19:28 +0800)]
imx: mx6ul remove errata for i.MX6UL

Since i.MX6UL use A7 core, but not A9 core, we do not need
the erratas for i.MX6UL.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx-common: timer: add i.MX6UL support
Peng Fan [Mon, 20 Jul 2015 11:28:25 +0000 (19:28 +0800)]
imx-common: timer: add i.MX6UL support

Add i.MX6UL GPT timer support.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL
Peng Fan [Mon, 20 Jul 2015 11:28:24 +0000 (19:28 +0800)]
imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL

Since i.MX6UL's cache line size is 64bytes, need to
define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6ul: Update imx registers head file
Peng Fan [Mon, 20 Jul 2015 11:28:23 +0000 (19:28 +0800)]
imx: mx6ul: Update imx registers head file

1. Update imx register base address for i.MX6UL.
2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
3. Remove #ifdef for register addresses that equal to
   "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
4. According fuse map, complete fuse_bank4_regs.
5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX,
   because we can use runtime check

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: mx6ul: Add pins IOMUX head file
Peng Fan [Mon, 20 Jul 2015 11:28:22 +0000 (19:28 +0800)]
imx: mx6ul: Add pins IOMUX head file

Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
9 years agoimx: mx6ul: Add i.MX6UL CPU type
Peng Fan [Mon, 20 Jul 2015 11:28:21 +0000 (19:28 +0800)]
imx: mx6ul: Add i.MX6UL CPU type

Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from
DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which
is not real id from DIGPROG register, so change i.MX6D to value 0x67 which
was not occupied.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
9 years agosf: kconfig: add kconfig options for spi flashes
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:38 +0000 (17:19 +0300)]
sf: kconfig: add kconfig options for spi flashes

Add kconfig options for various SPI flashes and use them in cm-fx6 defconfig.

Cc: Jagan Teki <jteki@openedev.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agousb: kconfig: create a menu for usb
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:37 +0000 (17:19 +0300)]
usb: kconfig: create a menu for usb

With recent additions to USB Kconfig the number of USB options had grown
large enough to warrant a separate menu for USB.

Add a Kconfig menu for USB.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
9 years agousb: kconfig: usb keyboard kconfig
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:36 +0000 (17:19 +0300)]
usb: kconfig: usb keyboard kconfig

Add Kconfig options for USB keyboard and use them for cm-fx6.

Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: usb: kconfig: add USB_EHCI_MX6 kconfig option
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:35 +0000 (17:19 +0300)]
arm: mx6: usb: kconfig: add USB_EHCI_MX6 kconfig option

Add USB_EHCI_MX6 option to menuconfig and use it when migrating cm-fx6 usb
config to defconfig.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: kconfig: don't select CPU_V7 per board
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:34 +0000 (17:19 +0300)]
arm: mx6: kconfig: don't select CPU_V7 per board

CPU_V7 is already selected by ARCH_MX6, so no point in selecting it again
by boards that depend on ARCH_MX6.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
9 years agoarm: mx6: cm-fx6: move cm-fx6 target under ARCH_MX6
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:33 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: move cm-fx6 target under ARCH_MX6

cm-fx6 is an MX6 based board, and the menuconfig hierarchy should
reflect that. Make TARGET_CM_FX6 dependant on ARCH_MX6.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: cm-fx6: move CMD configs to defconfig
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:32 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: move CMD configs to defconfig

Move CONFIG_CMD_* options that can be selected in menuconfig to cm-fx6
defconfig.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: cm-fx6: setup hdmi only on hdmi enable
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:31 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: setup hdmi only on hdmi enable

Refactor display code to only setup hdmi if do_enable_hdmi() is invoked.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: cm-fx6: add support for displaytype env var
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:30 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: add support for displaytype env var

Add support for selecting display preset using the environment variable
"displaytype". This is a preparation for future merging of compulab
omap3_display.c display selection code with the cm-fx6 display selection code.

The "panel" environment variable is retained for backwards compatibility.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: cm-fx6: make it possible to not init display
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:29 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: make it possible to not init display

Implement a cm-fx6 specific board_video_skip() to provide the option to not
initialize the display.

The new function does not init display if the environment variable "panel" is
not defined, or if it is set to an unsupported value.

Collateral changes:
- Don't use the global displays array (it's CONFIG_IMX_VIDEO_SKIP specific).
- Don't use detect_hdmi(), since env controlled init makes it unnecessary.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: cm-fx6: map HDMI to IPU1 DI0 explicitly
Nikita Kiryanov [Thu, 23 Jul 2015 14:19:28 +0000 (17:19 +0300)]
arm: mx6: cm-fx6: map HDMI to IPU1 DI0 explicitly

U-Boot does not explicitly assign the display to an IPU interface. Instead, it
relies on the power-on default of DI0.

Since the kernel reassigns HDMI display to DI1, after a warm reset the HDMI
display no longer works in U-Boot.

Fix this by explicitly assigning HDMI to IPU1 DI0 in U-Boot.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoimx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
Peng Fan [Sat, 11 Jul 2015 03:38:47 +0000 (11:38 +0800)]
imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support

1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
   and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.

Build target: mx6qpsabreauto_config

Boot Log:
U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)

CPU:   Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
PMIC:  PFUZE100 ID=0x10
Flash: 32 MiB
NAND:  0 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

No panel detected: default to HDMI
Display: HDMI (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Note:
In this patch, we still add a new config mx6qpsabreauto_config,
since SPL is not supported now, and IMX_CONFIG is needed at
build time, so add this config. Future, when SPL is converted,
this config can be removed.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agoimx: mx6sabresd/sabreauto runtime setting fdt_file
Peng Fan [Sat, 11 Jul 2015 03:38:46 +0000 (11:38 +0800)]
imx: mx6sabresd/sabreauto runtime setting fdt_file

Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.

Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
9 years agoimx: mx6qp Enable PRG clock for IPU
Peng Fan [Sat, 11 Jul 2015 03:38:45 +0000 (11:38 +0800)]
imx: mx6qp Enable PRG clock for IPU

The i.MX6DQP has a PRG module, need to enable its clock for using IPU.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Brown Oliver <B37094@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
9 years agoimx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QP
Ye.Li [Sat, 11 Jul 2015 03:38:44 +0000 (11:38 +0800)]
imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QP

Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround
for i.MX6QP.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
9 years agoimx: mx6: ccm: Change the clock settings for i.MX6QP
Peng Fan [Sat, 11 Jul 2015 03:38:43 +0000 (11:38 +0800)]
imx: mx6: ccm: Change the clock settings for i.MX6QP

Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.

In c files, use runtime check and discard #ifdef.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
9 years agoimx: add cpu type for i.MX6QP/DP
Peng Fan [Sat, 11 Jul 2015 03:38:42 +0000 (11:38 +0800)]
imx: add cpu type for i.MX6QP/DP

Add cpu type for i.MX6QP/DP.

This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP
and MXC_CPU_MX6DP, we should use:
(is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)).

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Tom Rini [Sat, 1 Aug 2015 00:16:21 +0000 (20:16 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

9 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Sat, 1 Aug 2015 00:16:04 +0000 (20:16 -0400)]
Merge git://git.denx.de/u-boot-x86

9 years agopowerpc/T104xRDB: Remove vbank check redundant code
Priyanka Jain [Thu, 30 Jul 2015 04:50:18 +0000 (10:20 +0530)]
powerpc/T104xRDB: Remove vbank check redundant code

sw variable in checkboard function is storing vbank value
which can only take 3-bit value.
So check of sw value for if greater than 7 is redundant.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t1023rdb: eMMC boot without external SD card
Shengzhou Liu [Tue, 28 Jul 2015 02:46:47 +0000 (10:46 +0800)]
powerpc/t1023rdb: eMMC boot without external SD card

eMMC has no CD and WP pins, it needs to add board-specific
board_mmc_getcd() and board_mmc_getwp() in SPL to support
eMMC boot without external SD card inserted.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t4240: update serdes table
Shaohui Xie [Wed, 29 Jul 2015 03:28:36 +0000 (11:28 +0800)]
powerpc/t4240: update serdes table

Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3
support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes
A/B/C/D are not available, updated the serdes table accordingly with
some minor fix.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t1023rdb: add support for T1023RDB RevC
Shengzhou Liu [Wed, 17 Jun 2015 08:37:01 +0000 (16:37 +0800)]
powerpc/t1023rdb: add support for T1023RDB RevC

Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM
Aneesh Bansal [Tue, 16 Jun 2015 05:06:43 +0000 (10:36 +0530)]
powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAM

For running Chain of Trust when doing Secure Boot from NAND,
the Bootscript header and bootscript must be copied from NAND
to RAM(DDR).
The addresses and commands for the same have been defined.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Aneesh Bansal [Tue, 16 Jun 2015 05:06:30 +0000 (10:36 +0530)]
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040

Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.

The targets for P5020 and P5040 are added in the same manner.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Aneesh Bansal [Tue, 16 Jun 2015 05:06:00 +0000 (10:36 +0530)]
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.

In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopatman: Don't run patman when it is imported as a module
Simon Glass [Thu, 30 Jul 2015 19:47:41 +0000 (13:47 -0600)]
patman: Don't run patman when it is imported as a module

Commit 488d19c (patman: add distutils based installer) has the side effect
of making patman run twice with each invocation. Fix this by checking for
'main program' invocation in patman.py. This is good practice in any case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
9 years agoarmv8: caches: Added routine to set non cacheable region
Siva Durga Prasad Paladugu [Fri, 26 Jun 2015 12:35:07 +0000 (18:05 +0530)]
armv8: caches: Added routine to set non cacheable region

Added routine mmu_set_region_dcache_behaviour() to set a
particular region as non cacheable.

Define dummy routine for mmu_set_region_dcache_behaviour()
to handle incase of dcache off.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-tegra
Tom Rini [Wed, 29 Jul 2015 22:58:39 +0000 (18:58 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-tegra

9 years agopowerpc/T102xRDB: Enable ifc nand ecc encode and decode
Jaiprakash Singh [Fri, 22 May 2015 09:51:07 +0000 (15:21 +0530)]
powerpc/T102xRDB: Enable ifc nand ecc encode and decode

IFC nand ecc encode and decode mode are not correctly
set in CSOR register during nand initialization.Enable
ecc encode/decode in 4-bit mode

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: Correct CONFIG_USB_MAX_CONTROLLER_COUNT for p1025
Nikhil Badola [Thu, 21 May 2015 03:37:53 +0000 (09:07 +0530)]
powerpc/mpc85xx: Correct CONFIG_USB_MAX_CONTROLLER_COUNT for p1025

Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1
for p1025 as it has one USB controller

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/b4860qds: Update README for DIP switch information
Raghav Dogra [Thu, 14 May 2015 11:17:16 +0000 (16:47 +0530)]
powerpc/b4860qds: Update README for DIP switch information

The board manual desribes ON as boolean 1 and OFF as boolean 0.
Updating README with correct boolean values.

Signed-off-by: Raghav Dogra <raghav@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t1024: update fman liodn for mac1
Shengzhou Liu [Thu, 14 May 2015 08:51:39 +0000 (16:51 +0800)]
powerpc/t1024: update fman liodn for mac1

MAC1 acts as 1G/10G dual-role MAC on T1024. We introduce
macro SET_FMAN_RX_10G_TYPE2_LIODN for 10G MACs which have
same Port ID and same offset of address with 1G MAC.
Update it to match with the setting of fman in t1024 device
tree, otherwise there is no 'fsl,liodn' in
/proc/device-tree/soc@ffe000000/fman@400000/port@88000/

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t104x, t102x: Update CPC debug register value in PBI commands
Priyanka Jain [Thu, 7 May 2015 08:54:31 +0000 (14:24 +0530)]
powerpc/t104x, t102x: Update CPC debug register value in PBI commands

Update PBI command in pbi_cfg files to keep register bit
to default reset value while configuring CPC
as SRAM

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t4rdb: fix cpld reset altbank
Shaohui Xie [Wed, 29 Apr 2015 06:56:53 +0000 (14:56 +0800)]
powerpc/t4rdb: fix cpld reset altbank

cpld reset altbank should always reset to bank4 no matter what
current bank is.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/p2020rdb: fix the FDT_ERR_NOTFOUND issue
Ying Zhang [Fri, 24 Apr 2015 07:49:15 +0000 (15:49 +0800)]
powerpc/p2020rdb: fix the FDT_ERR_NOTFOUND issue

Because the function ft_board_setup() delete the USB2 device node, it
leads to can't find the device node and hung up.

In fact only P1020RDB needs to delete the USB2 node, this patch fixes
this issue.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms
gaurav rana [Thu, 26 Mar 2015 10:22:47 +0000 (15:52 +0530)]
powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms

defconfig files are added and SFP version for these platforms
is updated.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/T104xD4RDB: Add T104xD4RDB boards support
Priyanka Jain [Fri, 5 Jun 2015 09:59:02 +0000 (15:29 +0530)]
powerpc/T104xD4RDB: Add T104xD4RDB boards support

T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
    T1040D4RDB is re-designed T1040RDB board with following changes :
    - Support of DDR4 memory
    - Support of 0x66 serdes protocol which can support following interfaces
        - 2 RGMII's on DTSEC4, DTSEC5
        - 1 SGMII on DTSEC3
    - Support of QE-TDM

    Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
    SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
    - Support of DDR4 memory
    - Support for 0x86 serdes protocol which can support following interfaces
        - 2 RGMII's on DTSEC4, DTSEC5
        - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
    - Support of DIU

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoT210: Add support for 64-bit T210-based P2571 board
Tom Warren [Thu, 12 Feb 2015 22:01:49 +0000 (15:01 -0700)]
T210: Add support for 64-bit T210-based P2571 board

Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.

With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).

Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoP2571: dts: Add DT file for Tegra210 P2571 board
Tom Warren [Fri, 13 Feb 2015 21:39:53 +0000 (14:39 -0700)]
P2571: dts: Add DT file for Tegra210 P2571 board

Based on T124 Venice2. SDMMC1 is SD-card slot.

Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: Tegra210: Add support to common Tegra source/config files
Tom Warren [Wed, 4 Mar 2015 23:36:00 +0000 (16:36 -0700)]
ARM: Tegra210: Add support to common Tegra source/config files

Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
9 years agoARM: Tegra210: Add SoC code/include files for T210
Tom Warren [Mon, 2 Feb 2015 20:22:29 +0000 (13:22 -0700)]
ARM: Tegra210: Add SoC code/include files for T210

All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.

Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.

Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoTegra: Rework KConfig options to allow 64-bit builds (T210)
Tom Warren [Fri, 17 Jul 2015 15:12:51 +0000 (08:12 -0700)]
Tegra: Rework KConfig options to allow 64-bit builds (T210)

Moved Tegra config options to mach-tegra/Kconfig so that both
32-bit and 64-bit builds can co-exist for Tegra SoCs.

T210 will be 64-bit only (no SPL) and will require a 32-bit
AVP/BPMP loader.

Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoTegra210: Fix 64-bit build warning about save_boot_params_ret()
Tom Warren [Wed, 8 Jul 2015 15:05:35 +0000 (08:05 -0700)]
Tegra210: Fix 64-bit build warning about save_boot_params_ret()

Simon's 'tegra124: Implement spl_was_boot_source()' needs
a prototype for save_boot_params_ret() to build cleanly
for 64-bit Tegra210.

Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Use architected timer on ARMv8
Thierry Reding [Tue, 28 Jul 2015 09:35:54 +0000 (11:35 +0200)]
ARM: tegra: Use architected timer on ARMv8

ARMv8 requires an architected timer to be present, so it can be used
instead of the Tegra US timer. This allows for better code reuse.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Initialize timer earlier
Thierry Reding [Tue, 28 Jul 2015 09:35:53 +0000 (11:35 +0200)]
ARM: tegra: Initialize timer earlier

A subsequent patch will enable the use of the architected timer on
ARMv8. Doing so implies that udelay() will be backed by this timer
implementation, and hence the architected timer must be ready when
udelay() is first called. The first time udelay() is used is while
resetting the debug UART, which happens very early. Make sure that
arch_timer_init() is called before that.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Disable SPL and non-cached memory on 64-bit
Thierry Reding [Mon, 27 Jul 2015 17:45:26 +0000 (11:45 -0600)]
ARM: tegra: Disable SPL and non-cached memory on 64-bit

For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cached memory is not
implemented (yet) for 64-bit ARM.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
9 years agoARM: tegra: Use standard cache enable for 64-bit
Thierry Reding [Mon, 27 Jul 2015 17:45:25 +0000 (11:45 -0600)]
ARM: tegra: Use standard cache enable for 64-bit

On 64-bit SoCs the I-cache isn't enabled in early code, so the default
cache enable functions for 64-bit ARM can be used.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
9 years agoARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCs
Thierry Reding [Mon, 27 Jul 2015 17:45:24 +0000 (11:45 -0600)]
ARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCs

Most peripherals on Tegra can do DMA only to the lower 32-bit
address space, even on 64-bit SoCs. This limitation is
typically overcome by the use of an IOMMU. Since the IOMMU is
not entirely trivial to set up and serves no other purpose
(I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to
the lower 32-bit address space for RAM. This ensures that the
physical addresses of buffers that are programmed into the
various DMA engines are valid and don't alias to lower addresses.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
9 years agofdt: Fix fdtdec_get_addr_size() for 64-bit
Thierry Reding [Thu, 23 Jul 2015 16:51:30 +0000 (10:51 -0600)]
fdt: Fix fdtdec_get_addr_size() for 64-bit

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
9 years agoarmv8/cache: Fix page table creation
Thierry Reding [Wed, 22 Jul 2015 23:10:11 +0000 (17:10 -0600)]
armv8/cache: Fix page table creation

While generating the page tables, a running integer index is shifted by
SECTION_SHIFT (29) and causes overflow for any integer bigger than 7.
The page tables therefore alias to the same 8 sections and cause U-Boot
to hang once the MMU is enabled.

Fix this by making the index a 64-bit unsigned integer and so avoid the
overflow.

swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and
"j" varies depending on RAM size; from 4 to 11 for a board with 4GB at
physical address 2GB, as some Tegra boards have.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agopatman: add distutils based installer
Chris Packham [Wed, 22 Jul 2015 09:21:46 +0000 (21:21 +1200)]
patman: add distutils based installer

To make it easier to use patman on other projects add a distutils style
installer. Now patman can be installed with

  cd u-boot/tools/patman && python setup.py install

There are also the usual distutils options for creating source/binary
distributions of patman.

Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Reserve PCIe ECAM address range in the E820 table
Bin Meng [Wed, 22 Jul 2015 08:21:15 +0000 (01:21 -0700)]
x86: Reserve PCIe ECAM address range in the E820 table

We should mark PCIe ECAM address range in the E820 table as reserved
otherwise kernel will not attempt to use ECAM.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: qemu: Turn on PCIe ECAM address range decoding on Q35
Bin Meng [Wed, 22 Jul 2015 08:21:14 +0000 (01:21 -0700)]
x86: qemu: Turn on PCIe ECAM address range decoding on Q35

Turn on PCIe ECAM address range decoding on Q35.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: qemu: Enable writing MP table
Bin Meng [Wed, 22 Jul 2015 08:21:13 +0000 (01:21 -0700)]
x86: qemu: Enable writing MP table

Enable writing MP table for QEMU boads (i440fx and q35).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Allow cpu-x86 driver to be probed for UP
Bin Meng [Wed, 22 Jul 2015 08:21:12 +0000 (01:21 -0700)]
x86: Allow cpu-x86 driver to be probed for UP

Currently cpu-x86 driver is probed only for SMP. We add the same
support for UP when there is only one cpu node in the deive tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: qemu: Enable I/O APIC chip select on PIIX3
Bin Meng [Wed, 22 Jul 2015 08:21:11 +0000 (01:21 -0700)]
x86: qemu: Enable I/O APIC chip select on PIIX3

The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: mpspec: Move writing ISA interrupt entry after PCI
Bin Meng [Wed, 22 Jul 2015 08:21:10 +0000 (01:21 -0700)]
x86: mpspec: Move writing ISA interrupt entry after PCI

On some platforms the I/O APIC interrupt pin#0-15 may be connected
to platform pci devices' interrupt pin. In such cases the legacy ISA
IRQ is not available so we should not write ISA interrupt entry if
it is already occupied.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC
Bin Meng [Wed, 22 Jul 2015 08:21:09 +0000 (01:21 -0700)]
x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC

Currently during writing MP table I/O interrupt assignment entry, we
assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which
however is not always the case on some platforms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Convert to use driver model pci on queensbay/crownbay
Bin Meng [Sat, 18 Jul 2015 16:20:07 +0000 (00:20 +0800)]
x86: Convert to use driver model pci on queensbay/crownbay

Move to driver model pci for Intel queensbay/crownbay.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: pci: Support bridge device configuration correctly
Bin Meng [Sat, 18 Jul 2015 16:20:06 +0000 (00:20 +0800)]
dm: pci: Support bridge device configuration correctly

Commit aec241d "dm: pci: Use the correct hose when configuring devices"
was an attempt to fix pci bridge device configuration, but unfortunately
that does not work 100%. In pciauto_config_devices(), the fix tried to
call pciauto_config_device() with a ctlr_hose which is supposed to be
the root controller hose, however when walking through a pci topology
with 2 or more pci bridges this logic simply fails.

The call chain is: pciauto_config_devices()->pciauto_config_device()
->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus()
does not make any sense as the given hose is not the bridge device's
hose, instead it is either the root controller's hose (case#1: if it
is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2:
if it is the 3rd pci bridge). In both cases the logic is wrong.

For example, for failing case#1 if the bridge device to config has the
same devfn as one of the devices under the root controller, the call
to pci_bus_find_devfn() will return the udevice of that pci device
under the root controller as the bus, but this is wrong as the udevice
is not a bus which does not contain all the necessary bits associated
with the udevice which causes further failures.

To correctly support pci bridge device configuration, we should still
call pciauto_config_device() with the pci bridge's hose directly.
In order to access valid pci region information, we need to refer to
the root controller simply by a call to pci_bus_to_hose(0) and get the
region information there in the pciauto_prescan_setup_bridge(),
pciauto_postscan_setup_bridge() and pciauto_config_device().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: pci: Pass only device/function to pci_bus_find_devfn()
Bin Meng [Sat, 18 Jul 2015 16:20:05 +0000 (00:20 +0800)]
dm: pci: Pass only device/function to pci_bus_find_devfn()

In dm_pci_hose_probe_bus(), pci_bus_find_devfn() is called with a bdf
which includes a bus number, but it really should not as this routine
only expects a device/function encoding.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: pci: Use complete bdf in all pci config read/write routines
Bin Meng [Sat, 18 Jul 2015 16:20:04 +0000 (00:20 +0800)]
dm: pci: Use complete bdf in all pci config read/write routines

Currently pci_bus_read_config() and pci_bus_write_config() are
called with bus number masked off in the parameter bdf, and bus
number is supposed to be added back in the bridge driver's pci
config read/write ops if the device is behind a pci bridge.
However this logic only works for a pci topology where there is
only one bridge off the root controller. If there is addtional
bridge in the system, the logic will create a non-existent bdf
where its bus number gets accumulated across bridges.

To correct this, we change all pci config read/write routines
to use complete bdf all the way up to the root controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agodm: pci: Correct primary/secondary/subordinate bus number assignment
Bin Meng [Sat, 18 Jul 2015 16:20:03 +0000 (00:20 +0800)]
dm: pci: Correct primary/secondary/subordinate bus number assignment

In driver model, each pci bridge device has its own hose structure.
hose->first_busno points to the bridge device's device number, so
we should not substract hose->first_busno before programming the
bridge device's primary/secondary/subordinate bus number registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agoFix incorrect comments in linker_lists.h
Bin Meng [Sat, 18 Jul 2015 16:20:02 +0000 (00:20 +0800)]
Fix incorrect comments in linker_lists.h

This corrects several typos in the comment block as well as some
indentions and nits in the linker_lists.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agobuildman: Correct '--fetch-arch' command documentation
Bin Meng [Fri, 17 Jul 2015 02:43:46 +0000 (19:43 -0700)]
buildman: Correct '--fetch-arch' command documentation

The doc wrongly put sandbox in the '--fetch-arch' command. Remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: pci: Do not assign irq 0 to pci device
Bin Meng [Wed, 15 Jul 2015 08:23:41 +0000 (16:23 +0800)]
x86: pci: Do not assign irq 0 to pci device

IRQ 0 is reserved and should not be assigned to pci device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: pci: Assign pci irqs to all functions
Bin Meng [Wed, 15 Jul 2015 08:23:40 +0000 (16:23 +0800)]
x86: pci: Assign pci irqs to all functions

We need walk through all functions within a PCI device and assign
their IRQs accordingly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Enable DM RTC support for all x86 boards
Bin Meng [Wed, 15 Jul 2015 08:23:39 +0000 (16:23 +0800)]
x86: Enable DM RTC support for all x86 boards

Add a RTC node in the device tree to enable DM RTC support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squashed in 'x86: Fix RTC build error on ivybridge')

9 years agox86: Change pci option rom area MTRR setting to cacheable
Bin Meng [Wed, 15 Jul 2015 08:23:38 +0000 (16:23 +0800)]
x86: Change pci option rom area MTRR setting to cacheable

Turn on cache on the pci option rom area to improve the performance.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Simplify architecture defined exception handling in irq_llsr()
Bin Meng [Fri, 10 Jul 2015 02:51:23 +0000 (10:51 +0800)]
x86: Simplify architecture defined exception handling in irq_llsr()

Instead of using switch..case for architecture defined exceptions,
simply unify the handling by printing a message of exception name,
followed by registers dump then halt the CPU.

With this unification, it also fixes the wrong exception numbers
for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 15/16/17/18.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Display correct CS/EIP/EFLAGS when there is an error code
Bin Meng [Fri, 10 Jul 2015 02:38:32 +0000 (10:38 +0800)]
x86: Display correct CS/EIP/EFLAGS when there is an error code

Some exceptions cause an error code to be saved on the current stack
after the EIP value. We should extract CS/EIP/EFLAGS from different
position on the stack based on the exception number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Tue, 28 Jul 2015 15:31:21 +0000 (11:31 -0400)]
Merge branch 'zynq' of git://denx.de/git/u-boot-microblaze

9 years agocmd_mp: Add support for showing all CPU status by one command
Michal Simek [Mon, 22 Jun 2015 08:46:40 +0000 (10:46 +0200)]
cmd_mp: Add support for showing all CPU status by one command

Use one command for showing overall CPU status than several without
knowing how many cpus is available in the system.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
9 years agospi: zynq_spi: Simplify debug macro
Michal Simek [Tue, 21 Jul 2015 05:54:11 +0000 (07:54 +0200)]
spi: zynq_spi: Simplify debug macro

Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynq: Fix typo in Makefile about custom ps7_init file
Michal Simek [Tue, 21 Jul 2015 09:05:31 +0000 (11:05 +0200)]
zynq: Fix typo in Makefile about custom ps7_init file

Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agonet: gem: Extend timeout value
Michal Simek [Tue, 16 Oct 2012 15:37:11 +0000 (17:37 +0200)]
net: gem: Extend timeout value

Extend time for MDIO. (Because of zed board)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agozynqmp: Show EL level where U-Boot runs
Michal Simek [Mon, 22 Jun 2015 12:31:06 +0000 (14:31 +0200)]
zynqmp: Show EL level where U-Boot runs

Add one more print to make clear which EL level U-Boot runs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
9 years agoARM: zynqmp: Wire up SATA for the board
Michal Simek [Thu, 23 Jul 2015 11:27:40 +0000 (13:27 +0200)]
ARM: zynqmp: Wire up SATA for the board

Enable SATA for the ZynqMP targets.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>