oweals/u-boot.git
5 years agodoc: README.commands: sub-commands
Heinrich Schuchardt [Fri, 21 Dec 2018 01:57:03 +0000 (02:57 +0100)]
doc: README.commands: sub-commands

Describe the implementation of sub-commands.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agomt7629: use linux kernel compatible SMP initialization
Weijie Gao [Thu, 20 Dec 2018 08:12:50 +0000 (16:12 +0800)]
mt7629: use linux kernel compatible SMP initialization

This patch changes mt7629 to use the compatible platform SMP initialization
method of linux kernel.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
5 years agomt7623: fix a typo in include/configs/mt7623.h
Weijie Gao [Thu, 20 Dec 2018 08:12:49 +0000 (16:12 +0800)]
mt7623: fix a typo in include/configs/mt7623.h

Fix typo: neede -> needed

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
5 years agophy: Fix u-boot coruption when fixed-phy is used
Michal Simek [Wed, 19 Dec 2018 15:57:38 +0000 (16:57 +0100)]
phy: Fix u-boot coruption when fixed-phy is used

When fixed-link phy is used subnode offset is used as phy address. This
number is bigger then space allocated for bus structure (allocated via
mdio_alloc).
bus->phymap[] array has PHY_MAX_ADDR size (32).
That's why writing bus->phymap[addr] where addr is < 0 or > PHY_MAX_ADDR
is causing write to memory which can caused full U-Boot crash.

The patch is checking if address is in correct range.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm: K3: Fix usage of CONFIG_SYS_K3_KEY
Lokesh Vutla [Wed, 19 Dec 2018 07:23:31 +0000 (12:53 +0530)]
arm: K3: Fix usage of CONFIG_SYS_K3_KEY

For signing the tiboot3.bin image, an optional KEY file can be passed
using CONFIG_SYS_K3_KEY. Right now, Makefile scripts directly takes
the config value and uses it for signing. This is okay if the build
directory is a sub-directory of source tree, otherwise it fails.
Fix it by using the path relative to the source tree.

Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
5 years agoapi: storage: Fix enumeration of storage devices
Cristian Ciocaltea [Tue, 18 Dec 2018 18:03:49 +0000 (20:03 +0200)]
api: storage: Fix enumeration of storage devices

dev_stor_get() is not able to find the next available device in the current
storage group when the previous enumerated device belongs to a different
group or class (e.g. network).

The root cause is the device group iterator not being reset after an
unsuccessful search for the last returned device so that the following
search for the next available device will start from beginning.

The issue has been identified by loading and booting GRUB in a QEMU
vexpress-a9 environment.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@iquestgroup.com>
5 years agodm: pinctrl: Prevent (re-)configuring pins when already done before relocation
Lukasz Majewski [Tue, 18 Dec 2018 11:30:50 +0000 (12:30 +0100)]
dm: pinctrl: Prevent (re-)configuring pins when already done before relocation

This commit prevents from re-configuring pins if those were configured
before relocation.

Some pins - like UART or DDR must be setup before relocation
(as they have 'u-boot,dm-pre-reloc' property set in DTS). Without this
change, those pins are re-configured after relocation (pre_reloc_only = 0,
so we do not "continue").
Such behavior may be a problem for DDR PAD configuration, as they might
be already leveled/tuned with original setup).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
5 years agoARM: mach-omap2: omap3: Fix GPIO clocking in SPL
Adam Ford [Fri, 14 Dec 2018 22:28:30 +0000 (16:28 -0600)]
ARM: mach-omap2: omap3: Fix GPIO clocking in SPL

OMAP3_GPIO_x is needed to enable each GPIO bank on the OMAP3
boards. At one point, the #ifdef's were replaced with
if CONFIG_IS_ENABLED but this won't work for people who need
OMAP3_GPIO_x in SPL since the SPL prefix for this option isn't
used in Kconfig.  This patch moves the check to #if defined and
also makes Kconfig select the banks if CMD_GPIO is used which
makes the checks in the code less cumbersome.

Fixes: bd8a9c14c91c ("arm: mach-omap2/omap3/clock.c: Enable
all GPIO with CMD_GPIO")

Reported-by: Liam O'Shaughnessy <liam.o.shaughnessy@gumstix.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Migrate omap3_igep00x0.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agotests: enable DT overlay tests by default
Heinrich Schuchardt [Fri, 14 Dec 2018 21:43:48 +0000 (22:43 +0100)]
tests: enable DT overlay tests by default

Enable device tree overlay tests by default if unit tests are selected
and the runtime is configured via device tree.

Overlays have been mainlined in the device tree compiler so there is no
reason anymore to disable the tests by default.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoscripts/check-config.sh: Add usage()
Andy Shevchenko [Tue, 11 Dec 2018 16:22:28 +0000 (18:22 +0200)]
scripts/check-config.sh: Add usage()

When arguments are not supplied the error message is misleading and
doesn't tell what exactly has to be done.

Fix this by adding usage() and call it if above circumstance occurs.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agoMerge git://git.denx.de/u-boot-marvell
Tom Rini [Fri, 21 Dec 2018 18:38:09 +0000 (13:38 -0500)]
Merge git://git.denx.de/u-boot-marvell

- Fix breakage in helios4: Change U-Boot offset on SPI Flash
- Enable CONFIG_BLK for db-88f6820-amc

5 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Fri, 21 Dec 2018 18:37:34 +0000 (13:37 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- stratix10 updates

5 years agoMerge tag 'u-boot-amlogic-20181219' of git://git.denx.de/u-boot-amlogic
Tom Rini [Fri, 21 Dec 2018 18:37:09 +0000 (13:37 -0500)]
Merge tag 'u-boot-amlogic-20181219' of git://git.denx.de/u-boot-amlogic

A single fix to properly enable eMMC on the AXG S400 board.

5 years agoMerge tag 'mips-updates-for-2019.11' of git://git.denx.de/u-boot-mips
Tom Rini [Fri, 21 Dec 2018 18:36:51 +0000 (13:36 -0500)]
Merge tag 'mips-updates-for-2019.11' of git://git.denx.de/u-boot-mips

- mips: fix some DTC warnings
- bmips: bcm6348: add DMA driver
- bmips: bcm5348: add ethernet driver
- bmips: bcm6368: add ethernet driver
- mips: mt76xx: fix DMA problems, disable CONFIG_OF_EMBED
- mips: mscc: add support for Microsemi Ocelot and Luton SoCs
- mips: mscc: add support for Ocelot and Luton evaluation boards
- mips: jz47xx: add basic support for Ingenic JZ4780 SoC
- mips: jz47xx: add support for Imgtec Creator CI20 board

5 years agoMerge git://git.denx.de/u-boot-riscv
Tom Rini [Fri, 21 Dec 2018 18:36:08 +0000 (13:36 -0500)]
Merge git://git.denx.de/u-boot-riscv

- Add DM drivers to support RISC-V CPU and timer, plus some bug fixes.
- Support SiFive UART
- Rename ax25-ae350 defconfig

5 years agoarm: mvebu: configs: helios4: Change U-Boot offset on SPI Flash
Aditya Prayoga [Wed, 19 Dec 2018 04:08:50 +0000 (12:08 +0800)]
arm: mvebu: configs: helios4: Change U-Boot offset on SPI Flash

SPI flash support on Helios4 [1] has been merge to u-boot/master on
commit 8cb8c0c6a83bef ("Merge git://git.denx.de/u-boot-marvell")

However, the SPI image build failed after the merge with following
message:

COPY    spl/u-boot-spl.bin
MKIMAGE u-boot-spl.kwb
Error: Image header (incl. SPL image) too big!
header=0x20816 CONFIG_SYS_U_BOOT_OFFS=0x20000!
Increase CONFIG_SYS_U_BOOT_OFFS!
Error: Image header (incl. SPL image) too big!
header=0x20816 CONFIG_SYS_U_BOOT_OFFS=0x20000!
Increase CONFIG_SYS_U_BOOT_OFFS!
Could not create image
Makefile:1162: recipe for target 'u-boot-spl.kwb' failed
make: *** [u-boot-spl.kwb] Error 1

Let's increase the u-boot offset to 0x30000 to accommodate SPL changes
and leave some margin for future changes.

[1] https://patchwork.ozlabs.org/patch/1007762/

Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoARM: mvebu: remove out of date comment
Chris Packham [Fri, 14 Dec 2018 03:27:57 +0000 (16:27 +1300)]
ARM: mvebu: remove out of date comment

The Marvell DDR3 training code is now part of the U-Boot SPL so the
comment saying it needs porting is no longer correct.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoARM: mvebu: define CONFIG_BLK for db-88f6820-amc
Chris Packham [Fri, 7 Dec 2018 03:19:42 +0000 (16:19 +1300)]
ARM: mvebu: define CONFIG_BLK for db-88f6820-amc

db-88f6820-amc uses CONFIG_DM_USB and CONFIG_USB_STORAGE already so
define CONFIG_BLK to prepare it for full conversion to DM.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration
Ang, Chee Hong [Thu, 20 Dec 2018 02:35:16 +0000 (18:35 -0800)]
arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration

Select CONFIG_FPGA_STRATIX10 for CONFIG_TARGET_SOCFPGA_STRATIX10.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
5 years agoarm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
Ang, Chee Hong [Thu, 20 Dec 2018 02:35:15 +0000 (18:35 -0800)]
arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
5 years agoarm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver
Ang, Chee Hong [Thu, 20 Dec 2018 02:35:14 +0000 (18:35 -0800)]
arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver

Enable FPGA reconfiguration support for Stratix 10 SoC.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
5 years agoarm: socfpga: stratix10: Add macros for mailbox's arguments
Ang, Chee Hong [Thu, 20 Dec 2018 02:35:13 +0000 (18:35 -0800)]
arm: socfpga: stratix10: Add macros for mailbox's arguments

Add macros for specifying number of arguments in mailbox command.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
5 years agoarm: socfpga: stratix10: Add generic FPGA reconfig mailbox API for S10
Ang, Chee Hong [Thu, 20 Dec 2018 02:35:12 +0000 (18:35 -0800)]
arm: socfpga: stratix10: Add generic FPGA reconfig mailbox API for S10

Add a generic mailbox API for FPGA reconfig status which can be
called by others. This new function accepts 2 different mailbox
commands: CONFIG_STATUS or RECONFIG_STATUS.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
5 years agoarm: dts: s400: Fix status for eMMC and SDIO ports
Neil Armstrong [Mon, 17 Dec 2018 09:26:16 +0000 (10:26 +0100)]
arm: dts: s400: Fix status for eMMC and SDIO ports

Under U-boot, the WiFi SDIO Module should be disabled and the
eMMC modules should be enabled, so this patch adds an s400-u-boot.dtsi
include file specific for U-Boot that will be included by the build system.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
5 years agomips: jz47xx: Add Creator CI20 platform
Paul Burton [Sun, 16 Dec 2018 22:25:23 +0000 (19:25 -0300)]
mips: jz47xx: Add Creator CI20 platform

Add support for the Creator CI20 platform based on the JZ4780 SoC.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Marek Vasut <marex@denx.de>
5 years agomips: jz47xx: Add JZ4780 SoC support
Paul Burton [Sun, 16 Dec 2018 22:25:22 +0000 (19:25 -0300)]
mips: jz47xx: Add JZ4780 SoC support

Add initial support for the Ingenic JZ47xx MIPS SoC.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Marek Vasut <marex@denx.de>
5 years agomips: Add SPL header
Paul Burton [Sun, 16 Dec 2018 22:25:21 +0000 (19:25 -0300)]
mips: Add SPL header

Add header with SPL boot mode and type definitions.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
5 years agommc: Add JZ47xx SD/MMC controller driver
Paul Burton [Sun, 16 Dec 2018 22:25:20 +0000 (19:25 -0300)]
mmc: Add JZ47xx SD/MMC controller driver

Add driver for the JZ47xx MSC controller.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Marek Vasut <marex@denx.de>
5 years agomisc: Add JZ47xx efuse driver
Paul Burton [Sun, 16 Dec 2018 22:25:19 +0000 (19:25 -0300)]
misc: Add JZ47xx efuse driver

Add driver for the efuse block in the JZ47xx SOC.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Marek Vasut <marex@denx.de>
5 years agoMSCC: add board support for the Luton based evaluation board
Gregory CLEMENT [Fri, 14 Dec 2018 15:16:50 +0000 (16:16 +0100)]
MSCC: add board support for the Luton based evaluation board

Adding the support for the Luton boards PCB91 which share common code with
the Ocelots boards, including board code, device tree and configuration.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
5 years agoMSCC: add board support for the Ocelots based evaluation boards
Gregory CLEMENT [Fri, 14 Dec 2018 15:16:49 +0000 (16:16 +0100)]
MSCC: add board support for the Ocelots based evaluation boards

Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
5 years agoMSCC: add support for Luton SoCs
Gregory CLEMENT [Fri, 14 Dec 2018 15:16:48 +0000 (16:16 +0100)]
MSCC: add support for Luton SoCs

As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
5 years agoMSCC: add support for Ocelot SoCs
Gregory CLEMENT [Fri, 14 Dec 2018 15:16:47 +0000 (16:16 +0100)]
MSCC: add support for Ocelot SoCs

This family of SoCs are found in the Microsemi Switches solution and have
already a support in the linux kernel.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
5 years agoMIPS: Allow to prefetch and lock instructions into cache
Gregory CLEMENT [Fri, 14 Dec 2018 15:16:46 +0000 (16:16 +0100)]
MIPS: Allow to prefetch and lock instructions into cache

This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
5 years agoMIPS: move create_tlb() in an proper header: mipsregs.h
Gregory CLEMENT [Fri, 14 Dec 2018 15:16:45 +0000 (16:16 +0100)]
MIPS: move create_tlb() in an proper header: mipsregs.h

Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.

Then it will allow also to use this function very early in the boot when
the stack is not usable.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
5 years agoMIPS: remove local_irq_[save|restore] from CP0 macros
Daniel Schwierzeck [Wed, 19 Dec 2018 14:18:52 +0000 (15:18 +0100)]
MIPS: remove local_irq_[save|restore] from CP0 macros

With moving write_on_tlb() to arch/mips/include/asm/mipsregs.h
there are now compiler warnings when some generic code includes
asm/io.h. This happens for example when enabling OF live tree.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agogpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi
Gregory CLEMENT [Tue, 9 Oct 2018 12:08:42 +0000 (14:08 +0200)]
gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi

The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.

Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver, the management of this pin
is done through this simple gpio driver.

Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agopinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)
Gregory CLEMENT [Sat, 8 Dec 2018 08:59:01 +0000 (09:59 +0100)]
pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)

This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.

The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).

For Ocelot and Luton the controller is the same, only the pins to program
differ.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agoDW SPI: Allow to overload the management of the external CS
Gregory CLEMENT [Tue, 9 Oct 2018 12:14:07 +0000 (14:14 +0200)]
DW SPI: Allow to overload the management of the external CS

On some platforms, as the Ocelot ones, when wanting to control the CS
through software, it is not possible to do it through the GPIO
controller. Indeed, this signal is managed through a dedicated range of
registers inside the SoC..

By declaring the external_cs_manage function as weak, it is possible to
manage the CS at platform level and then using the appropriate registers.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
5 years agomips: mt76xx: linkit/gardena: Don't use CONFIG_OF_EMBED
Stefan Roese [Tue, 18 Dec 2018 09:27:15 +0000 (10:27 +0100)]
mips: mt76xx: linkit/gardena: Don't use CONFIG_OF_EMBED

Building with CONFIG_OF_EMBED generates build warnings, as it should
only be used for debugging purposes. So let's move all MT7688 targets to
CONFIG_OF_SEPARATE instead with this patch.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agomips: mt76xx: Flush d-cache in arch_misc_init() to solve d-cache issues
Stefan Roese [Tue, 18 Dec 2018 09:27:14 +0000 (10:27 +0100)]
mips: mt76xx: Flush d-cache in arch_misc_init() to solve d-cache issues

It has been noticed, that sometimes the d-cache is not in a
"clean-state" when U-Boot is running on MT7688. This was detected when
using the ethernet driver (which uses d-cache) and a TFTP command does
not complete. Flushing the complete d-cache (again?) here seems to fix
this issue.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agomips: xilfpga: fix DTC warnings
Daniel Schwierzeck [Sat, 15 Dec 2018 18:19:33 +0000 (19:19 +0100)]
mips: xilfpga: fix DTC warnings

This fixes following DTC warning:

arch/mips/dts/nexys4ddr.dtb: Warning (compatible_is_string_list): /ethernet@10e00000/mdio/phy@1:compatible: property is not a string list

As upstream DTS in Linux doesn't have the offending property,
simply remove it to fix the warning.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agomips: ath79: fix DTC warnings
Daniel Schwierzeck [Sat, 15 Dec 2018 18:05:08 +0000 (19:05 +0100)]
mips: ath79: fix DTC warnings

Remove all interrupt nodes that cause warnings regarding a missing
interrupt parent. There are no interrupt controller nodes defined
and the device trees don't match the ones in Linux anymore.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agobmips: enable ar-5315u enet support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:42 +0000 (19:00 +0100)]
bmips: enable ar-5315u enet support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6318: add support for bcm6368-enet
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:41 +0000 (19:00 +0100)]
bmips: bcm6318: add support for bcm6368-enet

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: enable vr-3032u enet support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:40 +0000 (19:00 +0100)]
bmips: enable vr-3032u enet support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm63268: add support for bcm6368-enet
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:39 +0000 (19:00 +0100)]
bmips: bcm63268: add support for bcm6368-enet

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: enable dgnd3700v2 enet support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:38 +0000 (19:00 +0100)]
bmips: enable dgnd3700v2 enet support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6362: add support for bcm6368-enet
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:37 +0000 (19:00 +0100)]
bmips: bcm6362: add support for bcm6368-enet

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: enable ar-5387un enet support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:36 +0000 (19:00 +0100)]
bmips: enable ar-5387un enet support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6328: add support for bcm6368-enet
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:35 +0000 (19:00 +0100)]
bmips: bcm6328: add support for bcm6368-enet

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: enable wap-5813n enet support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:34 +0000 (19:00 +0100)]
bmips: enable wap-5813n enet support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6368: add support for bcm6368-enet
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:33 +0000 (19:00 +0100)]
bmips: bcm6368: add support for bcm6368-enet

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agonet: add support for bcm6368-enet
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:32 +0000 (19:00 +0100)]
net: add support for bcm6368-enet

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agobmips: enable nb4-ser enet support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:31 +0000 (19:00 +0100)]
bmips: enable nb4-ser enet support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: enable hg556a enet support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:30 +0000 (19:00 +0100)]
bmips: enable hg556a enet support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6358: add support for bcm6348-enet
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:29 +0000 (19:00 +0100)]
bmips: bcm6358: add support for bcm6348-enet

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: enable ct-5361 enet support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:28 +0000 (19:00 +0100)]
bmips: enable ct-5361 enet support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6348: add support for bcm6348-enet
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:27 +0000 (19:00 +0100)]
bmips: bcm6348: add support for bcm6348-enet

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: enable f@st1704 enet support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:26 +0000 (19:00 +0100)]
bmips: enable f@st1704 enet support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6338: add support for bcm6348-enet
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:25 +0000 (19:00 +0100)]
bmips: bcm6338: add support for bcm6348-enet

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agonet: add support for bcm6348-enet
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:24 +0000 (19:00 +0100)]
net: add support for bcm6348-enet

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agobmips: bcm6318: add bcm6348-iudma support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:23 +0000 (19:00 +0100)]
bmips: bcm6318: add bcm6348-iudma support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm63268: add bcm6348-iudma support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:22 +0000 (19:00 +0100)]
bmips: bcm63268: add bcm6348-iudma support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6362: add bcm6348-iudma support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:21 +0000 (19:00 +0100)]
bmips: bcm6362: add bcm6348-iudma support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6328: add bcm6348-iudma support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:20 +0000 (19:00 +0100)]
bmips: bcm6328: add bcm6348-iudma support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6368: add bcm6348-iudma support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:19 +0000 (19:00 +0100)]
bmips: bcm6368: add bcm6348-iudma support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6358: add bcm6348-iudma support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:18 +0000 (19:00 +0100)]
bmips: bcm6358: add bcm6348-iudma support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6348: add bcm6348-iudma support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:17 +0000 (19:00 +0100)]
bmips: bcm6348: add bcm6348-iudma support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agobmips: bcm6338: add bcm6348-iudma support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:16 +0000 (19:00 +0100)]
bmips: bcm6338: add bcm6348-iudma support

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
5 years agodma: add bcm6348-iudma support
Álvaro Fernández Rojas [Sat, 1 Dec 2018 18:00:15 +0000 (19:00 +0100)]
dma: add bcm6348-iudma support

BCM6348 IUDMA controller is present on multiple BMIPS (BCM63xx) SoCs.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agodoc: README.ae350: Sync for ax25-ae350 rename
Rick Chen [Tue, 18 Dec 2018 02:48:55 +0000 (10:48 +0800)]
doc: README.ae350: Sync for ax25-ae350 rename

Rename ax25-ae350 as ae350_rv[32|64] for 32 or 64 bit.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: configs: Rename ax25-ae350 defconfig
Rick Chen [Tue, 18 Dec 2018 03:02:27 +0000 (11:02 +0800)]
riscv: configs: Rename ax25-ae350 defconfig

Remove cpu name from the defconfig naming.
Because other cpus maybe run on AE350 platform.
So only use platfrom name in defconfig naming
will be better.

Also sync MAINTAINERS:
Rename
a25-ae350_32_defconfig as ae350_rv32_defconfig
ax25-ae350_64_defconfig as ae350_rv64_defconfig

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: qemu: Imply SIFIVE_SERIAL for emulation
Anup Patel [Sat, 15 Dec 2018 06:05:16 +0000 (11:35 +0530)]
riscv: qemu: Imply SIFIVE_SERIAL for emulation

This patch enables SiFive UART driver for QEMU RISC-V emulation
by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
5 years agodrivers: serial: Add SiFive UART driver
Anup Patel [Sat, 15 Dec 2018 06:05:15 +0000 (11:35 +0530)]
drivers: serial: Add SiFive UART driver

This patch adds SiFive UART driver. The driver is 100% DM driver
and it determines input clock using clk framework.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: Remove ae350.dts
Bin Meng [Wed, 12 Dec 2018 14:12:47 +0000 (06:12 -0800)]
riscv: Remove ae350.dts

This is not used by any board. Remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: bootm: Change to use boot_hart from global data
Bin Meng [Wed, 12 Dec 2018 14:12:46 +0000 (06:12 -0800)]
riscv: bootm: Change to use boot_hart from global data

Avoid reading mhartid CSR directly, instead use the one we saved
in the global data structure before.

With this patch, BBL no longer needs to be hacked to provide the
mhartid CSR emulation for S-mode U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Save boot hart id to the global data
Bin Meng [Wed, 12 Dec 2018 14:12:45 +0000 (06:12 -0800)]
riscv: Save boot hart id to the global data

At present the hart id passed via a0 in the U-Boot entry is saved
to s0 at the beginning but does not preserve later. Save it to the
global data structure so that it can be used later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Adjust the _exit_trap() position to come before handle_trap()
Bin Meng [Wed, 12 Dec 2018 14:12:44 +0000 (06:12 -0800)]
riscv: Adjust the _exit_trap() position to come before handle_trap()

With this change, we can avoid a forward declaration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Return to previous privilege level after trap handling
Bin Meng [Wed, 12 Dec 2018 14:12:43 +0000 (06:12 -0800)]
riscv: Return to previous privilege level after trap handling

At present the trap handler returns to hardcoded M-mode/S-mode.
Change to returning to previous privilege level instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Fix context restore before returning from trap handler
Bin Meng [Wed, 12 Dec 2018 14:12:42 +0000 (06:12 -0800)]
riscv: Fix context restore before returning from trap handler

sp cannot be loaded before restoring other registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Move trap handler codes to mtrap.S
Bin Meng [Wed, 12 Dec 2018 14:12:41 +0000 (06:12 -0800)]
riscv: Move trap handler codes to mtrap.S

Currently the M-mode trap handler codes are in start.S. For future
extension, move them to a separate file mtrap.S.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Do some basic architecture level cpu initialization
Bin Meng [Wed, 12 Dec 2018 14:12:40 +0000 (06:12 -0800)]
riscv: Do some basic architecture level cpu initialization

In arch_cpu_init_dm() do some basic architecture level cpu
initialization, like FPU enable, etc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Add indirect stringification to csr_xxx ops
Bin Meng [Wed, 12 Dec 2018 14:12:39 +0000 (06:12 -0800)]
riscv: Add indirect stringification to csr_xxx ops

With current csr_xxx ops, we cannot pass a macro to parameter
'csr', hence we need add another level to allow the parameter
to be a macro itself, aka indirect stringification.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Update supports_extension() to use desc from cpu driver
Bin Meng [Wed, 12 Dec 2018 14:12:38 +0000 (06:12 -0800)]
riscv: Update supports_extension() to use desc from cpu driver

This updates supports_extension() implementation to use the desc
string from the cpu driver whenever possible, which avoids the
reading of misa CSR for S-mode U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Add exception codes for xcause register
Bin Meng [Wed, 12 Dec 2018 14:12:37 +0000 (06:12 -0800)]
riscv: Add exception codes for xcause register

This adds all exception codes in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Add CSR numbers
Bin Meng [Wed, 12 Dec 2018 14:12:36 +0000 (06:12 -0800)]
riscv: Add CSR numbers

The standard RISC-V ISA sets aside a 12-bit encoding space for up
to 4096 CSRs. This adds all known CSR numbers as defined in the
RISC-V Privileged Architecture Version 1.10.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Remove non-DM version of print_cpuinfo()
Bin Meng [Wed, 12 Dec 2018 14:12:35 +0000 (06:12 -0800)]
riscv: Remove non-DM version of print_cpuinfo()

With DM CPU driver, the non-DM version of print_cpuinfo() is no
longer needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Probe cpus during boot
Bin Meng [Wed, 12 Dec 2018 14:12:34 +0000 (06:12 -0800)]
riscv: Probe cpus during boot

This calls cpu_probe_all() to probe all available cpus.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Enlarge the default SYS_MALLOC_F_LEN
Bin Meng [Wed, 12 Dec 2018 14:12:33 +0000 (06:12 -0800)]
riscv: Enlarge the default SYS_MALLOC_F_LEN

Increase the heap size for the pre-relocation stage, so that CPU
driver can be loaded.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: qemu: Add platform-specific Kconfig options
Bin Meng [Wed, 12 Dec 2018 14:12:32 +0000 (06:12 -0800)]
riscv: qemu: Add platform-specific Kconfig options

Add the QEMU RISC-V platform-specific Kconfig options, to include
CPU and timer drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Implement riscv_get_time() API using rdtime instruction
Anup Patel [Wed, 12 Dec 2018 14:12:31 +0000 (06:12 -0800)]
riscv: Implement riscv_get_time() API using rdtime instruction

This adds an implementation of riscv_get_time() API that is using
rdtime instruction.

This is the case for S-mode U-Boot, and is useful for processors
that support rdtime in M-mode too.

Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
5 years agoriscv: Add a SYSCON driver for SiFive's Core Local Interruptor
Bin Meng [Wed, 12 Dec 2018 14:12:30 +0000 (06:12 -0800)]
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor

This adds U-Boot syscon driver for SiFive's Core Local Interruptor
(CLINT). The CLINT block holds memory-mapped control and status
registers associated with software and timer interrupts.

This driver implements the riscv_get_time() API as required by
the generic RISC-V timer driver, as well as some other APIs that
are needed for handling IPI.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: Introduce a Kconfig option for machine mode
Anup Patel [Wed, 12 Dec 2018 14:12:29 +0000 (06:12 -0800)]
riscv: Introduce a Kconfig option for machine mode

So far we have a Kconfig option for supervisor mode. This adds an
option for the machine mode.

Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
5 years agoriscv: ax25: Hide the ax25-specific Kconfig option
Bin Meng [Wed, 12 Dec 2018 14:12:28 +0000 (06:12 -0800)]
riscv: ax25: Hide the ax25-specific Kconfig option

There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agotimer: Add generic driver for RISC-V privileged architecture defined timer
Bin Meng [Wed, 12 Dec 2018 14:12:27 +0000 (06:12 -0800)]
timer: Add generic driver for RISC-V privileged architecture defined timer

RISC-V privileged architecture v1.10 defines a real-time counter,
exposed as a memory-mapped machine-mode register - mtime. mtime must
run at constant frequency, and the platform must provide a mechanism
for determining the timebase of mtime. The mtime register has a
64-bit precision on all RV32, RV64, and RV128 systems.

Different platform may have different implementation of the mtime
block hence an API riscv_get_time() is required by this driver for
platform codes to hide such implementation details. For example,
on some platforms mtime is provided by the CLINT module, while on
some other platforms a simple 'rdtime' can be used to get the timer
counter.

With this timer driver the U-Boot timer functionalities like delay
works correctly now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agocpu: Add a RISC-V CPU driver
Bin Meng [Wed, 12 Dec 2018 14:12:26 +0000 (06:12 -0800)]
cpu: Add a RISC-V CPU driver

This adds a driver for RISC-V CPU. Note the driver will bind
a RISC-V timer driver if "timebase-frequency" property is
present in the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: qemu: Create a simple-bus driver for the soc node
Bin Meng [Wed, 12 Dec 2018 14:12:25 +0000 (06:12 -0800)]
riscv: qemu: Create a simple-bus driver for the soc node

To enumerate devices on the /soc/ node, create a "simple-bus"
driver to match "riscv-virtio-soc".

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agodm: cpu: Add timebase frequency to the platdata
Bin Meng [Wed, 12 Dec 2018 14:12:24 +0000 (06:12 -0800)]
dm: cpu: Add timebase frequency to the platdata

This adds a timebase_freq member to the 'struct cpu_platdata', to
hold the "timebase-frequency" value in the cpu or /cpus node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
5 years agoriscv: add Kconfig entries for the code model
Lukas Auer [Wed, 12 Dec 2018 14:12:23 +0000 (06:12 -0800)]
riscv: add Kconfig entries for the code model

RISC-V has two code models, medium low (medlow) and medium any (medany).
Medlow limits addressable memory to a single 2 GiB range between the
absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory
to any single 2 GiB address range.

By default, medlow is selected for U-Boot on both 32-bit and 64-bit
systems.

The -mcmodel compiler flag is selected according to the Kconfig
configuration.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
[bmeng: adjust to make medlow the default code model for U-Boot]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>