oweals/u-boot.git
6 years agommc: k3_arasan: Add sdhci driver support for K3 family SoCs
Lokesh Vutla [Mon, 27 Aug 2018 10:27:54 +0000 (15:57 +0530)]
mmc: k3_arasan: Add sdhci driver support for K3 family SoCs

AM654 has an arasan sdhci controller and a mmc phy attached to it.
Add basic support for K3 specific arasan sdhci controller.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agospl: Allow remoteproc drivers to be used within SPL
Lokesh Vutla [Mon, 27 Aug 2018 10:27:53 +0000 (15:57 +0530)]
spl: Allow remoteproc drivers to be used within SPL

Add an option for building remoteproc drivers within SPL.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoremoteproc: Introduce K3 remoteproc driver
Lokesh Vutla [Mon, 27 Aug 2018 10:27:52 +0000 (15:57 +0530)]
remoteproc: Introduce K3 remoteproc driver

Add support for K3 based remoteproc driver that
communicates with TISCI to start start a remote processor.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoremoteproc: Introduce K3 system controller
Lokesh Vutla [Mon, 27 Aug 2018 10:27:51 +0000 (15:57 +0530)]
remoteproc: Introduce K3 system controller

K3 specific SoCs have a dedicated microcontroller for doing
resource management. Any HLOS/firmware on compute clusters should
load a firmware to this microcontroller before accessing any resource.
Adding support for loading this firmware.

After the K3 system controller got loaded with firmware and started
up it sends out a boot notification message through the secure proxy
facility using the TI SCI protocol. Intercept and receive this message
through the rproc start operation which will need to get invoked
explicitly after the firmware got loaded.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
6 years agoremoteproc: Allow for individual remoteproc initialization
Lokesh Vutla [Mon, 27 Aug 2018 10:27:50 +0000 (15:57 +0530)]
remoteproc: Allow for individual remoteproc initialization

Existing rproc_init() api tries to initialize all available
remoteproc devices. This will fail when there is dependency
among available remoteprocs. So introduce a separate api
that allows to initialize remoteprocs individually based
on id.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agospl: Allow mailbox drivers to be used within SPL
Lokesh Vutla [Mon, 27 Aug 2018 10:27:49 +0000 (15:57 +0530)]
spl: Allow mailbox drivers to be used within SPL

Add an option for building mailbox drivers within SPL.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agomailbox: Introduce K3 Secure Proxy Driver
Lokesh Vutla [Mon, 27 Aug 2018 10:27:48 +0000 (15:57 +0530)]
mailbox: Introduce K3 Secure Proxy Driver

Secure Proxy module manages hardware threads that are meant
for communication between the processor entities. Adding
support for this driver.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
6 years agomailbox: Allow attaching private data for mbox_chan
Lokesh Vutla [Mon, 27 Aug 2018 10:27:47 +0000 (15:57 +0530)]
mailbox: Allow attaching private data for mbox_chan

Sometimes mbox controllers wants to store private data in
mbox_chan so that it can be used at a later point of time.
Adding support for hooking private data.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agosysreset: Add TI System Control Interface (TI SCI) sysreset driver
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:46 +0000 (15:57 +0530)]
sysreset: Add TI System Control Interface (TI SCI) sysreset driver

Devices from the TI K3 family of SoCs like the AM654x contain a Device
Management and Security Controller (SYSFW) that manages the low-level
device control (like clocks, resets etc) for the various hardware
modules present on the SoC. These device control operations are provided
to the host processor OS through a communication protocol called the TI
System Control Interface (TI SCI) protocol.

This patch adds a system reset driver that communicates to the system
controller over the TI SCI protocol for allowing to perform a system-
wide SoC reset.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agopower domain: Introduce TI System Control Interface (TI SCI) power domain driver
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:45 +0000 (15:57 +0530)]
power domain: Introduce TI System Control Interface (TI SCI) power domain driver

Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a power domain driver that communicates to the system
controller over the TI SCI protocol for performing power management of
various devices present on the SoC. Various power domain functionalities
are achieved by the means of different TI SCI device operations provided
by the TI SCI framework.

This code is loosely based on the drivers/soc/ti/ti_sci_pm_domains.c
driver of the Linux kernel.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agopower domain: Add support for multiple powerdomains per device
Lokesh Vutla [Mon, 27 Aug 2018 10:27:44 +0000 (15:57 +0530)]
power domain: Add support for multiple powerdomains per device

There are cases where there are more than one power domain
attached to the device inorder to get the device functional.
So add support for enabling power domain based on the index.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoclk: Introduce TI System Control Interface (TI SCI) clock driver
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:43 +0000 (15:57 +0530)]
clk: Introduce TI System Control Interface (TI SCI) clock driver

Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a clock driver that communicates to the system
controller over the TI SCI protocol for performing clock management of
various devices present on the SoC. Various clock functionality is
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.

This code is loosely based on the drivers/clk/keystone/sci-clk.c driver
of the Linux kernel.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoclk: Extend clock control with an optional data field
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:42 +0000 (15:57 +0530)]
clk: Extend clock control with an optional data field

Some systems require more than a single ID to identify and configure any
clock provider. For those scenarios add an optional data field to the
clock control structure.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoreset: Introduce TI System Control Interface (TI SCI) reset driver
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:41 +0000 (15:57 +0530)]
reset: Introduce TI System Control Interface (TI SCI) reset driver

Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a reset driver that communicates to the system
controller over the TI SCI protocol for performing reset management of
various devices present on the SoC. Various reset functionalities are
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.

This code is loosely based on the drivers/reset/reset-ti-sci.c driver of
the Linux kernel.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoreset: Extend reset control with an optional data field
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:40 +0000 (15:57 +0530)]
reset: Extend reset control with an optional data field

Some systems require more than a single ID to identify and configure any
reset provider. For those scenarios add an optional data field to the
reset control structure.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agodm: reset: Update uclass to allow querying reset status
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:39 +0000 (15:57 +0530)]
dm: reset: Update uclass to allow querying reset status

Add a reset operations function pointer to support querying the current
status of a reset control.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agodm: firmware: Automatically bind child devices
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:38 +0000 (15:57 +0530)]
dm: firmware: Automatically bind child devices

To support scenarios where a firmware device node has subnodes that
have their own drivers automatically scan the DT and bind those when
the firmware device gets bound.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agofirmware: ti_sci: Add support for processor control services
Lokesh Vutla [Mon, 27 Aug 2018 10:27:37 +0000 (15:57 +0530)]
firmware: ti_sci: Add support for processor control services

TI-SCI message protocol provides support for controlling of various
physical cores available in SoC. In order to control which host is
capable of controlling a physical processor core, there is a processor
access control list that needs to be populated as part of the board
configuration data.

Introduce support for the set of TI-SCI message protocol apis that
provide us with this capability of controlling physical cores.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agofirmware: ti_sci: Add support for reboot core service
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:36 +0000 (15:57 +0530)]
firmware: ti_sci: Add support for reboot core service

Since system controller now has control over SoC power management, it
needs to be explicitly requested to reboot the SoC. Add support for
it.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
6 years agofirmware: ti_sci: Add support for clock control
Lokesh Vutla [Mon, 27 Aug 2018 10:27:35 +0000 (15:57 +0530)]
firmware: ti_sci: Add support for clock control

In general, we expect to function at a device level of abstraction,
however, for proper operation of hardware blocks, many clocks directly
supplying the hardware block needs to be queried or configured.

Introduce support for the set of SCI message protocol support that
provide us with this capability.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
6 years agofirmware: ti_sci: Add support for device control
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:34 +0000 (15:57 +0530)]
firmware: ti_sci: Add support for device control

TI-SCI message protocol provides support for management of various
hardware entitites within the SoC. Introduce the fundamental
device management capability support to the driver protocol
as part of this change.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
6 years agofirmware: ti_sci: Add support for board configuration
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:33 +0000 (15:57 +0530)]
firmware: ti_sci: Add support for board configuration

TI-SCI message protocol provides support for board configuration
to assign resources and other board related operations.
Introduce the board configuration capability support to the driver protocol
as part of this change.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agofirmware: Add basic support for TI System Control Interface (TI SCI) protocol
Lokesh Vutla [Mon, 27 Aug 2018 10:27:32 +0000 (15:57 +0530)]
firmware: Add basic support for TI System Control Interface (TI SCI) protocol

Texas Instrument's System Control Interface (TI SCI) message protocol is
used in Texas Instrument's System on Chip (SoC) such as those in the K3
family AM654 SoC to communicate between various compute processors with
a central system controller entity.

The TI SCI message protocol provides support for management of various
hardware entities within the SoC. Add support driver to allow
communication with system controller entity within the SoC using the
mailbox client.

This is mostly derived from the TI SCI driver in Linux located at
drivers/firmware/ti_sci.c.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
6 years agoarmv8: K3: am654: Add support for generating build targets
Lokesh Vutla [Mon, 27 Aug 2018 10:27:15 +0000 (15:57 +0530)]
armv8: K3: am654: Add support for generating build targets

Update Makefile to generate
- tispl.bin: First stage bootloader on ARMv8 core
- u-boot.img: Second stage bootloader on ARMv8 core.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoarmv8: K3: am654: Introduce FIT generator script
Lokesh Vutla [Mon, 27 Aug 2018 10:27:14 +0000 (15:57 +0530)]
armv8: K3: am654: Introduce FIT generator script

Add a script that is capable of generating a FIT image
source file that combines ATF, SPL(64 bit) and DT.
This combined image is used by R5 SPL and start ATF
on ARMv8 core.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
6 years agoarmv8: K3: am654: Add custom MMU support
Lokesh Vutla [Mon, 27 Aug 2018 10:27:13 +0000 (15:57 +0530)]
armv8: K3: am654: Add custom MMU support

Add MMU mappings for AM654 SoC.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoarm: K3: am654: Unlock control module registers during init
Andreas Dannenberg [Mon, 27 Aug 2018 10:27:12 +0000 (15:57 +0530)]
arm: K3: am654: Unlock control module registers during init

By default the device control module registers are locked,
preventing any writes to its registers.
Unlock those registers as part of the init flow.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoarm: K3: am654: Add support for boot device detection
Lokesh Vutla [Mon, 27 Aug 2018 10:27:11 +0000 (15:57 +0530)]
arm: K3: am654: Add support for boot device detection

AM654 allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
6 years agoarm: K3: Update _start instruction
Lokesh Vutla [Mon, 27 Aug 2018 10:27:10 +0000 (15:57 +0530)]
arm: K3: Update _start instruction

On K3 family SoCs, once the ROM loads image on R5, M3 resets R5 and
expects to start executing from 0x0. In order to handle this ROM
updates the boot vector of R5 such that first 64 bytes of image load
address are mapped to 0x0.

In this case, it is SPL's responsibility to jump to the proper image
location. So, update the PC with address of reset vector(like how
other exception vectors are handled), instead of branching to reset.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agoarm: K3: Add support for AM654 SoC definition
Lokesh Vutla [Mon, 27 Aug 2018 10:27:09 +0000 (15:57 +0530)]
arm: K3: Add support for AM654 SoC definition

The AM654 device is designed for industrial automation and PLC
controller class platforms among other applications. Introduce
base support for AM654 SoC.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
6 years agoarm: K3: Add initial support for TI's K3 generation of SoCs
Lokesh Vutla [Mon, 27 Aug 2018 10:27:08 +0000 (15:57 +0530)]
arm: K3: Add initial support for TI's K3 generation of SoCs

Add support for Texas Instruments' K3 Generation Processor
families.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
6 years agocmd: part: use MAX_SEARCH_PARTITIONS for part search
Kever Yang [Fri, 7 Sep 2018 09:37:36 +0000 (17:37 +0800)]
cmd: part: use MAX_SEARCH_PARTITIONS for part search

Use Macro instead of hard code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agoarm: armv7m: clean up armv7m unified code compilation
Vikas Manocha [Fri, 31 Aug 2018 23:57:06 +0000 (16:57 -0700)]
arm: armv7m: clean up armv7m unified code compilation

unified syntax should be selected by config ARM_ASM_UNIFIED

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoarm: armv7m: remove un-necessary If then instruction
Vikas Manocha [Fri, 31 Aug 2018 23:39:36 +0000 (16:39 -0700)]
arm: armv7m: remove un-necessary If then instruction

With gas option -mimplicit-it=always, IT block is inserted by the assembler
for thumb2.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoarm: stm32: Remove redundant thumb build selection
Vikas Manocha [Fri, 31 Aug 2018 23:15:14 +0000 (16:15 -0700)]
arm: stm32: Remove redundant thumb build selection

All armv7m arch builds are thumb & SYS_THUMB_BUILD is already selected by
CPU_ARMV7M.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoarm: spear: enable GPIO3 and 4 clocks when the GPIO controller driver is built
Quentin Schulz [Fri, 31 Aug 2018 14:15:53 +0000 (16:15 +0200)]
arm: spear: enable GPIO3 and 4 clocks when the GPIO controller driver is built

There are multiple GPIOs that can be used with the same driver depending
on the CONFIG_GPIO_BASE defined in the controller driver.

GPIO3 and 4 require a clock to be enabled so let's enable them when the
driver is built.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
6 years agotools: mkimage: Ensure munmap unmaps the same length that was mapped
Mark Tomlinson [Tue, 28 Aug 2018 22:51:14 +0000 (10:51 +1200)]
tools: mkimage: Ensure munmap unmaps the same length that was mapped

The set_header call in kwbimage.c adds a checksum to the end of the
image in addition to setting up the header. It 'helpfully' updates the
st_size to match the fact that the file is now longer. However, mkimage
uses this length in the munmap call. This can lead to unmapping an extra
page, of perhaps required data. When this happens, a SEGV can occur.

To prevent this from happening, the munmap call now uses the same length
that was passed to mmap. This could also have been fixed by not changing
the length in kwbimage.c, however changing it in the main file means
that other plugins will also not fall for the same trap.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
[cp: resolve checkpatch complaints]
Tested-by: Chris Packham <judge.packham@gmail.com>
6 years agoserial: omap: Introduce DM specific omap serial
Lokesh Vutla [Mon, 27 Aug 2018 10:25:24 +0000 (15:55 +0530)]
serial: omap: Introduce DM specific omap serial

Add driver model support for OMAP_SERIAL while reusing
the functions in ns16550.c

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
6 years agoomap3: pandora: Enable DM_SERIAL
Grazvydas Ignotas [Sat, 25 Aug 2018 19:40:08 +0000 (22:40 +0300)]
omap3: pandora: Enable DM_SERIAL

This patch enables DM_SERIAL for the pandora board. Verified that
the default kernel can still be booted with this.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
6 years agoboard: arm: Add support for Broadcom BCM7260
Thomas Fitzsimmons [Wed, 22 Aug 2018 22:37:55 +0000 (18:37 -0400)]
board: arm: Add support for Broadcom BCM7260

Add support for loading U-Boot on the Broadcom 7260 SoC.  This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
6 years agoarm: bcm7445: Change serial console index
Thomas Fitzsimmons [Wed, 22 Aug 2018 22:37:54 +0000 (18:37 -0400)]
arm: bcm7445: Change serial console index

Change the configured serial console index to reflect that it is the
first physical UART, reorder some defconfig lines and move some
environment configuration from bcmstb.h to bcm7445.h.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
6 years agoARM: CPU: arm926ejs: Consolidate cache routines to common file
Adam Ford [Thu, 16 Aug 2018 18:23:11 +0000 (13:23 -0500)]
ARM: CPU: arm926ejs: Consolidate cache routines to common file

Four different boards had different options for enabling cache
that were virtually all the same.  This consolidates these
common functions into arch/arm/cpu/arm926ejs/cache.c

This also has the positive side-effect of enabling cache on
the Davinci (da850) boards.

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add mach-at91 to the list of consolidations]
Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agoserial: arm_dcc: Add DCC support for V7R based cores
Lokesh Vutla [Thu, 16 Aug 2018 13:13:56 +0000 (18:43 +0530)]
serial: arm_dcc: Add DCC support for V7R based cores

DCC is supported on Cortex R series as well. Enable DCC support
for V7R.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agopinctrl: Fix build warning with ARM64
Lokesh Vutla [Thu, 16 Aug 2018 13:11:49 +0000 (18:41 +0530)]
pinctrl: Fix build warning with ARM64

Following build warning appears when pinctrl-single is built for ARM64:

In file included from drivers/pinctrl/pinctrl-single.c:10:0:
drivers/pinctrl/pinctrl-single.c: In function â€˜single_configure_pins’:
./arch/arm/include/asm/io.h:43:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
 #define __arch_getw(a)   (*(volatile unsigned short *)(a))

Fix this by using phys_addr_t for variable reg instead of u32

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agodm: omap-timer: Update clock rate only if not populated
Lokesh Vutla [Thu, 16 Aug 2018 12:56:55 +0000 (18:26 +0530)]
dm: omap-timer: Update clock rate only if not populated

timer_pre_probe() tries to populate the clock rate from DT. omap
timer driver tries to overwrite this value irrespective of the value
populated fro DT. So update this value only when DT doesn't populate
the clock rate.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agodm: omap-timer: Use 64bit for counter values
Lokesh Vutla [Thu, 16 Aug 2018 12:56:54 +0000 (18:26 +0530)]
dm: omap-timer: Use 64bit for counter values

In order to handle counter overflows use 64 bit values for counter.
Also load the initial value during probe.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
6 years agommc: fsl_esdhc: enable HS400 feature
Peng Fan [Fri, 10 Aug 2018 06:07:55 +0000 (14:07 +0800)]
mmc: fsl_esdhc: enable HS400 feature

The strobe dll code is ported from Linux Kernel:
drivers/mmc/host/sdhci-esdhc-imx.c
The comments are from the above file,
"For HS400 eMMC, there is a data_strobe line. This signal is generated
by the device and used for data output and CRC status response output
in HS400 mode. The frequency of this signal follows the frequency of
CLK generated by host. The host receives the data which is aligned to the
edge of data_strobe line. Due to the time delay between CLK line and
data_strobe line, if the delay time is larger than one clock cycle,
then CLK and data_strobe line will be misaligned, read error shows up.
So when the CLK is higher than 100MHz, each clock cycle is short enough,
host should configure the delay target. "

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
6 years agommc: add HS400 support
Peng Fan [Fri, 10 Aug 2018 06:07:54 +0000 (14:07 +0800)]
mmc: add HS400 support

Add HS400 support.
Selecting HS400 needs first select HS200 according to spec, so use
a dedicated function for HS400.
Add HS400 related macros.
Remove the restriction of only using the low 6 bits of
EXT_CSD_CARD_TYPE, using all the 8 bits.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
6 years agoat91: fix devicetree warnings
Eugen Hristev [Thu, 9 Aug 2018 11:12:01 +0000 (14:12 +0300)]
at91: fix devicetree warnings

This commit fixes various devicetree warnings in the at91 devicetrees
like:
arch/arm/dts/sama5d36ek_cmp.dtb: Warning (avoid_unnecessary_addr_size): /gpio_keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property

These warnings make buildman report failed builds for most of at91 boards.
Thus, fixing it.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
6 years agoARM: dts: Makefile: fix build for at91family
Eugen Hristev [Thu, 9 Aug 2018 11:12:00 +0000 (14:12 +0300)]
ARM: dts: Makefile: fix build for at91family

For at91family, makefile was building unwanted DTBs
Moved them under specific target configuration.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
6 years agogpio: stm32f7: replace ODR update by BSRR write
Patrice Chotard [Thu, 9 Aug 2018 09:57:57 +0000 (11:57 +0200)]
gpio: stm32f7: replace ODR update by BSRR write

Replace clrsetbits on ODR register (2 operations: one read + one write)
by writing on the correct bit (SET or RESET) of the BSRR register
(only 1 write operation).

Moreover this register if safe for simultaneous access by 2 master on
the bus.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
6 years agoclk: clk_meson: Add mux and div support for reparent and rate setting
Neil Armstrong [Mon, 6 Aug 2018 12:49:20 +0000 (14:49 +0200)]
clk: clk_meson: Add mux and div support for reparent and rate setting

This patch adds support for :
- Rate calculation through muxes and generic dividers
- Basic gate setting propagation
- Reparenting for muxes
- Clock rate setting through generic dividers without reparenting

Support is only added to the Composite VPU and VAPB clocks in order
to support the Video Processing Unit Power Domain clock setup.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
6 years agopower: domain: Add the VPU Power Domain driver
Neil Armstrong [Mon, 6 Aug 2018 12:49:19 +0000 (14:49 +0200)]
power: domain: Add the VPU Power Domain driver

The Amlogic Meson SoCs embeds a specific Power Domain dedicated to the
Video Processing Unit.
This patch implements support for this power domain in preparation of the
future support for the Video display support in U-Boot.

This driver will depend on changes in the clock driver to handle the setup
of the VPU and VAPB clocks configured from DT using assigned-clocks entries.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
6 years agoRemove <inttypes.h> includes and PRI* usages in printf() entirely
Masahiro Yamada [Mon, 6 Aug 2018 11:47:40 +0000 (20:47 +0900)]
Remove <inttypes.h> includes and PRI* usages in printf() entirely

In int-ll64.h, we always use the following typedefs:

  typedef unsigned int         u32;
  typedef unsigned long        uintptr_t;
  typedef unsigned long long   u64;

This does not need to match to the compiler's <inttypes.h>.
Do not include it.

The use of PRI* makes the code super-ugly.  You can simply use
"l" for printing uintptr_t, "ll" for u64, and no modifier for u32.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
6 years agoarch: types.h: factor out fixed width typedefs to int-ll64.h
Masahiro Yamada [Mon, 6 Aug 2018 11:47:39 +0000 (20:47 +0900)]
arch: types.h: factor out fixed width typedefs to int-ll64.h

All architectures have the same definition for s8/16/32/64
and u8/16/32/64.

Factor out the duplicated code into <asm-generic/int-ll64.h>.

BTW, Linux unified the kernel space definition into int-ll64.h
a few years ago as you see in Linux commit 0c79a8e29b5f
("asm/types.h: Remove include/asm-generic/int-l64.h").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
6 years agoRemove CONFIG_USE_STDINT
Masahiro Yamada [Mon, 6 Aug 2018 11:47:38 +0000 (20:47 +0900)]
Remove CONFIG_USE_STDINT

You do not need to use the typedefs provided by compiler.

Our compilers are either IPL32 or LP64.  Hence, U-Boot can/should
always use int-ll64.h typedefs like Linux kernel, whatever the
typedefs the compiler internally uses.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
6 years agoarm: armv7-a: Compile and tune for armv7-a instead of armv5
Adam Ford [Sat, 4 Aug 2018 21:34:54 +0000 (16:34 -0500)]
arm: armv7-a: Compile and tune for armv7-a instead of armv5

arch/arm/Makefile references armv5 for backwards compatibility with
older compilers.  This patch removes those references to armv5,
since by now newer compilers are required which should have armv7
support enabled.

The Makefile also also has a list of options for mtune, but the
entry for CONFIG_CPU_V7A is empty, so this patch tunes the
CPU_V7A architecture to generic-armv7-a.

The following size changed apply to omap3_logic using GCC.

Stock
text data bss dec hex filename
50910 429 67580 118919 1d087 spl/u-boot-spl
540713 22700 327072 890485   d9675 u-boot

Without Armv5
text data bss dec hex filename
50916 429 67580 118925   1d08d spl/u-boot-spl
540719 22700 327064 890483   d9673 u-boot

mtune=generic-armv7-a
text data bss dec hex filename
50932 429 67580 118941   1d09d spl/u-boot-spl
540519 22700 327080 890299   d95bb u-boot

Signed-off-by: Adam Ford <aford173@gmail.com>
6 years agosandbox: Add serial test
Patrice Chotard [Fri, 3 Aug 2018 13:07:41 +0000 (15:07 +0200)]
sandbox: Add serial test

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agodm: serial: Remove setparity ops
Patrice Chotard [Fri, 3 Aug 2018 13:07:40 +0000 (15:07 +0200)]
dm: serial: Remove setparity ops

setparity users has been updated to use new setconfig ops,
so we can safely remove setparity ops

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoserial: stm32: Replace setparity by setconfig
Patrice Chotard [Fri, 3 Aug 2018 13:07:39 +0000 (15:07 +0200)]
serial: stm32: Replace setparity by setconfig

Replace stm32_serial_setparity by stm32_serial_setconfig
which allows to set serial bits number, parity and stop
bits number.
Only parity setting is implemented.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agodm: serial: Replace setparity by setconfig
Patrice Chotard [Fri, 3 Aug 2018 13:07:38 +0000 (15:07 +0200)]
dm: serial: Replace setparity by setconfig

Replace setparity by more generic setconfig ops
to allow uart parity, bits word length and stop bits
number change.

Adds SERIAL_GET_PARITY/BITS/STOP macros.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agocli: handle getch error
Patrick Delaunay [Fri, 3 Aug 2018 11:38:45 +0000 (13:38 +0200)]
cli: handle getch error

Handle getch error (when getch return 0x0) to avoid display issue
in the console.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
6 years agoconsole: unify fgetc function when console MUX is deactivated
Patrick Delaunay [Fri, 3 Aug 2018 11:38:44 +0000 (13:38 +0200)]
console: unify fgetc function when console MUX is deactivated

Unify the fgetc function when MUX is activated or not:
- always call tstc() : it is the normal behavior expected
  by serial uclass (call tstc then getc) and that avoids
  issue when SERIAL_RX_BUFFER is activated
- reload WATCHDOG in the char waiting loop

This patch allow to have the same behavior when CONSOLE_MUX is activated
or not and avoid regression when this feature is deactivated.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoserial: protect access to serial rx buffer
Patrick Delaunay [Fri, 3 Aug 2018 11:38:43 +0000 (13:38 +0200)]
serial: protect access to serial rx buffer

Add test to avoid access to rx buffer when this buffer is empty.
In this case directly call getc() function to avoid issue when tstc()
is not called.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agostm32mp1: activate serial rx buffer
Patrick Delaunay [Fri, 3 Aug 2018 11:38:42 +0000 (13:38 +0200)]
stm32mp1: activate serial rx buffer

Activate the serial rx buffer.
Prepare console MUX activation with vidconsole, and avoid console
performance issue (missing character for copy-paste).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
6 years agoinclude/version.h: workaround sysroot inc order
Matt Weber [Fri, 27 Jul 2018 03:37:53 +0000 (22:37 -0500)]
include/version.h: workaround sysroot inc order

On some systems the host system or even the cross sysroot can
contain a version.h.  This leads to the wrong file being picked
up and a PLAIN_VERSION undefined error.

This workaround symlinks the version.h into the tool folder to
allow reordering of search folders.

Fixes
http://autobuild.buildroot.net/results/770/7702d5df36a6532aafdbe6e9e62709bbfa058b54/build-end.log
http://autobuild.buildroot.net/results/e34/e3401027d2fb3ce565ca9e2456a427afd3610a87/build-end.log
... additional can be found with these queries ...
http://autobuild.buildroot.net/?reason=uboot-tools-2018.03
http://autobuild.buildroot.net/?reason=uboot-tools-2018.05

Upstream: pending

Signed-off-by: Matthew Weber <matthew.weber@rockwellcollins.com>
6 years agoPrepare v2018.09 v2018.09
Tom Rini [Mon, 10 Sep 2018 21:46:42 +0000 (17:46 -0400)]
Prepare v2018.09

Signed-off-by: Tom Rini <trini@konsulko.com>
6 years ago.travis.yml: Fix typo in sun7i job description
Tuomas Tynkkynen [Fri, 7 Sep 2018 21:53:18 +0000 (00:53 +0300)]
.travis.yml: Fix typo in sun7i job description

'builman' -> 'buildman'

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
6 years agomtd: nand: denali: fix unaligned cache operations on ARMv7 SoCs
Masahiro Yamada [Mon, 10 Sep 2018 02:17:30 +0000 (11:17 +0900)]
mtd: nand: denali: fix unaligned cache operations on ARMv7 SoCs

If the OOB size is not multiple of the cache line size, the ARMv7
cache operation still prints "Misaligned operation at range".

=> nand info

Device 0: nand0, sector size 256 KiB
  Page size       4096 b
  OOB size         224 b
  Erase size    262144 b
  subpagesize     4096 b
  options     0x00104200
  bbt options 0x00060000
=> nand dump 0
CACHE: Misaligned operation at range [9fb152809fb16360]
CACHE: Misaligned operation at range [9fb152809fb16360]
CACHE: Misaligned operation at range [9fb152809fb16360]
CACHE: Misaligned operation at range [9fb152809fb16360]
  ...

The cache flushing operations won't happen in this case to cover all of
the range to fix this by making sure we have things aligned.

Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Reword the commit message to be clear this is a direct problem
rather than just a warning]

6 years agofdt: fix get_next_memory_node()
Marek Vasut [Sun, 9 Sep 2018 14:30:11 +0000 (16:30 +0200)]
fdt: fix get_next_memory_node()

The get_next_memory_node() always sets mem to -1 , which is incorrect,
because then every iteration of memory bank parsing will start from the
first memory bank instead of the previous one.

On systems with 1 memory bank defined in DT and CONFIG_NR_DRAM_BANKS=4 ,
like ie. r8a77965-salvator-x , this will result in U-Boot incorrectly
reporting four identical memory banks with the same memory configuration.

Fix this by setting mem to startoffset value, which restores the behavior
before the fixed patch was applied.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Fixes: 452bc121027d ("fdt: fix fdtdec_setup_memory_banksize()")
Tested-by: Michal Simek <michal.simek@xilinx.com> [on ZynqMP}
6 years agoARM: Specify aligned address for secure section instead of using attributes
Chen-Yu Tsai [Thu, 6 Sep 2018 03:56:28 +0000 (11:56 +0800)]
ARM: Specify aligned address for secure section instead of using attributes

In commit a1274cc94a20 ("ARM: Page align secure section only when it is
executed in situ"), we used output section attributes (the "ALIGN"
keyword after the colon) to specify the alignment requirements. Using
the constant "COMMONPAGE" there was recently broken in binutils 2.31 [1].

Binutils maintainer Alan Modra suggested the former method would still
work. Since both methods achieve the same result, this patch does just
that. This fixes the "reboot after bootm" issue we've been seeing on
sunxi when booting non-secure.

  [1] https://sourceware.org/bugzilla/show_bug.cgi?id=23571

Suggested-by: Alan Modra <amodra@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Jagan Teki <jagan@openedev.com>
6 years agopico-imx7d: Update the README file
Fabio Estevam [Tue, 4 Sep 2018 13:23:12 +0000 (10:23 -0300)]
pico-imx7d: Update the README file

Update the README file to take into accound the switch to SPL.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
6 years agotravis: Use kernel.org pre-built toolchain for riscv
Bin Meng [Thu, 30 Aug 2018 13:17:06 +0000 (06:17 -0700)]
travis: Use  pre-built toolchain for riscv

This updates travis configuration to use kernel.org pre-built
toolchain for riscv.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
6 years agoARM: qemu-arm: Fix qemu_arm64_defconfig for QEMU 3.0
Tuomas Tynkkynen [Tue, 4 Sep 2018 15:16:52 +0000 (18:16 +0300)]
ARM: qemu-arm: Fix qemu_arm64_defconfig for QEMU 3.0

QEMU 3.0 introduced additional memory-mapped regions for PCI-E ECAM and
MMIO. Thus we need to add them to our MMU map or U-Boot will crash with
a Synchronous Abort during PCI-E probing when it tries to access the
unmapped ECAM memory area.

Reported-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Tested-by: Jonathan Gray <jsg@jsg.id.au>
6 years agolib/slre: remove superfluous assignment
Heinrich Schuchardt [Mon, 3 Sep 2018 03:17:20 +0000 (05:17 +0200)]
lib/slre: remove superfluous assignment

It makes no sense to assign a value to 'res' if the next use of the
variable is an assignment.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
6 years agoamlogic: board p212: Fix Ethernet PHY init
Jasper kcoding [Mon, 3 Sep 2018 20:14:53 +0000 (22:14 +0200)]
amlogic: board p212: Fix Ethernet PHY init

Without this patch the Ethernet PHY on the p212 board does not get
fully configured.
When this happens Ethernet does not function.

The similar libretech-cc and khadas-vim boards have this code already.
That's why the Ethernet on these boards do work.

Signed-off-by: Jasper Kcoding <jasperkcoding@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
6 years agoqemu-arm: Enable DHCP distro target
Alexander Graf [Tue, 4 Sep 2018 11:49:29 +0000 (13:49 +0200)]
qemu-arm: Enable DHCP distro target

When booting the QEMU virt machine with -net nic,model=e1000 we can already
support network boot just fine today.

So let's enable the default bootcmd to also evaluate DHCP responses properly.
That way we can enable network boot seamlessly with the virt target.

Signed-off-by: Alexander Graf <agraf@suse.de>
6 years agoARM: dts: logicpd-torpedo-37xx-devkit-u-boot: Fix MMC Card Detect
Adam Ford [Mon, 3 Sep 2018 14:08:04 +0000 (09:08 -0500)]
ARM: dts: logicpd-torpedo-37xx-devkit-u-boot: Fix MMC Card Detect

When re-syncing the DTS files from the kernel, something caused
the MMC driver to no longer detect the MMC card. Undoing the
CD-invert appears to fix the issue.

Fixes: e6ea2390cde3 ("ARM: DTS: Resync LogicPD-Torpedo-37xx-devkit
with Linux 4.18-RC4")

Signed-off-by: Adam Ford <aford173@gmail.com>
6 years agoMerge tag 'arc-updates-for-2018.09' of git://git.denx.de/u-boot-arc
Tom Rini [Wed, 5 Sep 2018 15:39:03 +0000 (11:39 -0400)]
Merge tag 'arc-updates-for-2018.09' of git://git.denx.de/u-boot-arc

Minor changes for ARC

1. Fix CPU clock value in HSDK's .dts so time is counted properly.
2. Enable bootelf command on EMDK

6 years agoARC: HSDK: Fix timer frequency value
Eugeniy Paltsev [Wed, 5 Sep 2018 11:27:10 +0000 (14:27 +0300)]
ARC: HSDK: Fix timer frequency value

CPU (and hence cpu timers) on HSDK board runs at 500MHz after
preloader so fix wrong CPU frequency value in hsdk.dts

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
6 years agoEMDK: Enable bootelf
Alexey Brodkin [Mon, 6 Aug 2018 13:01:19 +0000 (16:01 +0300)]
EMDK: Enable bootelf

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoMerge branch 'master' of git://git.denx.de/u-boot-imx
Tom Rini [Tue, 4 Sep 2018 21:45:53 +0000 (17:45 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-imx

6 years agomx7dsabresd: Add the qspi target to the list of supported defconfigs
Fabio Estevam [Sat, 1 Sep 2018 17:24:56 +0000 (14:24 -0300)]
mx7dsabresd: Add the qspi target to the list of supported defconfigs

Add an entry for mx7dsabresd_qspi_defconfig to avoid the following
warnings:

WARNING: no status info for 'mx7dsabresd_qspi'
WARNING: no maintainers for 'mx7dsabresd_qspi'

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
6 years agoimx: missing CONFIG_MII in mx7dsabresd_qspi_defconfig
Stefano Babic [Fri, 31 Aug 2018 10:08:43 +0000 (12:08 +0200)]
imx: missing CONFIG_MII in mx7dsabresd_qspi_defconfig

CONFIG_CMD_MII is set without CONFIG_MII, build is broken.

Signed-off-by: Stefano Babic <sbabic@denx.de>
6 years agocolibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module support
Stefan Agner [Mon, 6 Aug 2018 07:19:19 +0000 (09:19 +0200)]
colibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module support

This commit adds support for the Toradex Colibri iMX7D 1GB Computer
on Module. The module is very similar to the Colibri iMX7D 512MB
but uses eMMC instead of raw NAND. This patch introduces a new
board specific Kconfig symbol to select between the two flash
options.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
6 years agoboard: toradex: common: fail gracefully on missing NAND chip
Stefan Agner [Mon, 6 Aug 2018 07:19:18 +0000 (09:19 +0200)]
board: toradex: common: fail gracefully on missing NAND chip

If the NAND chip is missing get_nand_dev_by_index() returns NULL. Fail
gracefully in this case.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
6 years agoimx: mx7: add system suspend/resume support
Anson Huang [Wed, 8 Aug 2018 01:17:50 +0000 (09:17 +0800)]
imx: mx7: add system suspend/resume support

This patch adds system suspend/resume support,
when linux kernel enters deep sleep mode, SoC will go
into below mode:

 - CA7 platform goes into STOP mode;
 - SoC goes into DSM mode;
 - DDR goes into self-refresh mode;
 - CPU0/SCU will be powered down.

When wake up event arrives:

 - SoC DSM mdoe exits;
 - CA7 platform exit STOP mode, SCU/CPU0 power up;
 - Invalidate L1 cache;
 - DDR exit self-refresh mode;
 - Do secure monitor mode related initialization;
 - Jump to linux kernel resume entry.

Belwo is the log of 1 iteration of system suspend/resume:

[  338.824862] PM: suspend entry (deep)
[  338.828853] PM: Syncing filesystems ... done.
[  338.834433] Freezing user space processes ... (elapsed 0.001 seconds) done.
[  338.842939] OOM killer disabled.
[  338.846182] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
[  338.869717] PM: suspend devices took 0.010 seconds
[  338.877846] Disabling non-boot CPUs ...
[  338.960301] Retrying again to check for CPU kill
[  338.964953] CPU1 killed.
[  338.968104] Enabling non-boot CPUs ...
[  338.973598] CPU1 is up
[  339.267155] mmc1: queuing unknown CIS tuple 0x80 (2 bytes)
[  339.275833] mmc1: queuing unknown CIS tuple 0x80 (7 bytes)
[  339.284158] mmc1: queuing unknown CIS tuple 0x80 (6 bytes)
[  339.385065] PM: resume devices took 0.400 seconds
[  339.389836] OOM killer enabled.
[  339.392986] Restarting tasks ... done.
[  339.398990] PM: suspend exit

The resume entry function has to initialize stack pointer before calling
C code, otherwise there will be an external abort occur, in additional,
invalidate L1 cache must be done in secure section as well, so this
patch also adds assembly code back and keep it as simple as possible.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
6 years agoimx: mx7: add gpc initialization for low power mode
Anson Huang [Wed, 8 Aug 2018 01:17:49 +0000 (09:17 +0800)]
imx: mx7: add gpc initialization for low power mode

Add i.MX7D GPC initialization for low power mode
support like system suspend/resume from linux kernel:

 - Pending IOMUXC IRQ to workaround GPC state machine issue;
 - Mask all GPC interrupts for M4/C0/C1;
 - Configure SCU timing;
 - Configure time slot ack;
 - Configure C0/C1 power up/down timing;
 - Configure wakeup source mechanism;
 - Disable DSM/RBC related settings.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
6 years agoimx: mx7: psci: improve cpu hotplug flow
Anson Huang [Wed, 8 Aug 2018 01:17:48 +0000 (09:17 +0800)]
imx: mx7: psci: improve cpu hotplug flow

This patch improves cpu hotplug, previous cpu_off
implementation is NOT safe, a CPU can NOT power down
itself in runtime, it will cause system bus hang due
to pending transaction. So need to use other online
CPU to kill it when it is ready for killed.

Here use SRC parameter register and a magic number
of ~0 as handshake for killing a offline CPU,
when the online CPU checks the psci_affinity_info,
it will help kill the offline CPU according to
the magic number stored in SRC parameter register.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
6 years agoCleanup CONFIG_BOOTDELAY on cl-som-imx7
Alex Kiernan [Tue, 24 Jul 2018 07:29:40 +0000 (07:29 +0000)]
Cleanup CONFIG_BOOTDELAY on cl-som-imx7

CONFIG_BOOTDELAY has been migrated to Kconfig, but cl-som-imx7 was
missed. We can just delete the assignments as the config already has
the correct value.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
6 years agowatchdog: mx25: use the imx_watchdog driver for mx25
Martin Kaiser [Sat, 21 Jul 2018 17:47:03 +0000 (19:47 +0200)]
watchdog: mx25: use the imx_watchdog driver for mx25

The existing imx_watchdog driver is compatible with mx25 chipsets.
Add a WDOG1_BASE_ADDR define for the base address and enable the driver
in watchdog's Makefile.

To use the driver, a board must define CONFIG_IMX_WATCHDOG and
CONFIG_HW_WATCHDOG.

This fixes an issue when booting an mx25 chip via usb/serial. In this
case, the boot rom will always enable the watchdog. If u-boot is running
in interactive mode and the watchdog is not serviced, the system is
rebooted when the watchdog expires.

Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
6 years agoimx: imx6ul_evk: Enable DM driver for iMX6UL EVK u-boot
Ye Li [Thu, 28 Jun 2018 03:23:17 +0000 (20:23 -0700)]
imx: imx6ul_evk: Enable DM driver for iMX6UL EVK u-boot

Convert the codes and configurations to enable DM drivers in u-boot for
modules: i2c, PMIC, regulator, USB, Ethernet, SD/MMC, GPIO and QSPI

This patch does not change SPL, so it still uses non-DM driver for
UART, GPIO and SD/MMC.

Signed-off-by: Ye Li <ye.li@nxp.com>
6 years agodts: imx6ul_evk: Add DTS files for 14x14 EVK and 9x9 EVK boards
Ye Li [Thu, 28 Jun 2018 03:23:16 +0000 (20:23 -0700)]
dts: imx6ul_evk: Add DTS files for 14x14 EVK and 9x9 EVK boards

Add the board DTS files for 14x14 EVK and 9x9 EVK. They are necessary
for converting to use u-boot DM driver.

Two -u-boot.dtsi are added to modify compatible string of SPI flash
device to "spi-flash".

Signed-off-by: Ye Li <ye.li@nxp.com>
6 years agodts: imx6ul: Update alias to support DM
Ye Li [Thu, 28 Jun 2018 03:23:15 +0000 (20:23 -0700)]
dts: imx6ul: Update alias to support DM

Add spi0 alias for qspi for enabling DM SPI.
Change usb alias for usbotg1 and usbotg2 for enabling DM USB

Signed-off-by: Ye Li <ye.li@nxp.com>
6 years agoimx: imx7d-sdb: Add DM QSPI support
Ye Li [Thu, 28 Jun 2018 02:30:53 +0000 (19:30 -0700)]
imx: imx7d-sdb: Add DM QSPI support

On iMX7D SabreSD board, the QSPI has pins conflict with EPDC (default).
To use QSPI, users have to rework the board (de-populate R388-R391, R396-R399
populate R392-R395, R299, R300). So we add new DTS file and new defconfig
dedicated for QSPI.

Other changes to support the DM QSPI:
 - Add QSPI node and alias spi0.
 - Modify spi4 (spi-gpio) node and add alias spi5 for it to avoid req
   conflict
 - Add EPDC node in imx7d.dtsi and disable it in imx7d-sdb-qspi.dts to
   align with kernel and also present the conflict.
 - Add -u-boot.dtsi to modify compatible string of mx25l51245g@0 to
   "spi-flash"
 - Remove iomux settings of qspi in board codes which is not needed
   for DM driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
6 years agoimx: imx6sx-sabreauto: convert to use DM QSPI driver
Ye Li [Thu, 28 Jun 2018 02:27:00 +0000 (19:27 -0700)]
imx: imx6sx-sabreauto: convert to use DM QSPI driver

To support DM QSPI driver:
 - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string
   to "spi-flash" and add "num-cs" property.
 - Enable DM SPI and DM SPI FLASH configurations
 - Remove iomux settings of qspi1 in board codes which is not needed
   for DM driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
6 years agoimx: imx6sx-sdb: Enable DM QSPI driver
Ye Li [Thu, 28 Jun 2018 02:26:59 +0000 (19:26 -0700)]
imx: imx6sx-sdb: Enable DM QSPI driver

To support DM QSPI driver
 - Add spi0 and spi1 alias for qspi1 and qspi2.
 - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string
   to "spi-flash" and add "num-cs" property.
 - Enable DM SPI/QSPI relavent configurations
 - Remove iomux settings of qspi2 in board codes which is not needed
   for DM driver.
 - Add sf default settings. So running "sf probe" can detect the flash

Signed-off-by: Ye Li <ye.li@nxp.com>
6 years agoPrepare v2018.09-rc3 v2018.09-rc3
Tom Rini [Mon, 3 Sep 2018 19:36:33 +0000 (15:36 -0400)]
Prepare v2018.09-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agoconfigs: Resync with savedefconfig
Tom Rini [Mon, 3 Sep 2018 19:26:12 +0000 (15:26 -0400)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agospl: Kconfig: Fix typo in 'Upgrade'
Fabio Estevam [Fri, 31 Aug 2018 13:02:28 +0000 (10:02 -0300)]
spl: Kconfig: Fix typo in 'Upgrade'

Correct the spelling of 'Upgrade'.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>