oweals/u-boot.git
4 years agodm: powerpc: T1023/T1024: add i2c DM support
Biwen Li [Fri, 1 May 2020 12:04:11 +0000 (20:04 +0800)]
dm: powerpc: T1023/T1024: add i2c DM support

This supports i2c DM for SoC T1023/T1024

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: P4080DS: enable DM_I2C
Biwen Li [Fri, 1 May 2020 12:04:10 +0000 (20:04 +0800)]
configs: P4080DS: enable DM_I2C

This enables DM_I2C in P4080DS defconfigs,
except P4080DS SRIO_PCIE_BOOT and SECURE_BOOT defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agopowerpc: dts: P4080: add i2c node
Biwen Li [Fri, 1 May 2020 12:04:09 +0000 (20:04 +0800)]
powerpc: dts: P4080: add i2c node

This adds i2c node for SoC P4080

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: P3041DS: enable DM_I2C
Biwen Li [Fri, 1 May 2020 12:04:08 +0000 (20:04 +0800)]
configs: P3041DS: enable DM_I2C

This enables DM_I2C in P3041DS defconfigs,
except P3041DS SECURE_BOOT and SRIO_PCIE_BOOT defconfig

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agopowerpc: dts: P3041: add i2c node
Biwen Li [Fri, 1 May 2020 12:04:07 +0000 (20:04 +0800)]
powerpc: dts: P3041: add i2c node

This adds i2c node for SoC P3041

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfig: P2041RDB: enable DM_I2C
Biwen Li [Fri, 1 May 2020 12:04:06 +0000 (20:04 +0800)]
config: P2041RDB: enable DM_I2C

This enables DM_I2C in P2041RDB defconfig,
except P2041RDB SRIO_PCIE_BOOT and SECURE_BOOT defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agodm: powerpc: P2041RDB: add i2c DM support
Biwen Li [Fri, 1 May 2020 12:04:05 +0000 (20:04 +0800)]
dm: powerpc: P2041RDB: add i2c DM support

This supports i2c DM for board P2041RDB

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: P2020RDB: enable DM_I2C and DM_RTC
Biwen Li [Fri, 1 May 2020 12:04:04 +0000 (20:04 +0800)]
configs: P2020RDB: enable DM_I2C and DM_RTC

This enables DM_I2C and DM_RTC in P2020RDB defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agodts: powerpc: P2020RDB: add i2c node
Biwen Li [Fri, 1 May 2020 12:04:03 +0000 (20:04 +0800)]
dts: powerpc: P2020RDB: add i2c node

This adds i2c node for board P2020RDB

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: P1020RDB: enable DM_I2C and DM_RTC
Biwen Li [Fri, 1 May 2020 12:04:02 +0000 (20:04 +0800)]
configs: P1020RDB: enable DM_I2C and DM_RTC

This enables DM_I2C and DM_RTC in P1020RDB defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agodm: powerpc: P1020: add i2c DM support
Biwen Li [Fri, 1 May 2020 12:04:01 +0000 (20:04 +0800)]
dm: powerpc: P1020: add i2c DM support

This supports i2c DM for SoC P1020

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: P5040DS: enable DM_I2C
Biwen Li [Fri, 1 May 2020 12:04:00 +0000 (20:04 +0800)]
configs: P5040DS: enable DM_I2C

This enable DM_I2C in P5040DS defconfigs,
except P5040DS SECURE_BOOT defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agodm: powerpc: P5040DS: add i2c DM support
Biwen Li [Fri, 1 May 2020 12:03:59 +0000 (20:03 +0800)]
dm: powerpc: P5040DS: add i2c DM support

This supports i2c DM for board P5040DS

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agopowerpc: create dts component of i2c to build up an SoC
Biwen Li [Fri, 1 May 2020 12:03:58 +0000 (20:03 +0800)]
powerpc: create dts component of i2c to build up an SoC

Provide a common i2c components that we can utilize to
build up the various device tree.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agortc: pt7c4338: Add driver model support
Biwen Li [Fri, 1 May 2020 12:03:57 +0000 (20:03 +0800)]
rtc: pt7c4338: Add driver model support

Add support of driver model of pt7c4338

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agortc: ds1337: Add driver model support
Biwen Li [Fri, 1 May 2020 12:03:56 +0000 (20:03 +0800)]
rtc: ds1337: Add driver model support

Add support of driver model of ds1337

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoMerge branch '2020-05-01-master-imports'
Tom Rini [Fri, 1 May 2020 20:43:15 +0000 (16:43 -0400)]
Merge branch '2020-05-01-master-imports'

- Assorted bug fixes
- Framework for enabling D-CACHE in SPL on ARM

4 years ago.readthedocs.yml: fix type docs/
Heinrich Schuchardt [Fri, 1 May 2020 20:06:17 +0000 (22:06 +0200)]
.readthedocs.yml: fix type docs/

Out documentation directory is doc/ and not docs/.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoactions: Fix syntax for enabling SYS_RELOC_GD_ENV_ADDR
Tom Rini [Fri, 1 May 2020 14:52:11 +0000 (10:52 -0400)]
actions: Fix syntax for enabling SYS_RELOC_GD_ENV_ADDR

The correct syntax is 'select SYS_...' and not 'select CONFIG_SYS...'

Fixes: d5c819b885c2 ("actions: Move defconfig options to Kconfig")
Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agocommon/board_r: Drop initr_bedbug wrapper
Ovidiu Panait [Mon, 20 Apr 2020 07:31:46 +0000 (10:31 +0300)]
common/board_r: Drop initr_bedbug wrapper

Drop initr_bedbug wrapper and call bedbug_init directly during the init
sequence.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agocmd/bedbug.c: Make bedbug_init have a return value
Ovidiu Panait [Mon, 20 Apr 2020 07:31:45 +0000 (10:31 +0300)]
cmd/bedbug.c: Make bedbug_init have a return value

Do this as a preparation for removing initr_bedbug wrapper from
common/board_r.c.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agocommon/board_r: arm: Merge initr_enable_interrupts into interrupts_init
Ovidiu Panait [Mon, 20 Apr 2020 07:31:44 +0000 (10:31 +0300)]
common/board_r: arm: Merge initr_enable_interrupts into interrupts_init

initr_enable_interrupts() is an ARM-specific wrapper over
enable_interrupts(), which is run during the common init sequence. It can
be eliminated by moving the enable_interrupts() call to the end of
interrupt_init() function, in arch/arm/lib/interrupts*.c.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agomalloc: dlmalloc: add an ability for the malloc to be re-init/init multiple times
Marek Bykowski [Wed, 29 Apr 2020 16:23:07 +0000 (18:23 +0200)]
malloc: dlmalloc: add an ability for the malloc to be re-init/init multiple times

Malloc gets initialized with a call to mem_malloc_init() with the address
the allocation starts to and its size. Currently it is not possible to
move the malloc from one memory area to another as the malloc would eventually
fail.

This patch adds in the ability to re-init the malloc with the updated
start address and the size.

One of the use cases of this feature is SPL U-Boot running from within
the static memory and calling to malloc init from within board_init_f():

arch/arm/cpu/armv8/start.S:reset vector
arch/arm/cpu/armv8/start.S:main()
arch/arm/lib/crt0_64.S:board_init_f()
board/<my_board>/common/spl.c:board_init_f()
        board/<my_board>/common/spl.c:mem_malloc_init((ulong)CONFIG_SYS_SPL_MALLOC_START,
                        CONFIG_SYS_SPL_MALLOC_SIZE);

Shortly after the DDR (main) memory is init and ready we call to malloc init
again but this time with the start address in the DDR memory and a much greater
size for moving the allocation off the static to the DDR memory:

board/<my_board>/common/spl.c:mem_malloc_init((ulong)CONFIG_SPL_MALLOC_OFFSET,
CONFIG_SPL_MALLOC_SIZE);

Where CONFIG_SYS_SPL_MALLOC_START and CONFIG_SPL_MALLOC_OFFSET are the start
addresses of the malloc in the static and DDR memories respectively and
CONFIG_SYS_SPL_MALLOC_SIZE=SZ_16K and CONFIG_SPL_MALLOC_SIZE=SZ_2M are
the sizes of the mallocs in these memories. Note, now we have a much greater
memory, enlarging from 16K to 2M, available for allocation.

There is an alternative approach already existing in U-Boot with the use of
an early (simplified) malloc and the proper (dlamalloc) malloc however
necessitating managing the two mallocs whereas this approach proposes using
a single dlmalloc.

Signed-off-by: Marek Bykowski <marek.bykowski@gmail.com>
4 years agorsa: sig: fix config signature check for fit with padding
Philippe Reynes [Wed, 29 Apr 2020 13:26:17 +0000 (15:26 +0200)]
rsa: sig: fix config signature check for fit with padding

The signature check on config node is broken on fit with padding.
To compute the signature for config node, U-Boot compute the
signature on all properties of requested node for this config,
except for the property "data". But, when padding is used for
binary in a fit, there isn't a property "data" but two properties:
"data-offset" and "data-size". So to fix the check of signature,
we also don't use the properties "data-offset" and "data-size"
when checking the signature on config node.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
4 years agotest/py: vboot: add a test to check fit signature on fit with padding
Philippe Reynes [Wed, 29 Apr 2020 13:26:16 +0000 (15:26 +0200)]
test/py: vboot: add a test to check fit signature on fit with padding

The pytest vboot does all his tests on fit without padding.
We add the same tests on fit with padding.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
4 years agohush: avoid NULL check before free()
Heinrich Schuchardt [Tue, 28 Apr 2020 19:56:10 +0000 (21:56 +0200)]
hush: avoid NULL check before free()

free() checks if its argument is NULL. Don't duplicate this in the calling
code.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agofs: ext4: avoid NULL check before free()
Heinrich Schuchardt [Tue, 28 Apr 2020 19:50:02 +0000 (21:50 +0200)]
fs: ext4: avoid NULL check before free()

free() checks if its argument is NULL. Don't duplicate this in the calling
code.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agocmd/gpt: avoid NULL check before free()
Heinrich Schuchardt [Tue, 28 Apr 2020 19:40:13 +0000 (21:40 +0200)]
cmd/gpt: avoid NULL check before free()

free() checks if its argument is NULL. Do not duplicate this in the calling
code.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agotools/fit-image: print a warning when cmd-line for dtc might be truncated
Sven Roederer [Mon, 27 Apr 2020 00:08:39 +0000 (02:08 +0200)]
tools/fit-image: print a warning when cmd-line for dtc might be truncated

Signed-off-by: Sven Roederer <devel-sven@geroedel.de>
4 years agotools/mkimage: fix handling long filenames
Sven Roederer [Mon, 27 Apr 2020 00:08:38 +0000 (02:08 +0200)]
tools/mkimage: fix handling long filenames

The cmdline for calling the dtc was cut-off when using long filenames (e.g.
245 bytes) for output-file and datafile of "-f" parameter.
For FIT-images cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN] is declared (hardcoded 512 bytes),
and contains some static values, the path of a tmpfile and a datafile. tmpfile is
max MKIMAGE_MAX_TMPFILE_LEN (256) and datafile might be also this size. Having two
very long pathname results in a truncation os the executed shell command, as the
truncated datafile path will not be found.
Redefine MKIMAGE_MAX_DTC_CMDLINE_LEN to "2 * MKIMAGE_MAX_TMPFILE_LEN + 35 for the
parameters.
This likely applies to the "-d" parameter, too.

Signed-off-by: Sven Roederer <devel-sven@geroedel.de>
4 years agoarm: enable distro boot for bananapi-r2
Matthias Brugger [Sat, 25 Apr 2020 23:17:46 +0000 (01:17 +0200)]
arm: enable distro boot for bananapi-r2

This patch enables distro boot for the bananapi-r2, based on
a MediaTek mt7623n.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
4 years agowatchdog MediaTek add upstream compatible
Matthias Brugger [Sat, 25 Apr 2020 23:17:45 +0000 (01:17 +0200)]
watchdog MediaTek add upstream compatible

The upstream compatible is called mt6589-wdt.
Add this compatible to the driver.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
4 years agotimer MediaTek use upstream compatible
Matthias Brugger [Sat, 25 Apr 2020 23:17:44 +0000 (01:17 +0200)]
timer MediaTek use upstream compatible

The timers compatible string in upstream is called
mt6577-timer. Add this compatible to the driver.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
4 years agodoc: describe the analysis of crash dumps
Heinrich Schuchardt [Fri, 24 Apr 2020 21:31:20 +0000 (23:31 +0200)]
doc: describe the analysis of crash dumps

Provide an overview of the analysis of U-Boot crash dumps.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
4 years agortc: pcf2127: don't add/subtract 1 to tm_mon
Rasmus Villemoes [Fri, 1 May 2020 13:24:50 +0000 (15:24 +0200)]
rtc: pcf2127: don't add/subtract 1 to tm_mon

As noted in rtc_def.h, the tm_mon field in struct rtc_time is 1-12,
unlike in struct tm where it is 0-11. Currently, running "date" prints
the wrong

Date: 2020-04-01 (Friday)    Time: 13:05:30

and setting the RTC via the date command is also broken.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
4 years agoarm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviour
Patrick Delaunay [Fri, 24 Apr 2020 18:20:17 +0000 (20:20 +0200)]
arm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviour

Solved the overflow on phys_addr_t type for start + size in
mmu_set_region_dcache_behaviour() function.

This overflow is avoided by dividing start and end by 2 before addition,
and we only expecting that start and size are even.

This patch doesn't change the current function behavior if the
parameters (start or size) are not aligned on MMU_SECTION_SIZE.

For example, this overflow occurs on ARM32 with:
start = 0xC0000000 and size = 0x40000000
then start + size = 0x100000000 and end = 0x0.

For information the function behavior change with risk of regression,
if we just shift start and size before the addition.
Example with 2MB section size:
  MMU_SECTION_SIZE 0x200000 and MMU_SECTION_SHIFT = 21
  with start = 0x1000000, size = 0x1000000,
  - with the proposed patch, start = 0 and end = 0x1 as previously
  - with the more simple patch:
    end = (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT)
    the value of end change:
    start >> 21 = 0, size >> 21 = 0 and end = 0x0 !!!

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
4 years agoarm: caches: add DCACHE_DEFAULT_OPTION
Patrick Delaunay [Fri, 24 Apr 2020 18:20:16 +0000 (20:20 +0200)]
arm: caches: add DCACHE_DEFAULT_OPTION

Add the new flags DCACHE_DEFAULT_OPTION to define the default
option to use according the compilation flags
CONFIG_SYS_ARM_CACHE_*.

This new compilation flag allows to simplify dram_bank_mmu_setup()
and can be used as third parameter (option=dcache option to select)
of mmu_set_region_dcache_behaviour function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
4 years agoarm: caches: protect dram_bank_mmu_setup access to bi_dram
Patrick Delaunay [Fri, 24 Apr 2020 18:20:15 +0000 (20:20 +0200)]
arm: caches: protect dram_bank_mmu_setup access to bi_dram

Add protection in dram_bank_mmu_setup() to avoid access to bd->bi_dram
before relocation.

This patch allow to use the generic weak function dram_bank_mmu_setup
to activate the MMU and the data cache in SPL or in U-Boot before
relocation, when bd->bi_dram is not yet initialized.

In this cases, the MMU must be initialized explicitly with
mmu_set_region_dcache_behaviour function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
4 years agoconfigs: migrate CONFIG_SYS_ARM_CACHE_* in Kconfig
Patrick Delaunay [Fri, 10 Apr 2020 14:02:02 +0000 (16:02 +0200)]
configs: migrate CONFIG_SYS_ARM_CACHE_* in Kconfig

Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and
CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py.

Kconfig uses a choice between the 3 values supported in U-Boot,
including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK
(the default configuration).

The patch also avoids to select simultaneously 2 configurations.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
4 years agotiny-printf: Support %i
Marek Vasut [Fri, 10 Apr 2020 18:54:49 +0000 (20:54 +0200)]
tiny-printf: Support %i

The most basic printf("%i", value) formating string was missing,
add it for the sake of convenience.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
4 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-spi
Tom Rini [Thu, 30 Apr 2020 22:05:15 +0000 (18:05 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi

- distro boot support for SPI flash
- sifive spi flash driver

4 years agoMerge tag 'efi-2020-07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Thu, 30 Apr 2020 19:11:06 +0000 (15:11 -0400)]
Merge tag 'efi-2020-07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2020-07-rc2

This pull request contains bug fixes needed due to the merged changes for
EFI secure boot.

Patches are supplied to identify EFI system partitions.

4 years agosifive: fu540: Enable spi-nor flash support
Jagan Teki [Wed, 29 Apr 2020 15:33:53 +0000 (21:03 +0530)]
sifive: fu540: Enable spi-nor flash support

HiFive Unleashed A00 support is25wp256 spi-nor flash,
So enable the same and add test result log for future
reference.

Tested on SiFive FU540 board.

Thanks to Sagar for various use cases and tests.

[QUAD mode in dt with spi-tx-bus-width: <4>]
 pp opcode      = 0x34 [QUAD MODE]
 read opcode  = 0x6c  [QUAD MODE]
 erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc

[SPI MODE in dt with spi-tx-bus-width: <1>]
pp opcode     = 0x12 [SPI MODE]
read opcode  = 0xc   [SPI MODE]
erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
4 years agoriscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi
Jagan Teki [Thu, 23 Apr 2020 17:00:56 +0000 (22:30 +0530)]
riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi

Add U-Boot specific dts file for hifive-unleashed-a00, this
would help to add u-boot specific properties and other node
changes without touching the base dts(i) files which are easy
to sync from Linux.

Added spi2 alias for qspi2 as an initial u-boot specific
property change.

spi probing in current dm model is very much rely on aliases
numbering. Even though the qspi2 can't come under any associated
spi nor flash it would require to specify the same to make proper
binding happen for other spi slaves.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
4 years agospi: sifive: Fix QPP transfer
Jagan Teki [Thu, 23 Apr 2020 17:00:55 +0000 (22:30 +0530)]
spi: sifive: Fix QPP transfer

The guessed reason is that the existing logic of filling
tx fifo with data, rx fifo with NULL for tx transfer and
filling rx fifo with data, tx fifo with NULL for rx transfer
is not clear enough to support the Quad Page Program.
  Â 
SiFive SPI controllers have specific sets of watermark
registers and SPI I/O directions bits in order to program
SPI controllers clear enough to support all sets of operating
modes.
  Â 
Here is the exact programing sequence that would follow on this
patch and tested via SPI-NOR and MMC_SPI.
  Â 
- set the frame format proto, endian
- set the frame format dir, set it for tx and clear it for rx
- TX transfer:
  fill tx fifo with data.
  wait for TX watermark bit to clear.
- RX transfer:
  fill tx fifo with 0xff.
  write nbytes to rx watermark register
  wait for rx watermark bit to clear.
  read the rx fifo data.

So, this patch adopts this program sequence and fixes the existing
I/O direction bit.

Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
4 years agospi: sifive: Fix format register proto field
Jagan Teki [Thu, 23 Apr 2020 17:00:54 +0000 (22:30 +0530)]
spi: sifive: Fix format register proto field

SiFive SPI controller has a proto bit field in frame format
register which would be used to configure the SPI I/O protocol
lines used on specific transfer. 

Right now the driver is configuring this proto using slave->mode,
for all types of transctions. This makes the driver unable to
function since the proto needs to configure dynamically for
each and every transaction separately at runtime.

Now, the controller driver supports per transfer via spi-mem
exec_opo, so add the fmt_proto flag and fill the per transfer
buswidth so that the controller configures the proto bit at
runtime.

This patch fixes the SPI controller works with SPI NOR flash
on quad read with page program.

Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
4 years agospi: sifive: Add spi-mem exec op
Jagan Teki [Thu, 23 Apr 2020 17:00:53 +0000 (22:30 +0530)]
spi: sifive: Add spi-mem exec op

SiFive SPI controller is responsible to handle the
slave devices like mmc spi and spi nor flash.

The controller is designed such a way that it would
handle the slave transactions based on the I/O protocol
numbers, example if spi nor slave send quad write opcode
it has to send alone with I/O protocol number of 4 and
if it try to send data it has to send I/O protocol number
along with 4 line data.

But the current spi-xfer code from spi-mem is combining
the opcode and address in a single transaction, so the
SPI controller will be unable to identify the I/O protocol
number of opcode vs address.

So, add the spi-mem exec_op with spi-xfer of opcode, address
and data as a separate transaction. This doesn't remove
the .xfer of dm_spi_ops since mmc spi will make use of it.

Note: This code might have moved to the spi-mem core area
once we have done the dedicated tests on other controllers
and have real reason to move.

Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
4 years agomtd: spi-nor-ids: Add Spansion s25fs512s flash entry
Kuldeep Singh [Fri, 3 Apr 2020 06:57:42 +0000 (12:27 +0530)]
mtd: spi-nor-ids: Add Spansion s25fs512s flash entry

Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on
various platforms as former is not present. Add the entry.

Linux already has both the flashes present. A snippet below:
{ "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256...},
{ "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256...},

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agowatchdog: kconfig: Enable designware for rk3399
Jagan Teki [Mon, 20 Apr 2020 18:04:13 +0000 (23:34 +0530)]
watchdog: kconfig: Enable designware for rk3399

Enable designware watchdog driver for rk3399 if WDT defined.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agomtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256
Jagan Teki [Mon, 20 Apr 2020 10:06:07 +0000 (15:36 +0530)]
mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256

IS25WP256 flash chips do support 4byte address opcodes,
so enable support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
4 years agomtd: spi-nor: Enable QE bit for ISSI flash
Jagan Teki [Mon, 20 Apr 2020 10:06:06 +0000 (15:36 +0530)]
mtd: spi-nor: Enable QE bit for ISSI flash

Enable QE bit for ISSI flash chips.

QE enablement logic is similar to what Macronix
has, so reuse the existing code itself.

Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: sifive: Tidy up dm_spi_slave_platdata variable
Jagan Teki [Mon, 20 Apr 2020 10:33:46 +0000 (16:03 +0530)]
spi: sifive: Tidy up dm_spi_slave_platdata variable

Usually variable name slave is used for spi_slave structure
and slave_plat for the dm_spi_slave_platdata.

Let's follow this meaningful notation by replacing slave
with slave_plat for dm_spi_slave_platdata structure.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agork3399: Enable SF distro bootcmd
Jagan Teki [Fri, 10 Apr 2020 18:26:31 +0000 (23:56 +0530)]
rk3399: Enable SF distro bootcmd

Enable SPI flash(SF) distro boot command in rk3399.

This distro boot will read the boot script at specific
location at the flash and start sourcing the same.

Included the SF device at the last of the target devices
list since all the rest of the devices on the list have
more possibility to boot the distribution due to the
size of the SPI flash is concern.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
Tom Rini [Thu, 30 Apr 2020 17:00:20 +0000 (13:00 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86

- DM ACPI support (Part A)
- Improve support for chain-loading x86 U-Boot

4 years agoMerge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u...
Tom Rini [Thu, 30 Apr 2020 15:31:33 +0000 (11:31 -0400)]
Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2020.07-rc2

mmc:
- Fix dt property handling via generic function

clk:
- Fix versal watchdog clock setting

nand:
- Fix zynq nand command comparison

xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose

zynq:
- Kconfig alignments
- Fix nand cse configuration

zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates

Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Tom Rini [Thu, 30 Apr 2020 14:06:54 +0000 (10:06 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb,
  ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb.
- Add GICv3 support for ls1028a, ls2088a, ls1088a.
- Add lpuart support on ls1028aqds.
- Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based
  platforms.

4 years agox86: Add documentation for the chain-load feature
Simon Glass [Sun, 26 Apr 2020 15:13:01 +0000 (09:13 -0600)]
x86: Add documentation for the chain-load feature

Add a few notes about this feature, which is aimed for development.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Use the existing stack when chain-loading
Simon Glass [Sun, 26 Apr 2020 15:13:00 +0000 (09:13 -0600)]
x86: Use the existing stack when chain-loading

With chromebook_coral we normally run TPL->SPL->U-Boot. This is the
'bare metal' case.

When running from coreboot we put u-boot.bin in the RW_LEGACY portion
of the image, e.g. with:

   cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \
-f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \
-c lzma -l 0x1110000 -e 0x1110000

In this case U-Boot is run from coreboot (actually Depthcharge, its
payload) so we cannot access CAR. Use the existing stack instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Add a way to detect running from coreboot
Simon Glass [Sun, 26 Apr 2020 15:12:59 +0000 (09:12 -0600)]
x86: Add a way to detect running from coreboot

If U-Boot is running from coreboot we need to skip low-level init. Add
an way to detect this and to set the gd flag.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: Move coreboot-table detection into common code
Simon Glass [Sun, 26 Apr 2020 15:12:58 +0000 (09:12 -0600)]
x86: Move coreboot-table detection into common code

To support detecting booting from coreboot, move the code which locates
the coreboot tables into a common place. Adjust the algorithm slightly to
use a word comparison instead of string, since it is faster.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct the comments to 960KB]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoboard: Add a gd flag for chain loading
Simon Glass [Sun, 26 Apr 2020 15:12:57 +0000 (09:12 -0600)]
board: Add a gd flag for chain loading

When U-Boot is run from another boot loader, much of the low-level init
needs to be skipped.

Add a flag for this and adjust ll_boot_init() to use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agopci: Avoid auto-config when chain loading
Simon Glass [Sun, 26 Apr 2020 15:12:56 +0000 (09:12 -0600)]
pci: Avoid auto-config when chain loading

When U-Boot is not the first-stage bootloader we don't want to
re-configure the PCI devices, since this has already been done. Add a
check to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: cpu: Skip init code when chain loading
Simon Glass [Sun, 26 Apr 2020 15:12:55 +0000 (09:12 -0600)]
x86: cpu: Skip init code when chain loading

When U-Boot is not the first-stage bootloader the interrupt and cache init
must be skipped, as well as init for various peripherals. Update the code
to add checks for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: apl: Skip init code when chain loading
Simon Glass [Sun, 26 Apr 2020 15:12:54 +0000 (09:12 -0600)]
x86: apl: Skip init code when chain loading

When U-Boot is not the first-stage bootloader the FSP-S init must be
skipped. Update it to add a check.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agox86: fsp: Allow skipping init code when chain loading
Simon Glass [Sun, 26 Apr 2020 15:12:53 +0000 (09:12 -0600)]
x86: fsp: Allow skipping init code when chain loading

It is useful to be able to boot the same x86 image on a device with or
without a first-stage bootloader. For example, with chromebook_coral, it
is helpful for testing to be able to boot the same U-Boot (complete with
FSP) on bare metal and from coreboot. It allows checking of things like
CPU speed, comparing registers, ACPI tables and the like.

When U-Boot is not the first-stage bootloader much of this code is not
needed and can break booting. Add checks for this to the FSP code.

Rather than checking for the amount of available SDRAM, just use 1GB in
this situation, which should be safe. Using 2GB may run into a memory
hole on some SoCs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoacpi: Add an acpi command
Simon Glass [Sun, 26 Apr 2020 15:19:53 +0000 (09:19 -0600)]
acpi: Add an acpi command

It is useful to dump ACPI tables in U-Boot to see what has been generated.
Add a command to handle this.

To allow the command to find the tables, add a position into the global
data.

Support subcommands to list and dump the tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agoacpi: Move the xsdt pointer to acpi_ctx
Simon Glass [Sun, 26 Apr 2020 15:19:52 +0000 (09:19 -0600)]
acpi: Move the xsdt pointer to acpi_ctx

Put this in the context along with the other important pointers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agoacpi: Put table-setup code in its own function
Simon Glass [Sun, 26 Apr 2020 15:19:51 +0000 (09:19 -0600)]
acpi: Put table-setup code in its own function

We always write three basic tables to ACPI at the start. Move this into
its own function, along with acpi_fill_header(), so we can write a test
for this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoacpi: Move acpi_add_table() to generic code
Simon Glass [Sun, 26 Apr 2020 15:19:50 +0000 (09:19 -0600)]
acpi: Move acpi_add_table() to generic code

Move this code to a generic location so that we can test it with sandbox.
This requires adding a few new fields to acpi_ctx, so drop the local
variables used in the original code.

Also use mapmem to avoid pointer-to-address casts which don't work on
sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agoacpi: Drop code for missing XSDT from acpi_write_rsdp()
Simon Glass [Sun, 26 Apr 2020 15:19:49 +0000 (09:19 -0600)]
acpi: Drop code for missing XSDT from acpi_write_rsdp()

We don't actually support tables without an XSDT so we can drop this dead
code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agox86: Allow devices to write ACPI tables
Simon Glass [Sun, 26 Apr 2020 15:19:48 +0000 (09:19 -0600)]
x86: Allow devices to write ACPI tables

Call the new core function to permit devices to write their own ACPI
tables. These tables will appear after all other tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agoacpi: Convert part of acpi_table to use acpi_ctx
Simon Glass [Sun, 26 Apr 2020 15:19:47 +0000 (09:19 -0600)]
acpi: Convert part of acpi_table to use acpi_ctx

The current code uses an address but a pointer would result in fewer
casts. Also it repeats the alignment code in a lot of places so this would
be better done in a helper function.

Update write_acpi_tables() to make use of the new acpi_ctx structure,
adding a few helpers to clean things up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agoacpi: Add a method to write tables for a device
Simon Glass [Sun, 26 Apr 2020 15:19:46 +0000 (09:19 -0600)]
acpi: Add a method to write tables for a device

A device may want to write out ACPI tables to describe itself to Linux.
Add a method to permit this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agoacpi: Add a binding for ACPI settings in the device tree
Simon Glass [Sun, 26 Apr 2020 15:19:45 +0000 (09:19 -0600)]
acpi: Add a binding for ACPI settings in the device tree

Devices need to report various identifiers in the ACPI tables. Rather than
hard-coding these in drivers it is typically better to put them in the
device tree.

Add a binding file to describe this.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agox86: cbfs: Drop unwanted declaration
Simon Glass [Sun, 5 Apr 2020 23:22:38 +0000 (17:22 -0600)]
x86: cbfs: Drop unwanted declaration

The intention here is add a forward declaration, not actually declare a
variable. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
4 years agoefi_loader: fix 'efidebug bootorder'
Heinrich Schuchardt [Wed, 29 Apr 2020 19:15:08 +0000 (21:15 +0200)]
efi_loader: fix 'efidebug bootorder'

* don't copy GUIDs for no reason
* shorten print format strings by using variable names
* don't use the run-time table to access exported functions
* check the result of malloc() (fixes Coverity CID 300331)

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: efidebug, avoid illegal memory access
Heinrich Schuchardt [Wed, 29 Apr 2020 18:21:39 +0000 (20:21 +0200)]
efi_loader: efidebug, avoid illegal memory access

For EFI_PERSISTENT_MEMORY_TYPE the 'efidebug memmap' command produces an
illegal memory access.

* Add the missing descriptive string for EFI_PERSISTENT_MEMORY_TYPE.
* Replace the check for EFI_MAX_MEMORY_TYPE by the ARRAY_SIZE() macro.

Reported-by: Coverity (CID 300336)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: fix 'efidebug boot dump'
Heinrich Schuchardt [Wed, 29 Apr 2020 17:20:35 +0000 (19:20 +0200)]
efi_loader: fix 'efidebug boot dump'

* Do not recreate a variable name that we already have as u16 string.
* Check the return value of malloc()
* EFI_NOT_FOUND cannot occur for a variable name returned by
  GetNextVariableName(). Remove a print statement.
* Don't copy a GUID for no reason.
* Don't use the run-time service table to call exported functions.
* Don't pass NULL to show_efi_boot_opt_data() (fixes Coverity CID 300338).

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoMAINTAINERS: assign test/py/tests/test_efi*/ to EFI PAYLOAD
Heinrich Schuchardt [Wed, 22 Apr 2020 15:53:34 +0000 (17:53 +0200)]
MAINTAINERS: assign test/py/tests/test_efi*/ to EFI PAYLOAD

Some UEFI related files are not assigned currently. Add them to the
EFI PAYLOAD area.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: remove CONFIG_EFI_SECURE_BOOT in efi_loader.h
AKASHI Takahiro [Tue, 21 Apr 2020 00:38:38 +0000 (09:38 +0900)]
efi_loader: remove CONFIG_EFI_SECURE_BOOT in efi_loader.h

The guard doesn't make any difference, so remove it.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agodoc/efi: rework secure boot description
Heinrich Schuchardt [Thu, 16 Apr 2020 18:31:56 +0000 (20:31 +0200)]
doc/efi: rework secure boot description

Ensure a uniform formatting.
Some rephrasing.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: identify EFI system partition
Heinrich Schuchardt [Thu, 19 Mar 2020 14:16:31 +0000 (15:16 +0100)]
efi_loader: identify EFI system partition

In subsequent patches UEFI variables shalled be stored on the EFI system
partition. Hence we need to identify the EFI system partition.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agopart: detect EFI system partition
Heinrich Schuchardt [Thu, 19 Mar 2020 12:49:34 +0000 (13:49 +0100)]
part: detect EFI system partition

Up to now for MBR and GPT partitions the info field 'bootable' was set to 1
if either the partition was an EFI system partition or the bootable flag
was set.

Turn info field 'bootable' into a bit mask with separate bits for bootable
and EFI system partition.

This will allow us to identify the EFI system partition in the UEFI
sub-system.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: remove superfluous NULL check in bootefi.c
Heinrich Schuchardt [Mon, 20 Apr 2020 10:44:56 +0000 (12:44 +0200)]
efi_loader: remove superfluous NULL check in bootefi.c

efi_free_pool() and efi_delete_handle() both check if their argument is
NULL. The caller should not duplicate this check.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agotest/py: fix test_efi_secboot/conftest.py
Heinrich Schuchardt [Tue, 21 Apr 2020 16:44:39 +0000 (18:44 +0200)]
test/py: fix test_efi_secboot/conftest.py

If udisksctl is present
test/py/tests/test_efi_secboot/conftest.py
fails because the disk image is never mounted.

Normal users can only mount fuse file systems. Unfortunately fusefat is
still in an experimental state and seems not to work here correctly.

So as we have to be root or use the sudo command anyway delete all coding
referring to udisksctl.

--

We should not use mount point /mnt as this directory or one of its
sub-directories might already be in use as active mount points. Instead
create a new directory in the build root as mount point.

--

Remove debug print statements that have been commented out. print without
parentheses is anyway invalid in Python 3. And pytest anyway filters out
the output if there is no exception reported.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
Tom Rini [Wed, 29 Apr 2020 14:39:18 +0000 (10:39 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh

- rmobile gen2/gen3 DTS sync and defconfig consolidation

4 years agoconfigs: ls2088ardb: Correct DEFAULT_DEVICE_TREE value
Kuldeep Singh [Thu, 19 Mar 2020 10:04:16 +0000 (15:34 +0530)]
configs: ls2088ardb: Correct DEFAULT_DEVICE_TREE value

LS2088A-RDB has CONFIG_DEFAULT_DEVICE_TREE value correctly set as
"fsl-ls2088a-rdb-qspi" for QSPI secure/non-secure boot and TFA
non-secure boot mode.

Fix the value for TFA secure boot mode.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: enable DM_ETH support for LS1046ARDB
Madalin Bucur [Thu, 23 Apr 2020 13:25:22 +0000 (16:25 +0300)]
configs: enable DM_ETH support for LS1046ARDB

Enable DM_ETH on all the defconfigs for the LS1046ARDB board.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: enable DM_ETH support for LS1043ARDB
Madalin Bucur [Thu, 23 Apr 2020 13:25:21 +0000 (16:25 +0300)]
configs: enable DM_ETH support for LS1043ARDB

Enable DM_ETH on all the defconfigs for the LS1043ARDB board.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agodriver: net: fm: add DM ETH support
Madalin Bucur [Thu, 23 Apr 2020 13:25:19 +0000 (16:25 +0300)]
driver: net: fm: add DM ETH support

Probe the FMan MACs based on the device tree while
retaining the legacy code/functionality.
One notable change introduced here is that, for DM_ETH,
the name of the interfaces is corrected to the fmX-macY
format, that avoids the referral to the MAC block names
which were incorrect for FMan v3 devices (i.e. DTSEC,
TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1).
The legacy code is left unchanged in this respect.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agodriver: net: fm: add DM MDIO support
Madalin Bucur [Thu, 23 Apr 2020 13:25:18 +0000 (16:25 +0300)]
driver: net: fm: add DM MDIO support

Allow the MDIO devices to be probed based on the device tree.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agodriver: net: fm: separate receive buffer free code
Madalin Bucur [Thu, 23 Apr 2020 13:25:17 +0000 (16:25 +0300)]
driver: net: fm: separate receive buffer free code

Move the receive buffer free code in a separate function.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agodriver: net: fm: change init_phy() param
Madalin Bucur [Thu, 23 Apr 2020 13:25:16 +0000 (16:25 +0300)]
driver: net: fm: change init_phy() param

Change the init_phy() parameter to simplify the code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoARM: dts: add QorIQ DPAA 1 FMan v3 to LS1046ARDB
Madalin Bucur [Thu, 23 Apr 2020 13:25:15 +0000 (16:25 +0300)]
ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1046ARDB

Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1046ARDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoARM: dts: add QorIQ DPAA 1 FMan v3 for LS1046A
Madalin Bucur [Thu, 23 Apr 2020 13:25:14 +0000 (16:25 +0300)]
ARM: dts: add QorIQ DPAA 1 FMan v3 for LS1046A

Add the QorIQ DPAA 1 Frame Manager v3 device tree nodes for the
LS1046A SoC. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDB
Madalin Bucur [Thu, 23 Apr 2020 13:25:13 +0000 (16:25 +0300)]
ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDB

Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1043ARDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoARM: dts: add QorIQ DPAA 1 FMan v3 for LS1043A
Madalin Bucur [Thu, 23 Apr 2020 13:25:12 +0000 (16:25 +0300)]
ARM: dts: add QorIQ DPAA 1 FMan v3 for LS1043A

Add the QorIQ DPAA 1 Frame Manager v3 device tree nodes for the
LS1043A SoC. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoARM: dts: add QorIQ DPAA 1 FMan v3 device tree nodes
Madalin Bucur [Thu, 23 Apr 2020 13:25:11 +0000 (16:25 +0300)]
ARM: dts: add QorIQ DPAA 1 FMan v3 device tree nodes

Add the QorIQ DPAA Frame Manager v3 device tree nodes description.
The device tree fragments are copied over with little modification
from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls1012afrwy: drop env qspi_bootcmd
Biwen Li [Fri, 17 Apr 2020 09:37:01 +0000 (17:37 +0800)]
configs: ls1012afrwy: drop env qspi_bootcmd

Drop useless environment variable installer and qspi_bootcmd
for ls1012afrwy.
Only 2 MB nor flash in ls1012afrwy. So cannot get kernel(30 MB) from
the nor flash, then drop it.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls1046aqds: support distro boot
Biwen Li [Mon, 20 Apr 2020 10:29:06 +0000 (18:29 +0800)]
configs: ls1046aqds: support distro boot

Add support of distro boot for ls1046aqds

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>