oweals/u-boot.git
4 years agoMerge branch 'net' of git://git.denx.de/u-boot-socfpga
Tom Rini [Sat, 23 May 2020 02:58:16 +0000 (22:58 -0400)]
Merge branch 'net' of git://git.denx.de/u-boot-socfpga

- ks8851 cleanups and DM migration

4 years agonet: ks8851: Add Kconfig entries
Marek Vasut [Wed, 25 Mar 2020 18:08:59 +0000 (19:08 +0100)]
net: ks8851: Add Kconfig entries

Convert CONFIG_KS8851_MLL and CONFIG_KS8851_MLL_BASEADDR to Kconfig

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: ks8851: Add DM support
Marek Vasut [Wed, 25 Mar 2020 17:00:35 +0000 (18:00 +0100)]
net: ks8851: Add DM support

Add support for U-Boot DM and DT probing.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: ks8851: Receive one packet per recv call
Marek Vasut [Wed, 25 Mar 2020 17:47:10 +0000 (18:47 +0100)]
net: ks8851: Receive one packet per recv call

Instead of reading out the entire FIFO and possibly overwriting U-Boot
memory, read out one packet per recv call, pass it to U-Boot network
stack, and repeat. It is however necessary to cache RXFC value, because
reading that one out clears it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: ks8851: Split non-DM specific bits from common code
Marek Vasut [Wed, 25 Mar 2020 16:54:45 +0000 (17:54 +0100)]
net: ks8851: Split non-DM specific bits from common code

Split network handling functions into non-DM specific parts and
common code in preparation for conversion to DM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: ks8851: Pass around driver private data
Marek Vasut [Wed, 25 Mar 2020 16:35:00 +0000 (17:35 +0100)]
net: ks8851: Pass around driver private data

Introduce a private data structure for this driver with embedded
struct eth_device and pass it around. This prepares the driver to
work with both DM and non-DM systems.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: ks8851: Checkpatch cleanup
Marek Vasut [Wed, 25 Mar 2020 16:25:29 +0000 (17:25 +0100)]
net: ks8851: Checkpatch cleanup

Fix various checkpatch complaints.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: ks8851: Clean up chip ID readout
Marek Vasut [Wed, 25 Mar 2020 17:15:46 +0000 (18:15 +0100)]
net: ks8851: Clean up chip ID readout

There is only one chip ID in the table of chip IDs for this chip.
Read out the chip ID instead and mask off the last "revision" bit
to check the chip ID, this works for all chips in the family. Then
drop the chip ID passing around.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: ks8851: Remove type_frame_head
Marek Vasut [Wed, 25 Mar 2020 16:23:11 +0000 (17:23 +0100)]
net: ks8851: Remove type_frame_head

The packet status and length information should be extracted from the
FIFO per-packet. Adjust the code such that it reads the packet meta
data and then the packet afterward, if applicable.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: ks8851: Trim down struct ks_net
Marek Vasut [Wed, 25 Mar 2020 16:18:55 +0000 (17:18 +0100)]
net: ks8851: Trim down struct ks_net

Most of the entries in the structure are useless, remove them. Inline
the rest of uses where applicable.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: ks8851: Use 16bit RXQCR access
Marek Vasut [Wed, 25 Mar 2020 16:02:51 +0000 (17:02 +0100)]
net: ks8851: Use 16bit RXQCR access

Per KS8851-16MLL, the RXQCR is a 16bit register. Use 16bit accessors
to it consistently and drop the ks_wrreg8() function altogether, as
it is not used anymore.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: ks8851: Remove RXQCR cache
Marek Vasut [Wed, 25 Mar 2020 16:02:21 +0000 (17:02 +0100)]
net: ks8851: Remove RXQCR cache

The cached RXQCR value is never updated, remove the cache and just use
the bits in the cache directly in the code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: ks8851: Replace malloc()+memset() with calloc()
Marek Vasut [Wed, 25 Mar 2020 15:52:38 +0000 (16:52 +0100)]
net: ks8851: Replace malloc()+memset() with calloc()

Replace combination of malloc()+memset() with calloc() as the behavior
is exactly the same and the amount of code is reduced. Moreover, remove
printf() in the fail path, as it is useless, and return proper -ENOMEM
return code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agoMerge tag 'u-boot-rockchip-20200522' of https://gitlab.denx.de/u-boot/custodians...
Tom Rini [Fri, 22 May 2020 14:28:38 +0000 (10:28 -0400)]
Merge tag 'u-boot-rockchip-20200522' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

- Fix rk3288 chromebook veyron support;
- Add pcie driver support for rk3399;
- other fixes for rk3399 boards

4 years agoMerge tag 'imx8qxp-fixes' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
Tom Rini [Fri, 22 May 2020 14:28:26 +0000 (10:28 -0400)]
Merge tag 'imx8qxp-fixes' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- Fix i.MX8QXP boot hang when getting CPU temperature

4 years agoMerge tag 'efi-2020-07-rc3-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Fri, 22 May 2020 14:27:24 +0000 (10:27 -0400)]
Merge tag 'efi-2020-07-rc3-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2020-07-rc3 (2)

Problems fixed with these patches are:

* UEFI sub-system not working with virtio block devices
* Missing SATA support in UEFI sub-system
* A superfluous debug statement

4 years agoMerge tag 'uniphier-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot...
Tom Rini [Fri, 22 May 2020 14:27:06 +0000 (10:27 -0400)]
Merge tag 'uniphier-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier

UniPhier SoC updates for v2020.07

 - De-assert write protect for Denali NAND driver

 - Clean up include directives

 - Migrate to DM_ETH, and remove legacy board_eth_init()

4 years agorockchip: rk3328: rock64 - fix gen3 SPL hang
Kurt Miller [Wed, 13 May 2020 19:55:20 +0000 (15:55 -0400)]
rockchip: rk3328: rock64 - fix gen3 SPL hang

Use the same approach as ROC-RK3328-CC which enables SPL GPIO,
pinctl and regulator support. This allows the gen3 board to
boot through SPL and does not break gen2 in the process.

Signed-off-by: Kurt Miller <kurt@intricatesoftware.com>
Acked-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agodefconfig: veyron: no need for CONFIG_SPL_PINCTRL_FULL
Urja Rannikko [Wed, 13 May 2020 19:15:23 +0000 (19:15 +0000)]
defconfig: veyron: no need for CONFIG_SPL_PINCTRL_FULL

Veyrons do not need full pinctrl support for SPL.
The full pinctrl support does nothing when enabled with OF_PLATDATA,
thus was already unused.
This frees about 4kB of SPL size.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: spl-boot-order: do not attempt to access fdt if OF_PLATDATA
Urja Rannikko [Wed, 13 May 2020 19:15:22 +0000 (19:15 +0000)]
rockchip: spl-boot-order: do not attempt to access fdt if OF_PLATDATA

gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang
after f0921f5098 ("fdt: Sync up to the latest libfdt").
We use the same test that is used in spl_common_init on whether to call
fdtdec_setup to unconditionally avoid linking in the fdt-using code
when not necessary and thus reduce SPL size.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: veyron: move board_early_init_f to _r (after reloc)
Urja Rannikko [Wed, 13 May 2020 19:15:21 +0000 (19:15 +0000)]
rockchip: veyron: move board_early_init_f to _r (after reloc)

Previously veyron_init() was called in board_init() context, which is
called after relocation. Moving it to veyron.c used board_early_init_f
which is called way earlier, and causes veyron_init to hang.
Using board_early_init_r instead fixes this.

Fixes: b678f2790c ("rockchip: rk3288: Move veyron_init() back to veyron.c")
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: spl: veyron speedy boots from SPI
Urja Rannikko [Wed, 13 May 2020 19:15:20 +0000 (19:15 +0000)]
rockchip: spl: veyron speedy boots from SPI

Apparently speedy was forgotten from this list of veyron devices.

Fixes: 49105fb7ed ("rockchip: add common spl board file")
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agotools: value checks in rkcommon_check_params()
Heinrich Schuchardt [Sat, 9 May 2020 19:31:03 +0000 (21:31 +0200)]
tools: value checks in rkcommon_check_params()

Building with -Wtype-limits yields

tools/rkcommon.c: In function ‘rkcommon_check_params’:
tools/rkcommon.c:158:27: warning: comparison of
unsigned expression < 0 is always false [-Wtype-limits]
  158 |  if (spl_params.init_size < 0)
      |                           ^
tools/rkcommon.c:165:28: warning: comparison of
unsigned expression < 0 is always false [-Wtype-limits]
  165 |   if (spl_params.boot_size < 0)
      |

Fix the value checks.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: Enable PCIe/M.2 on rock960 board
Jagan Teki [Sat, 9 May 2020 16:56:24 +0000 (22:26 +0530)]
rockchip: Enable PCIe/M.2 on rock960 board

Due to board limitation some SSD's would work
on rock960 PCIe M.2 only with 1.8V IO domain.

So, this patch enables grf io_sel explicitly to
make PCIe/M.2 to work.

Cc: Tom Cubie <tom@radxa.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: Enable PCIe/M.2 on rk3399 board w/ M.2
Jagan Teki [Sat, 9 May 2020 16:56:23 +0000 (22:26 +0530)]
rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2

Enable PCIe/M.2 support on
- NanoPC-T4
- ROC-RK3399-PC Mezzanine boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agopci: Add Rockchip PCIe PHY controller driver
Jagan Teki [Sat, 9 May 2020 16:56:22 +0000 (22:26 +0530)]
pci: Add Rockchip PCIe PHY controller driver

Yes, it is possible to have a dedicated UCLASS PHY driver
for this Rockchip PCIe PHY but there are some issues on
Generic PHY framework to support the same.

The Generic PHY framework is unable to get the PHY if
the PHY parent is of a different uclass.

Say if we try to get the PCIe PHY then the phy-uclass
will look for PHY in the first instance if it is not
in the root node it will try to probe the parent by
assuming that the actual PHY is inside the parent PHY
of UCLASS_PHY. But, in rk3399 hardware representation
PHY like emmc, usb and pcie are part of syscon which
is completely a different of UCLASS_SYSCON.

Example:

grf: syscon@ff770000 {
   compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
   reg = <0x0 0xff770000 0x0 0x10000>;
   #address-cells = <1>;
   #size-cells = <1>;

   pcie_phy: pcie-phy {
       compatible = "rockchip,rk3399-pcie-phy";
       clocks = <&cru SCLK_PCIEPHY_REF>;
       clock-names = "refclk";
       #phy-cells = <1>;
       resets = <&cru SRST_PCIEPHY>;
       drive-impedance-ohm = <50>;
       reset-names = "phy";
       status = "disabled";
   };
};

Due to this limitation, this patch adds a separate PHY
driver for Rockchip PCIe. This might be removed in future
once Generic PHY supports this limitation.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agopci: Add Rockchip PCIe controller driver
Jagan Teki [Sat, 9 May 2020 16:56:21 +0000 (22:26 +0530)]
pci: Add Rockchip PCIe controller driver

Add Rockchip PCIe controller driver for rk3399 platform.

Driver support Gen1 by operating as a Root complex.

Thanks to Patrick for initial work.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
4 years agoclk: rk3399: Enable/Disable the PCIEPHY clk
Jagan Teki [Sat, 9 May 2020 16:56:20 +0000 (22:26 +0530)]
clk: rk3399: Enable/Disable the PCIEPHY clk

Enable/Disable the PCIEPHY clk for rk3399.

CLK is clear in both enable and disable functionality.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoclk: rk3399: Add enable/disable clks
Jagan Teki [Sat, 9 May 2020 16:56:19 +0000 (22:26 +0530)]
clk: rk3399: Add enable/disable clks

Yes, most of the high speed peripheral clocks
in rk3399 enabled by default.

But it would be better to handle them via clk
enable/disable API for handling proper reset
conditions like 'usb reset' over command line.

So, enable USB, GMAC clock via enable/disable ops.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil.m@amarulasolutions.com> # roc-rk3399-pc
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockpro64: Enable HDMI output on rockpro64 board
Andrius Štikonas [Fri, 24 Apr 2020 21:03:29 +0000 (22:03 +0100)]
rockpro64: Enable HDMI output on rockpro64 board

Reference to commit that adds HDMI to other rk3399 boards:
commit 9778edae5576 ("rockchip: Enable HDMI output on rk3399 board w/ HDMI")

Signed-off-by: Andrius Štikonas <andrius@stikonas.eu>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agothermal: imx_scu_thermal: prevent boot hang with zero pdata
Anatolij Gustschin [Wed, 20 May 2020 08:21:53 +0000 (10:21 +0200)]
thermal: imx_scu_thermal: prevent boot hang with zero pdata

Should initialization of pdata values have failed for some reason,
we end up in endless loop when getting the CPU temperature value
and can not boot. Check alert value in pdata and only retry reading
temperature if alert value is not zero. Also shorten the temperature
info string.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
4 years agocpu: imx8: use intended cpu-thermal device when getting temp value
Anatolij Gustschin [Tue, 19 May 2020 23:31:44 +0000 (01:31 +0200)]
cpu: imx8: use intended cpu-thermal device when getting temp value

This fixes getting DT alert and critical pdata values in imx_scu_thermal
driver. On i.MX8QXP using not initialized alert pdata value resulted in
boot hang and endless loop outputting:
CPU Temperature (47200C) has beyond alert (0C), close to critical (0C) waiting...

While at it, preset CPU type values once to avoid multiple calls
of device_is_compatible() for same property.

Fixes: 3ee6ea443eb4 ("cpu: imx_cpu: Print the CPU temperature for iMX8QM A72")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
4 years agocpu: imx8: fix type and rate detection
Anatolij Gustschin [Sat, 16 May 2020 20:34:19 +0000 (22:34 +0200)]
cpu: imx8: fix type and rate detection

CPU type and rate detection is broken, for A35 cpu we get A53:
...
sc_pm_get_clock_rate: resource:0 clk:2: res:3
Could not read CPU frequency: -22
CPU:   NXP i.MX8QXP RevB A53 at 0 MHz at 47C

Fixes: 55bc96f3b675 ("cpu: imx8: fix get core name and rate")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
4 years agorockchip: rk3399: enable spl-fifo-mode for sdmmc
Deepak Das [Wed, 15 Apr 2020 03:25:24 +0000 (08:55 +0530)]
rockchip: rk3399: enable spl-fifo-mode for sdmmc

adapting commit fa2047c47310 ("rockchip: rk3328: enable spl-fifo-mode
for emmc and sdmmc") for rk3399.
Since mmc to sram can't do dma, add patch to prevent aborts transferring
TF-A parts.

Signed-off-by: Deepak Das <deepakdas.linux@gmail.com>
4 years agoboard: puma: use dtb given on the commandline instead of using u-boot.dtb
Heiko Stuebner [Wed, 6 May 2020 11:06:56 +0000 (13:06 +0200)]
board: puma: use dtb given on the commandline instead of using u-boot.dtb

The make_fit_spl scripts get the dtb to use as commandline option,
so use it for puma as well.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
4 years agoARM: uniphier: remove board_eth_init()
Masahiro Yamada [Wed, 20 May 2020 03:31:28 +0000 (12:31 +0900)]
ARM: uniphier: remove board_eth_init()

This platform completely migrated to CONFIG_DM_ETH.

board_eth_init() is only called from net/eth_legacy.c

Remove the legacy hook.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: delete or replace <common.h> includes
Masahiro Yamada [Wed, 20 May 2020 03:31:27 +0000 (12:31 +0900)]
ARM: uniphier: delete or replace <common.h> includes

<common.h> pulls in a lot of bloat. <common.h> is unneeded in most of
places.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoARM: uniphier: drop #include <log.h> again
Masahiro Yamada [Wed, 20 May 2020 03:31:26 +0000 (12:31 +0900)]
ARM: uniphier: drop #include <log.h> again

I do not understand the changes made to these files by
commit f7ae49fc4f36 ("common: Drop log.h from common header").

  git show f7ae49fc4f36 -- arch/arm/mach-uniphier/

None of them uses the log function feature.

Simply revert the changes made to these files.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoARM: uniphier: drop #include <init.h> again from umc-pxs2.c
Masahiro Yamada [Wed, 20 May 2020 03:31:25 +0000 (12:31 +0900)]
ARM: uniphier: drop #include <init.h> again from umc-pxs2.c

I do not understand the change made to this file by
commit 691d719db718 ("common: Drop init.h from common header").

  git show 691d719db718 -- arch/arm/mach-uniphier/dram/umc-pxs2.c

This file does not call or define any functions declared in <init.h>

Simply revert the change made to this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoARM: uniphier: remove #include <net.h> again from micro-support-card.c
Masahiro Yamada [Wed, 20 May 2020 03:31:24 +0000 (12:31 +0900)]
ARM: uniphier: remove #include <net.h> again from micro-support-card.c

I do not understand the changes made to this file by
commit 90526e9fbac4 ("common: Drop net.h from common header").

  git show 90526e9fbac4 -- arch/arm/mach-uniphier/micro-support-card.c

The necessary declaration is already included by <netdev.h> at line 112.
It also moved the <dm/of.h> inclusion, but I do not understand the
motivation of doing so, either.

Simply revert the changes made to this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: include <asm/system.h> instead of <asm/cache.h> from psci.c
Masahiro Yamada [Wed, 20 May 2020 03:31:23 +0000 (12:31 +0900)]
ARM: uniphier: include <asm/system.h> instead of <asm/cache.h> from psci.c

I do not understand the change made to this file by
commit 90526e9fbac4 ("common: Drop net.h from common header").

  git show 90526e9fbac4 -- arch/arm/mach-uniphier/arm32/psci.c

It added <asm/cache.h> while this file does not call the standard cache
functions at all.

All the uniphier-specific cache functions, uniphier_cache_*() are
declared in cache-uniphier.h, which is already included from this file.

Including <asm/system.h> is sensible to fix the -Wmissing-prototypes
warnings because this file defines psci_cpu_on and psci_system_reset().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agomtd: rawnand: denali: deassert write protect pin
Masahiro Yamada [Thu, 7 May 2020 13:12:00 +0000 (22:12 +0900)]
mtd: rawnand: denali: deassert write protect pin

[ Linux commit 9afbe7c0140f663586edb6e823b616bd7076c00a ]

If the write protect signal from this IP is connected to the NAND
device, this IP can handle the WP# pin via the WRITE_PROTECT
register.

The Denali NAND Flash Memory Controller User's Guide describes
this register like follows:

  When the controller is in reset, the WP# pin is always asserted
  to the device. Once the reset is removed, the WP# is de-asserted.
  The software will then have to come and program this bit to
  assert/de-assert the same.

    1 - Write protect de-assert
    0 - Write protect assert

The default value is 1, so the write protect is de-asserted after
the reset is removed. The driver can write to the device unless
someone has explicitly cleared register before booting the kernel.

The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the
case; the boot ROM clears the WRITE_PROTECT register when the system
is booting from the NAND device, so the NAND device becomes read-only.

Set it to 1 in the driver in order to allow the write access to the
device.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
4 years agoARM: uniphier: select DM_ETH
Masahiro Yamada [Thu, 7 May 2020 13:11:19 +0000 (22:11 +0900)]
ARM: uniphier: select DM_ETH

drivers/net/smc911x.c has been converted to DM.

select DM_ETH to enable it for all the UniPhier platform boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agomtd: rawnand: denali: configure SPARE_AREA_SKIP_BYTES only for denali_spl
Masahiro Yamada [Fri, 17 Apr 2020 07:51:42 +0000 (16:51 +0900)]
mtd: rawnand: denali: configure SPARE_AREA_SKIP_BYTES only for denali_spl

This CONFIG option is only used in denali_spl.c

Move it close to SPL_NAND_DENALI, and make it depend on SPL_NAND_DENALI.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoMerge git://git.denx.de/u-boot-sh
Tom Rini [Thu, 21 May 2020 12:26:40 +0000 (08:26 -0400)]
Merge git://git.denx.de/u-boot-sh

- Enable -ffunction-sections / -fdata-sections --gc-sections to SH
- RCar Gen3 updates

4 years agoefi_loader: check device path is not installed twice
Heinrich Schuchardt [Thu, 21 May 2020 07:22:06 +0000 (09:22 +0200)]
efi_loader: check device path is not installed twice

Prior to corrective patches for virtio and SATA devices the same device
path was installed on two different handles. This is not allowable.
With this patch we will throw an error if this condition occurs for
block devices.

Update a comment for the installation of the simple file system
protocol.

Reported-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: device path for SATA devices
Heinrich Schuchardt [Wed, 20 May 2020 21:12:02 +0000 (23:12 +0200)]
efi_loader: device path for SATA devices

Provide device path nodes for SATA devices.

This avoids creation of two handles with the same device path indicating
our root node.

This is what the device paths for a SATA drive with four partitions could
like:

/VenHw(..)/Sata(0x0,0xffff,0x0)
/VenHw(..)/Sata(0x0,0xffff,0x0)/HD(1,MBR,0x81ea591f,0x800,0x63ff830)
/VenHw(..)/Sata(0x0,0xffff,0x0)/HD(2,MBR,0x81ea591f,0x6400800,0x9ff830)
/VenHw(..)/Sata(0x0,0xffff,0x0)/HD(3,MBR,0x81ea591f,0x6e00800,0x16ef2ab0)
/VenHw(..)/Sata(0x0,0xffff,0x0)/HD(4,MBR,0x81ea591f,0x1dcf3800,0x1dcedab0)

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: device path for virtio block devices
Heinrich Schuchardt [Wed, 20 May 2020 20:39:35 +0000 (22:39 +0200)]
efi_loader: device path for virtio block devices

The UEFI specification does not define a device sub-type for virtio.
Let's use a vendor hardware node here.

This avoids creation of two handles with the same device path indicating
our root node.

Reported-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: initialize root node first
Heinrich Schuchardt [Wed, 20 May 2020 19:27:29 +0000 (21:27 +0200)]
efi_loader: initialize root node first

With commit 16ad946f41d3 ("efi_loader: change setup sequence") the
detection of block device was moved to the start of the initialization
sequence. In the case of virtio devices two handles with the same device
path being created.

The root node handle should be created before anything else.

Reported-by: Ard Biesheuvel <ardb@kernel.org>
Fixes: 16ad946f41d3 ("efi_loader: change setup sequence")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: add EFI_MEMORY_SP to memory attributes
Heinrich Schuchardt [Tue, 19 May 2020 05:20:46 +0000 (07:20 +0200)]
efi_loader: add EFI_MEMORY_SP to memory attributes

The UEFI 2.8 specification has introduced the EFI_MEMORY_SP memory
attribute. Add it to the 'efidebug memmap' and 'efi mem' commands.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoefi_loader: Remove unnecessary debug
Pragnesh Patel [Tue, 19 May 2020 10:13:34 +0000 (15:43 +0530)]
efi_loader: Remove unnecessary debug

Remove unnecessary debug() from efi_set_variable_common().
native_name is NULL, so there is no meaning to print it.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Tom Rini [Wed, 20 May 2020 12:46:56 +0000 (08:46 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds
- QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based
  platforms
- Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property

4 years agoMerge branch '2020-05-19-misc-fixes'
Tom Rini [Wed, 20 May 2020 12:22:17 +0000 (08:22 -0400)]
Merge branch '2020-05-19-misc-fixes'

- Assorted minor fixes

4 years agosh: Enable ffunction-sections and fdata-sections
Marek Vasut [Sun, 3 May 2020 15:22:43 +0000 (17:22 +0200)]
sh: Enable ffunction-sections and fdata-sections

Enable these two options to let compiler eliminate unused code.
On R2Dplus, this results in considerable amount of saved space:

      text    data     bss     dec     hex filename
  - 266580   13196   39076  318852   4dd84 u-boot
  + 220214   12797   38745  271756   4258c u-boot

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Tom Rini <trini@konsulko.com>
4 years agoARM: dts: rmobile: Enable eMMC DDR52 modes on Gen3 Salvator-X(S),ULCB,Ebisu
Marek Vasut [Sun, 8 Mar 2020 17:25:09 +0000 (18:25 +0100)]
ARM: dts: rmobile: Enable eMMC DDR52 modes on Gen3 Salvator-X(S),ULCB,Ebisu

Enable DDR52 modes, since the SD core supports correct switching now.
For completeness, list HS200 modes, however those were already enabled.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4 years agoARM: rmobile: Enable support for OpTee on Gen3
Marek Vasut [Sat, 11 Apr 2020 18:54:02 +0000 (20:54 +0200)]
ARM: rmobile: Enable support for OpTee on Gen3

Enable OpTee support on R-Car Gen3, so that U-Boot would copy the
OpTee /firmware and /reserved-memory nodes into the Linux DT.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
4 years agoARM: rmobile: Merge prior-stage firmware DT fragment into U-Boot DT on Gen3
Marek Vasut [Sat, 11 Apr 2020 18:50:24 +0000 (20:50 +0200)]
ARM: rmobile: Merge prior-stage firmware DT fragment into U-Boot DT on Gen3

The prior-stage firmware generates DT fragment containing the /firmware
node, /reserved-memory node and /memory@ nodes. Merge these nodes into
the U-Boot DT, so U-Boot can use this information.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
4 years agoARM: dts: rmobile: Reserve space in R-Car Gen3 DTs
Marek Vasut [Sat, 11 Apr 2020 18:49:49 +0000 (20:49 +0200)]
ARM: dts: rmobile: Reserve space in R-Car Gen3 DTs

Reserve 4 kiB of space in R-Car Gen3 DTs when those DTs are compiled
to permit patching in OpTee-OS /firmware node, /reserved-memory node
and possibly also additional /memory@ nodes.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
4 years agofdtdec: Add weak function to patch U-Boot DT right after fdtdec_setup()
Marek Vasut [Sat, 11 Apr 2020 19:18:59 +0000 (21:18 +0200)]
fdtdec: Add weak function to patch U-Boot DT right after fdtdec_setup()

Add weak function which is called right after fdtdec_setup() configured
the U-Boot DT. This permits board-specific adjustments to the U-Boot DT
before U-Boot starts parsing the DT. This could be used e.g. to patch in
various custom nodes or merge in DT fragments from prior-stage firmware.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
4 years agolibfdt: Export overlay_apply_node() as fdt_overlay_apply_node()
Marek Vasut [Sat, 11 Apr 2020 18:43:07 +0000 (20:43 +0200)]
libfdt: Export overlay_apply_node() as fdt_overlay_apply_node()

This function is useful to merge a subset of DT into another DT, for
example if some prior-stage firmware passes a DT fragment to U-Boot
and U-Boot needs to merge it into its own DT. Export this function
to permit implementing such functionality.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
4 years agocmd: avb: free partition buffer upon verify completion
Gary Bisson [Mon, 11 May 2020 10:11:53 +0000 (12:11 +0200)]
cmd: avb: free partition buffer upon verify completion

Doing the same as the unittests for libavb [1].

Allows to run 'avb verify' multiple times which can be useful after a
failure to be able to re-flash the partition and try again.

[1]
https://android.googlesource.com/platform/external/avb/+/refs/tags/android-9.0.0_r37/test/avb_slot_verify_unittest.cc#156

Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
4 years agodrivers: crypto: mod_exp_sw: Re-add DM_FLAG_PRE_RELOC
Jan Kiszka [Thu, 7 May 2020 18:36:03 +0000 (20:36 +0200)]
drivers: crypto: mod_exp_sw: Re-add DM_FLAG_PRE_RELOC

This driver is safe to use in SPL without relocation. Denying
DM_FLAG_PRE_RELOC prevents its usability for verifying the main U-Boot
or other artifacts from the SPL unless needless enabling the full driver
set (SPL_OF_PLATDATA).

Fixes: 17e117408571 ("drivers: crypto: rsa_mod_exp: avoid DM_FLAG_PRE_RELOC")
CC: Heinrich Schuchardt <xypron.glpk@gmx.de>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
4 years agotest: Use ut_asserteq_mem() where possible
Simon Glass [Sun, 10 May 2020 18:52:45 +0000 (12:52 -0600)]
test: Use ut_asserteq_mem() where possible

Quite a few tests still use ut_assertok(memcmp(...)) and variants. Modify
them to use the macro designed for this purpose.

Suggested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
4 years agompc83xx, abb: remove suvd3 board
Heiko Schocher [Tue, 18 Feb 2020 17:03:51 +0000 (18:03 +0100)]
mpc83xx, abb: remove suvd3 board

the mpc83xxx suvd3 variant is not longer used, so
remove it.

Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agompc83xx: remove redundant MPC83xx_RESET #define
Rasmus Villemoes [Mon, 4 May 2020 22:21:18 +0000 (00:21 +0200)]
mpc83xx: remove redundant MPC83xx_RESET #define

This macro is only used (tested for existence) in mpc83xx.c, which
unconditionally includes mpc83xx.h where it is unconditionally
defined. Removing it makes the remaining code easier to read.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
4 years agoMerge branch '2020-05-18-reduce-size-of-common.h'
Tom Rini [Tue, 19 May 2020 14:51:43 +0000 (10:51 -0400)]
Merge branch '2020-05-18-reduce-size-of-common.h'

Bring in the latest round of Simon's changes to reduce what's in
<common.h> overall.

4 years agoconfigs: ls2080aqds_tfa_defconfig: enable DM_ETH and related
Ioana Ciornei [Mon, 18 May 2020 11:48:37 +0000 (14:48 +0300)]
configs: ls2080aqds_tfa_defconfig: enable DM_ETH and related

Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LS2080AQDS board.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT support
Ioana Ciornei [Mon, 18 May 2020 11:48:36 +0000 (14:48 +0300)]
arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT support

Add support for selecting the appropriate DTS file depending on the
SERDES protocol used.

The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS
file specifically made for the current SERDES protocol.

This patch adds the necessary DPMAC nodes (DPMAC 1-8) for
protocol 42 (0x2A) on SD#1.

Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled
implement the board_fit_config_name_match() function in order to choose
the appropriate DTS.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoboard: ls2080aqds: transition to DM_ETH
Ioana Ciornei [Mon, 18 May 2020 11:48:35 +0000 (14:48 +0300)]
board: ls2080aqds: transition to DM_ETH

In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated.  Also, force the PCI devices to be enumerated at probe
time.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls1088aqds_tfa_defconfig: enable DM_ETH and related
Ioana Ciornei [Fri, 15 May 2020 06:56:50 +0000 (09:56 +0300)]
configs: ls1088aqds_tfa_defconfig: enable DM_ETH and related

Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LS1088AQDS board.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoboard: ls1088aqds: transition to DM_ETH
Ioana Ciornei [Fri, 15 May 2020 06:56:49 +0000 (09:56 +0300)]
board: ls1088aqds: transition to DM_ETH

In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated.  Also, force the PCI devices to be enumerated at probe
time.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarm: dts: ls1088aqds: add CONFIG_MULTI_DTB_FIT support
Ioana Ciornei [Fri, 15 May 2020 06:56:48 +0000 (09:56 +0300)]
arm: dts: ls1088aqds: add CONFIG_MULTI_DTB_FIT support

Add support for selecting the appropriate DTS file depending on the
SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if
there isn't a DTS file specifically made for the current SERDES
protocol.

This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found
on the SERDES protocols 21(0x15) and 29(0x1d) for SD#1.

On the LS1088AQDS board EMDIO1 is used with two onboard RGMII PHYs
(Realtek RTL8211FD-CG), as well as 2 input/output connectors for
mezzanine cards. Configuration signals from the Qixis FPGA control the
routing of the external MDIOs.

Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one
of the 2 IO slots. As a consequence, a new node is added to
describe register 0x54 as a MDIO mux controlled with child nodes
describing all the IO slots as MDIO buses.

Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled
implement the board_fit_config_name_match() function in order to choose
the appropriate DTS.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoinclude/configs: ls1046afrwy: add support for boot targets.
Pramod Kumar [Wed, 29 Apr 2020 09:30:41 +0000 (15:00 +0530)]
include/configs: ls1046afrwy: add support for boot targets.

ls1046afrwy does not support sata boot.
So Override default BOOT_TARGET_DEVICES
and support only  mmc, usb and dhcp as boot targets.

Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agonet: fsl-mc: fixup DPC: add /board/ports node if missing
Razvan Ionut Cirjan [Tue, 28 Apr 2020 13:09:59 +0000 (16:09 +0300)]
net: fsl-mc: fixup DPC: add /board/ports node if missing

The DPC fixup for MAC address and enet_if is not made if
/board/ports node is missing in DPC file.
Add /board/ports or /ports nodes if them are missing.

Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Reviewed-by: Ioana Ciornei <Ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoboard_r: Detect ifc-nor flash at run-time
Pankit Garg [Thu, 30 Apr 2020 10:24:05 +0000 (15:54 +0530)]
board_r: Detect ifc-nor flash at run-time

CONFIG_MTD_NOR_FLASH flag needs to be enable for all
boot sources,as all flash drivers need to compile in
TFA Boot.Probe ifc nor flash only when there is nor
flash available on board.So needs to detect ifc-nor
flash at run-time for probing.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: lx2160aqds_tfa_defconfig: enable DM_ETH and related
Ioana Ciornei [Mon, 27 Apr 2020 12:21:17 +0000 (15:21 +0300)]
configs: lx2160aqds_tfa_defconfig: enable DM_ETH and related

Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LX2160AQDS board.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoboard: lx2160aqds: implement board_fit_config_name_match
Ioana Ciornei [Mon, 27 Apr 2020 12:21:16 +0000 (15:21 +0300)]
board: lx2160aqds: implement board_fit_config_name_match

In case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the
board_fit_config_name_match() function in order to choose the
appropriate DTS for the current SERDES protocol configuration.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoboard: lx2160aqds: transition to DM_ETH
Ioana Ciornei [Mon, 27 Apr 2020 12:21:15 +0000 (15:21 +0300)]
board: lx2160aqds: transition to DM_ETH

In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated.  Also, force the PCI devices to be enumerated at probe
time.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarm: dts: lx2160aqds: add nodes describing possible mezzanine cards
Ioana Ciornei [Mon, 27 Apr 2020 12:21:14 +0000 (15:21 +0300)]
arm: dts: lx2160aqds: add nodes describing possible mezzanine cards

Add device trees describing possible uses of mezzanine cards depending
on the SERDES protocol employed.

This patch adds DPAA2 networking support for the following protocols on
each SERDES block:
 * SD #1: 3, 7, 19, 20
 * SD #2: 11

Each SERDES block has a different device tree file per protocol
supported, where the IO SLOTs used are enabled and PHYs located on the
mezzanine cards are described. Also, dpmac nodes are edited and their
associated phy-connection-type and phy-handle are added.

Top DTS files are also added for each combination of protocol on the 3
SERDES blocks.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarm: dts: lx2160aqds: add MDIO slots
Ioana Ciornei [Mon, 27 Apr 2020 12:21:13 +0000 (15:21 +0300)]
arm: dts: lx2160aqds: add MDIO slots

The LX2160A processor has two external MDIO interfaces, described in the
DTS as emdio1 and emdio2.

On the LX2160AQDS board EMDIO1 is used with two onboard RGMII PHYs
(Realtek RTL8211FD-CG), as well as eight input/output connectors for
mezzanine cards. Configuration signals from the Qixis FPGA control the
routing of the external MDIOs.

Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one
of the 8 IO slots. As a consequence, a new node is added to
describe register 0x54 as a MDIO mux controlled with child nodes
describing all the IO slots as MDIO buses.

Also, DPMAC 17 and 18 are updated to reference the on-board PHYs.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoarm: dts: lx2160a: add noted for dpmacs 1, 2, 5-6
Ioana Ciornei [Mon, 27 Apr 2020 12:21:12 +0000 (15:21 +0300)]
arm: dts: lx2160a: add noted for dpmacs 1, 2, 5-6

Add nodes for DPMACs 1, 2 and 5-6 which were missing from the
description. These will be later used on the LX2160AQDS specific DTS.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agodrivers: net: fsl-mc: fixup msi-map property
Laurentiu Tudor [Mon, 4 May 2020 11:47:11 +0000 (14:47 +0300)]
drivers: net: fsl-mc: fixup msi-map property

Similarly to iommu-map, the msi-map property must also be fixed up
in the device tree, in order for the icid -> streamid translation
be possible in the MSI case as well.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Diana Craciun <diana.craciun@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agodriver: net: fm: minor fix in DM ETH support
Madalin Bucur [Mon, 4 May 2020 10:09:12 +0000 (13:09 +0300)]
driver: net: fm: minor fix in DM ETH support

Bus callback functions for read/write/reset need to be set only for
DM_ETH, moving endif a bit lower.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls1012a: Unset ENV_ADDR value
Kuldeep Singh [Mon, 4 May 2020 06:04:55 +0000 (11:34 +0530)]
configs: ls1012a: Unset ENV_ADDR value

LS1012A-FRWY and LS1012A-RDB crashes in flash environment when
CONFIG_ENV_ADDR value is set. Unset the config value in *_tfa_defconfig*
to resolve booting crash.

Following crash is observed:
    Using SERDES1 Protocol: 13576 (0x3508)
    "Synchronous Abort" handler, esr 0x96000006
    elr: 00000000820452c0 lr : 0000000082013f54 (reloc)
    elr: 00000000b7b932c0 lr : 00000000b7b61f54
    x0 : 0000000000000000 x1 : 000000007604e004
    x2 : 0000000000000001 x3 : 0000000000000000
    ...
    Code: 54ffff80 9100c000 17fffff7 f9402241 (3860c820)
    Resetting CPU ...

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: nxp: Enable CONFIG_SYS_RELOC_GD_ENV_ADDR
Kuldeep Singh [Sat, 14 Dec 2019 14:02:56 +0000 (19:32 +0530)]
configs: nxp: Enable CONFIG_SYS_RELOC_GD_ENV_ADDR

Commit 323d3af59fe4 ("configs: ls1012ardb: Enable
CONFIG_SYS_RELOC_GD_ENV_ADDR") enables the config only for LS1012ARDB.

Apart from LS1012A-RDB, other platforms such as LS1012A-FRWY, LS2088A
and LS1046A-RDB/FRWY also require this config to be enabled. This also
helps in resolving booting crash observed in flash environment.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls1012a: Reduce CONFIG_ENV_SIZE to 0x2000
Ashish Kumar [Wed, 29 Apr 2020 12:12:03 +0000 (17:42 +0530)]
configs: ls1012a: Reduce CONFIG_ENV_SIZE to 0x2000

All LS1012A board variants have same CONFIG_ENV_SECT_SIZE and
CONFIG_ENV_SIZE values. If both config values are same, flash
environment cannot be saved. Since, CONFIG_ENV_SECT_SIZE needs to be
same as that of flash sector size, this entry cannot be changed.
Reduce CONFIG_ENV_SIZE value to 0x2000. This also helps in making config
value aligned with other boards environemt size.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.kumar@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN size
Kuldeep Singh [Tue, 12 May 2020 09:28:51 +0000 (14:58 +0530)]
configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN size

CONFIG_SYS_MALLOC_LEN is currently set to low value and leaves very less
space to do malloc in flash environmet. Increase the value to get more
memory and also make it align with other boards(ls1046a, ls1043a etc.)
config values.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls2080ardb: Make BOOT command access flash memory as per spi-mem
Kuldeep Singh [Fri, 7 Feb 2020 16:45:18 +0000 (22:15 +0530)]
configs: ls2080ardb: Make BOOT command access flash memory as per spi-mem

BOOT command currently access spi-nor flash memory directly. As per spi-mem
framework, flash memory access via absolute addresses is no more possible.
Use flash APIs to access memory instead of directly using it.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls2080ardb: Make MC_INIT access flash memory as per spi-mem
Kuldeep Singh [Fri, 7 Feb 2020 16:39:09 +0000 (22:09 +0530)]
configs: ls2080ardb: Make MC_INIT access flash memory as per spi-mem

MC_INIT command currently access spi-nor flash memory directly. As per
spi-mem framework, flash memory access via absolute addresses is no more
possible. Use flash APIs to access memory instead of directly using it.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls1046a: Define ENV_ADDR value
Kuldeep Singh [Tue, 12 May 2020 09:09:46 +0000 (14:39 +0530)]
configs: ls1046a: Define ENV_ADDR value

CONFIG_ENV_ADDR helps in picking environment from flash before DDR init.
The macro value is already defined in ls1046ardb_tfa_defconfig, also
define the value as 0x40300000 in qspi_defconfig.

ls1046aqds has one spansion flash "S25FL128S_64K" of size 16M with
sector size 64K. Correct ENV_ADDR and ENV_SECT_SIZE value for QSPI and
TFA defconfigs of the board.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls2080a: Correct ENV_ADDR value
Kuldeep Singh [Tue, 11 Feb 2020 09:26:42 +0000 (14:56 +0530)]
configs: ls2080a: Correct ENV_ADDR value

CONFIG_ENV_ADDR helps in picking environment from flash before DDR init.
QSPI region in LS2088ARDB and LS2088AQDS starts from 0x20000000 offset.
Correct the config value i.e 0x80500000 -> 0x20500000.

Also, define config value as 0x20300000 in qspi defconfig.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls1088a: Correct ENV_ADDR value
Kuldeep Singh [Tue, 11 Feb 2020 09:21:35 +0000 (14:51 +0530)]
configs: ls1088a: Correct ENV_ADDR value

CONFIG_ENV_ADDR helps in picking environment from flash before DDR init.
QSPI region starts from 0x20000000 offset.
Correct the config value i.e 0x80500000 -> 0x20500000.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agotreewide: Update fsl qspi node dt properties as per spi-mem driver
Kuldeep Singh [Thu, 12 Dec 2019 06:19:24 +0000 (11:49 +0530)]
treewide: Update fsl qspi node dt properties as per spi-mem driver

According to new qspi driver, some properties like "bus-num, num-cs,
big-endian" are no longer used. Device endiannes can be determined from
device-type data in driver.

Now use board specific compatibles, generic node names and specific
labels to align with linux device-tree properties.

Also consolidate spi-max-frequency to 50Mhz treewide.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls1046a: Move SPI_FLASH_SPANSION to defconfig
Kuldeep Singh [Tue, 12 May 2020 09:02:39 +0000 (14:32 +0530)]
configs: ls1046a: Move SPI_FLASH_SPANSION to defconfig

Enable CONFIG_SPI_FLASH_SPANSION in defconfigs of LS1046ARDB and
LS1046AQDS which have two spansion flases i.e s25fs512s each of size
64M.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls1012a: Enable CONFIG_SPI_FLASH_SPANSION in defconfigs
Kuldeep Singh [Tue, 12 May 2020 09:01:07 +0000 (14:31 +0530)]
configs: ls1012a: Enable CONFIG_SPI_FLASH_SPANSION in defconfigs

Since CONFIG_FSL_QSPI is already enabled for LS1012A in defconfigs. Also
enable CONFIG_SPI_FLASH_SPANSION for LS1012A boards having spansion
flashes.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agoconfigs: ls1043a: Move CONFIG_FSL_QSPI and SPI_FLASH_SPANSION to defconfig
Kuldeep Singh [Tue, 12 May 2020 08:58:56 +0000 (14:28 +0530)]
configs: ls1043a: Move CONFIG_FSL_QSPI and SPI_FLASH_SPANSION to defconfig

Move CONFIG_FSL_QSPI to the board defconfigs and while at it also move
CONFIG_SPI_FLASH_SPANSION for LS1043AQDS.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agotreewide: Remove unused FSL QSPI config options for Layerscape platforms
Kuldeep Singh [Tue, 12 May 2020 07:24:07 +0000 (12:54 +0530)]
treewide: Remove unused FSL QSPI config options for Layerscape platforms

Some of these options are not used by the driver anymore and some of
them are obsolete as the information is gathered from the dt. Also
consolidating defines in common headers.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
4 years agocommon: Drop linux/bitops.h from common header
Simon Glass [Sun, 10 May 2020 17:40:13 +0000 (11:40 -0600)]
common: Drop linux/bitops.h from common header

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoUse __ASSEMBLY__ as the assembly macros
Simon Glass [Sun, 10 May 2020 17:40:12 +0000 (11:40 -0600)]
Use __ASSEMBLY__ as the assembly macros

Some places use __ASSEMBLER__ instead which does not work since the
Makefile does not define it. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agocommon: Drop linux/delay.h from common header
Simon Glass [Sun, 10 May 2020 17:40:11 +0000 (11:40 -0600)]
common: Drop linux/delay.h from common header

Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>