Marek Vasut [Sun, 15 Mar 2020 14:40:15 +0000 (15:40 +0100)]
net: smc911x: Rename smc911x_rx() to smc911x_recv()
Rename the function to keep the naming scheme consistent,
no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Marek Vasut [Sun, 15 Mar 2020 14:14:18 +0000 (15:14 +0100)]
net: smc911x: Replace malloc()+memset() with calloc()
Replace combination of malloc()+memset() with calloc() as the behavior
is exactly the same and the amount of code is reduced.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Marek Vasut [Sat, 14 Mar 2020 23:08:31 +0000 (00:08 +0100)]
net: smc911x: Remove pkt_data_{push,pull}
These functions are never used and are likely a pre-DM remnant
from times long past, just remove them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Marek Vasut [Sun, 12 Apr 2020 21:49:25 +0000 (23:49 +0200)]
net: rtl8139: Fill in SPDX tag
The rtl8139 driver is derived from Etherboot driver, which is in
turn derived from Linux 8139too driver added in Linux 2.2.18pre14.
An undocumented change in Linux 2.4.10.2 added a new field to the
driver, MODULE_LICENSE("GPL"); . According to current Linux kernel
licensing rules, Documentation/process/license-rules.rst, quote:
"GPL" Module is licensed under GPL version 2. This
does not express any distinction between
GPL-2.0-only or GPL-2.0-or-later. The exact
license information can only be determined
via the license information in the
corresponding source files.
And since the code does not contain any "future" clause, the tag
is therefore GPL-2.0 only.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 21:12:11 +0000 (23:12 +0200)]
net: rtl8139: Move functions around
Just move functions around in preparation for easy DM conversion,
rename rtl_bcast_addr() to rtl8139_bcast_addr(), no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 21:01:45 +0000 (23:01 +0200)]
net: rtl8139: Finish cleanup
Finish the checkpatch cleanup of the driver, fix the remaining issues
in probe and init function and in global variables, rename the probe
function to rtl8139_init(), no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 20:58:27 +0000 (22:58 +0200)]
net: rtl8139: Factor out hardware reset
This hardware reset and reset-wait implementation was twice in the
driver, factor it out into a separate function. This really should
use wait_for_bit() eventually and return -ETIMEDOUT, but thus far,
handling of any of this is missing from the driver. This must be
added later. Thus far, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 20:55:40 +0000 (22:55 +0200)]
net: rtl8139: Minor cleanup of rtl_disable()
Rename the function to rtl8139_stop(), clean up checkpatch errors in
the stop polling function. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 20:43:16 +0000 (22:43 +0200)]
net: rtl8139: Minor cleanup of rtl_poll()
Rename the function to rtl8139_recv(), clean up various checkpatch errors,
line-over-80 conditions, and malformed comments. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 20:40:45 +0000 (22:40 +0200)]
net: rtl8139: Minor cleanup of rtl_transmit()
Rename the function to rtl8139_send(), clean up the TX polling, the TX
OK condition at the end, overuse of typecasts, and various line-over-80
problems. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 19:41:56 +0000 (21:41 +0200)]
net: rtl8139: Minor cleanup of rtl_reset()
Rename the function to rtl8139_reset(), clean up the reset polling
and various line-over-80 problems. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 19:35:12 +0000 (21:35 +0200)]
net: rtl8139: Minor cleanup of set_rx_mode()
Rename the function to rtl8139_set_rx_mode(), use unsigned variables
where applicable and inline mc_filter[] values. No functional chanage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 19:30:38 +0000 (21:30 +0200)]
net: rtl8139: Consistently use rtl8139_rx_config
This string of macros is exactly the same thing as rtl8139_rx_config,
so just use rtl8139_rx_config. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 19:28:30 +0000 (21:28 +0200)]
net: rtl8139: Minor cleanup of read_eeprom()
Rename the function to rtl8139_read_eeprom() to keep the naming
consistent, keep the variables sorted in reverse xmas tree. No
functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 19:20:31 +0000 (21:20 +0200)]
net: rtl8139: Rework eeprom_delay() macro
The macro assumes ee_addr variable to be present when it's being
used. Rework the macro into a function instead and pass it an
argument specifying the register base address, to make it future
proof for DM conversion.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 12 Apr 2020 18:47:26 +0000 (20:47 +0200)]
net: rtl8139: Register macro cleanup
Clean up the horrible register definitions in the RTL8139 driver.
This does create a couple of checkpatch errors, but the driver is
full of them anyway, and those will be cleaned up later.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Mon, 23 Mar 2020 01:11:46 +0000 (02:11 +0100)]
net: dwc_eth_qos: Prevent DMA from writing updated RX DMA descriptor
The DMA may attempt to write a DMA descriptor in the ring while it is
being updated. By writing the DMA descriptor buffer address to 0, it
is assured the DMA will not use such a buffer and the buffer can be
updated without any interference.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Marek Vasut [Mon, 23 Mar 2020 01:09:55 +0000 (02:09 +0100)]
net: dwc_eth_qos: Invalidate RX packet DMA buffer
This patch prevents an issue where the RX packet might have been
accessed by the CPU, which now has cached data from the packet in
the caches and possibly various write buffers, and these data may
be evicted from the caches into the DRAM while the buffer is also
written by the DMA.
By invalidating the buffer after the CPU accessed it and before the
DMA populates the buffer, it is assured that the buffer will not be
corrupted.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Marek Vasut [Mon, 23 Mar 2020 01:09:21 +0000 (02:09 +0100)]
net: dwc_eth_qos: Invalidate RX descriptor before reading
The current code polls the RX desciptor ring for new packets by reading
the RX descriptor status. This works by accident, as the RX descriptors
are often in non-cacheable memory. However, the driver does support use
of RX descriptors in cacheable memory.
This patch adds a missing RX descriptor invalidation, which assures the
CPU will read a fresh copy of the RX descriptor instead of a cached one.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Marek Vasut [Mon, 23 Mar 2020 01:09:01 +0000 (02:09 +0100)]
net: dwc_eth_qos: Flush the RX descriptors on init
Currently the code only flushes the first RX descriptor, not every entry
in the RX descriptor ring. Fix this, to make sure the DMA engine can pick
the RX descriptors correctly.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Marek Vasut [Mon, 23 Mar 2020 01:03:50 +0000 (02:03 +0100)]
net: dwc_eth_qos: Correctly wrap around TX descriptor tail pointer
This code programs the next descriptor in the TX descriptor ring into
the hardware as the last valid TX descriptor. The problem is that if
the currenty descriptor is the last one in the array, the code will
not wrap around correctly and use TX descriptor 0 again, but instead
will use TX descriptor at address right past the TX descriptor ring,
which is the first descriptor in the RX ring.
Fix this by adding the necessary wrap-around.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Marek Vasut [Mon, 23 Mar 2020 01:02:57 +0000 (02:02 +0100)]
net: dwc_eth_qos: Fully rewrite RX descriptor field 3
The RX descriptor field 3 should contain only OWN and BUF1V bits before
being used for receiving data by the DMA engine. However, right now, if
the descriptor was already used for receiving data and is being cleared,
the field 3 is only modified and the aforementioned two bits are ORRed
into the field. This could lead to a residual dirty bits being left in
the field 3 from previous transfer, and it generally does. Fully set the
field 3 instead to clear those residual dirty bits.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Marek Vasut [Sun, 19 Apr 2020 02:05:44 +0000 (04:05 +0200)]
net: dc2114x: Switch DEBUG_SROM{,2} to debug_cond()
Replace the adhoc debugging ifdeffery with debug_cond() and an
internal SROM_DEBUG macro to select the debug level.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 19 Apr 2020 02:00:49 +0000 (04:00 +0200)]
net: dc2114x: Reorganize driver
Move the functions in the driver around to better fit future DM
conversion, drop function forward declarations. No functional
change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 19 Apr 2020 01:40:03 +0000 (03:40 +0200)]
net: dc2114x: Clean up INL/OUTL functions
Rename these functions to dc2114x_{inl,outl}(), use u32 values in
them instead of plain signed integers as all those values are in
fact register values and the driver code does bitwise operations
on them. No functional change intended.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 19 Apr 2020 01:36:46 +0000 (03:36 +0200)]
net: dc2114x: Clean up DE4X5 macros
Replace these macros with static functions to permit the compiler to
do type checking on the functions. The INL()/OUTL() functions have to
be moved in this patch as well, as those DE4X5 macros are using them.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 19 Apr 2020 01:09:26 +0000 (03:09 +0200)]
net: dc2114x: Clean up remaining driver code
Clean up the remaining driver code, macro space alignment, function
declaration indent, replace __attribute__((aligned(32))) with plain
__aligned(32). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 19 Apr 2020 01:11:06 +0000 (03:11 +0200)]
net: dc2114x: Clean up SROM operations
Clean up the SROM accessors to bring them up to standards with
U-Boot coding style. Sort variable into reverse xmas tree. No
functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 19 Apr 2020 01:10:50 +0000 (03:10 +0200)]
net: dc2114x: Clean up send_setup_frame()
Clean up the send_setup_frame() to bring it up to standards with
U-Boot coding style, invert the loops where applicable to cut
down the level of indent. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 19 Apr 2020 01:10:30 +0000 (03:10 +0200)]
net: dc2114x: Clean up dc21x4x_halt()
Clean up the driver halt code to bring it up to standards with
U-Boot coding style. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 19 Apr 2020 01:10:25 +0000 (03:10 +0200)]
net: dc2114x: Clean up dc21x4x_recv()
Clean up the driver recv code to bring it up to standards with
U-Boot coding style. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 19 Apr 2020 01:10:14 +0000 (03:10 +0200)]
net: dc2114x: Clean up dc21x4x_send()
Clean up the driver send code to bring it up to standards with
U-Boot coding style, invert the loops where applicable to cut
down the level of indent. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 19 Apr 2020 01:09:47 +0000 (03:09 +0200)]
net: dc2114x: Clean up init code
Clean up the driver init code to bring it up to standards with
U-Boot coding style, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sat, 18 Apr 2020 03:11:05 +0000 (05:11 +0200)]
net: pcnet: Switch to PCI memory access
Replace the PCI IO access with PCI memory access, the card
supports both, but the former does not work with QEMU SH4.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sat, 18 Apr 2020 00:32:19 +0000 (02:32 +0200)]
net: pcnet: Replace mips-specific accessors
Replace mips-specific UNCACHED_SDRAM() macro with standard
map_physmem(), which permits the driver to work on other
systems than mips.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Fri, 17 Apr 2020 23:56:51 +0000 (01:56 +0200)]
net: tulip: Remove CONFIG_TULIP_*
These macros are not used by any board, remove them to simplify
the driver. The EEPROM accessors are still retained however, as
those might still be useful.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Fri, 17 Apr 2020 23:44:12 +0000 (01:44 +0200)]
net: pcnet: Remove CONFIG_PCNET_79C97x
These macros guard one switch-case statement, which grows mips malta
by some 20 bytes if debug is enabled, and even less if it is not. To
make the code simpler, just support all the NICs and be done with it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sat, 4 Apr 2020 10:21:57 +0000 (12:21 +0200)]
net: Fix warning when including netdev.h on DM systems
If the DM_ETH is enabled and netdev.h is included somewhere, the
struct eth_device may not be defined, yet it is used in the header
file as an argument to fecmxc_register_mii_postcall. Add forward
declaration to remove the warning.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Deepak Das [Sun, 26 Apr 2020 10:41:50 +0000 (16:11 +0530)]
rockchip: rk3399: Add Nanopi M4 2GB board support
commit
b2f5da9dd068 ("rockchip: rk3399: Add Nanopi M4 board support") added
support for Nanopi M4 board with Dual-Channel 4GB LPDDR3-1866 RAM.
This patch adds another variant of NanoPi M4 board with Dual-Channel
2GB DDR3-1866 RAM.
Signed-off-by: Deepak Das <deepakdas.linux@gmail.com>
Suniel Mahesh [Tue, 28 Apr 2020 10:00:19 +0000 (15:30 +0530)]
rk3399: Add ROC-RK3399-PC Mezzanine board
Add Firefly ROC-RK3399-PC Mezzanine board which is an
extension board on top of roc-rk3399-pc.
Will drop the separate defconfig file, once we support
the board detection at runtime.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 28 Apr 2020 10:00:18 +0000 (15:30 +0530)]
arm: dts: rk3399: Sync roc-pc-mezzanine from v5.7-rc1
Sync Firefly ROC-RK3399-PC Mezzanine Board dts file
from Linux v5.7-rc1.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 28 Apr 2020 10:00:17 +0000 (15:30 +0530)]
arm64: dts: rk3399: Sync v5.7-rc1 from Linux
Sync rk3399 dts(i) files from v5.7-rc1 linux-next.
Reason:
To get updated PCIe nodes and properties on respective
dts(i) files.
Summary:
- sync won't include new board dts(i)
- sync will add required files used on respective dts(i)
- rk3399-puma-u-boot.dtsi spiflash label changed to norflash
- move puma.dtsi bios_enable into rk3399-puma-u-boot.dtsi
- move legacy max-frequency of sdhci into rk3399-u-boot.dtsi
- update cross-ec-[keyboard|sbs].dtsi path as per U-Boot
- keep roc-rk3399-pc dc_12v changes to -u-boot.dtsi
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 28 Apr 2020 10:00:16 +0000 (15:30 +0530)]
clk: rk3399: Set empty for HCLK_SD assigned-clocks
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have HCLK_SD assigned-clocks which are usually required for
Linux and don't require to handle them in U-Boot.
assigned-clocks = <&cru HCLK_SD>;
So, mark them as empty in clock otherwise device probe on
those SD controllers would fail.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 28 Apr 2020 10:00:15 +0000 (15:30 +0530)]
arm64: dts: rk3399-evb: Move u-boot properties into -u-boot.dtsi
Move U-Boot specific properties into rk3399-evb u-boot
specific dtsi file.
This would help to sync the devicetrees from Linux whenever
required instead of adding specific nodes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 28 Apr 2020 10:00:14 +0000 (15:30 +0530)]
arm64: dts: rk3399-puma: Move u-boot properties into -u-boot.dtsi
Move U-Boot specific properties into rk3399-puma u-boot
specific dtsi file.
This would help to sync the devicetrees from Linux whenever
required instead of adding specific nodes.
Cc: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chen-Yu Tsai [Mon, 27 Apr 2020 06:52:54 +0000 (14:52 +0800)]
rockchip: dts: rock64: Fix XHCI usage
If the VBUS regulator is always-on, XHCI will fail to detect USB 3.0
devices; USB 2.0 devices will work however.
Make the VBUS regulator controllable and tie it to only the XHCI. This
makes all three USB ports usable.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chen-Yu Tsai [Mon, 27 Apr 2020 06:52:53 +0000 (14:52 +0800)]
rockchip: rk3328: Add support for ROC-RK3328-CC board
The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit
card size development board based on the Rockchip RK3328 SoC, with:
- 1/2/4 GB DDR4 DRAM
- eMMC connector for optional module
- micro SD card slot
- 1 x USB 3.0 host port
- 2 x USB 2.0 host port
- 1 x USB 2.0 OTG port
- HDMI video output
- TRRS connector with audio and composite video output
- gigabit Ethernet
- consumer IR receiver
- debug UART pins
The ROC-RK3328-CC has the enable pin of the SD card power switch tied
to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is
muxed by default. SDMMC0_PWREN is an active high signal controlled by
the MMC controller, however the switch enable is active low, and
pulled low (enabled) by default to make things work on boot.
As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable
power to the card. The default GPIO state for the pin is pull-down and
input, which doesn't require extra configuration when paired with the
external pull-down and active low switch.
Deal with this by enabling regulator support in SPL, and setting
"u-boot,dm-spl" for the regulator and other device nodes needed for
muxing the pin.
The device tree file is synced from the Linux kernel next-
20200324.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chen-Yu Tsai [Mon, 27 Apr 2020 06:52:52 +0000 (14:52 +0800)]
rockchip: dts: rk3328: Sync device tree files from Linux
This syncs rk3328 device tree files from the Linux kernel next-
20200324.
The last commit to touch these files is:
b2411befed60 ("arm64: dts: add bus to rockchip amba nodenames")
Additional changes not yet in the Linux kernel include:
arm64: dts: rockchip: rk3328: drop #address-cells, #size-cells from grf node
arm64: dts: rockchip: rk3328: drop non-existent gmac2phy pinmux options
arm64: dts: rockchip: rk3328: Replace RK805 PMIC node name with "pmic"
Changes include:
- conversion of raw pin numbers to macros
- removal of deprecated RK_FUNC_* macros
- update of device tree binding headers
- new devices
- device tree cleanups
- gmac2phy disabled in -u-boot.dtsi as it is not supported in U-boot
This includes a re-ordering of the USB device nodes compared to upstream
Linux, moving the dwc2 OTG controller after the EHCI/OHCI nodes. This is
currently required as otherwise the dwc2 controller would not be able to
detect devices in some cases. This may be due to lack of USB PHY support
in U-boot.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Mon, 27 Apr 2020 06:52:51 +0000 (14:52 +0800)]
rockchip: rk3328: Disable generic PHY support
The USB PHYs on the RK3328 aren't supported, nor are any other generic
PHYs. Because upstream Linux device trees already include the USB PHYs
and references in the USB hosts, this would result in various calls
to the generic PHY API to fail.
Instead, just disable generic PHY support for now.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chen-Yu Tsai [Mon, 27 Apr 2020 06:52:50 +0000 (14:52 +0800)]
dt-bindings: power: rk3328-power: sync from upstream Linux kernel
This syncs the rk3328 power domain header file from Linux kernel
next-
20200324, to support newer hardware blocks when syncing the
device tree files.
The last non-merge commit to touch it was
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Mon, 27 Apr 2020 06:52:49 +0000 (14:52 +0800)]
dt-bindings: clock: rk3328: sync from upstream Linux kernel
This syncs the rk3328 clock header file from Linux kernel next-
20200324,
to support newer hardware blocks when syncing the device tree files.
The last non-merge commit to touch it was
0dc14b013f79 ("clk: rockchip: add clock id for watchdog pclk on rk3328")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Mon, 27 Apr 2020 06:52:48 +0000 (14:52 +0800)]
rockchip: dts: rk3328: Move OTG node's hnp-srp-disable to rk3328-u-boot.dtsi
The "hnp-srp-disable" property for dwc2 is specific to U-boot, not part
of upstream Linux's device tree bindings.
Move it to rk3328-u-boot.dtsi to avoid losing it when syncing device
tree files.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chen-Yu Tsai [Mon, 27 Apr 2020 06:52:47 +0000 (14:52 +0800)]
rockchip: dts: rk3328-evb: Move gmac2io related nodes to -u-boot.dtsi
The device tree file for rk3328-evb in the Linux kernel does not have
gmac2io enabled. Instead, gmac2phy is enabled, but that is not supported
in U-boot.
Move the gmac2io related nodes to rk3328-evb-u-boot.dtsi to preserve the
current functionality. When the device tree files are synced, gmac2phy
should be marked as "broken" in -u-boot.dtsi files.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Chen-Yu Tsai [Mon, 27 Apr 2020 06:52:46 +0000 (14:52 +0800)]
rockchip: dts: rk3328-evb: Move vcc5v0-host-xhci-drv to -u-boot.dtsi
USB 3.0 is only supported in U-boot, not in the Linux kernel where the
device tree files are ultimately synced from. While the xhci node was
moved, the external vbus regulator was not.
Move it as well.
Fixes:
2e91e2025c1b ("rockchip: rk3328: migrate u-boot node to -u-boot.dtsi")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tom Rini [Thu, 30 Apr 2020 22:05:15 +0000 (18:05 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- distro boot support for SPI flash
- sifive spi flash driver
Tom Rini [Thu, 30 Apr 2020 19:11:06 +0000 (15:11 -0400)]
Merge tag 'efi-2020-07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-07-rc2
This pull request contains bug fixes needed due to the merged changes for
EFI secure boot.
Patches are supplied to identify EFI system partitions.
Jagan Teki [Wed, 29 Apr 2020 15:33:53 +0000 (21:03 +0530)]
sifive: fu540: Enable spi-nor flash support
HiFive Unleashed A00 support is25wp256 spi-nor flash,
So enable the same and add test result log for future
reference.
Tested on SiFive FU540 board.
Thanks to Sagar for various use cases and tests.
[QUAD mode in dt with spi-tx-bus-width: <4>]
pp opcode = 0x34 [QUAD MODE]
read opcode = 0x6c [QUAD MODE]
erase opcode = 0x21
SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc
[SPI MODE in dt with spi-tx-bus-width: <1>]
pp opcode = 0x12 [SPI MODE]
read opcode = 0xc [SPI MODE]
erase opcode = 0x21
SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
Jagan Teki [Thu, 23 Apr 2020 17:00:56 +0000 (22:30 +0530)]
riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi
Add U-Boot specific dts file for hifive-unleashed-a00, this
would help to add u-boot specific properties and other node
changes without touching the base dts(i) files which are easy
to sync from Linux.
Added spi2 alias for qspi2 as an initial u-boot specific
property change.
spi probing in current dm model is very much rely on aliases
numbering. Even though the qspi2 can't come under any associated
spi nor flash it would require to specify the same to make proper
binding happen for other spi slaves.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
Jagan Teki [Thu, 23 Apr 2020 17:00:55 +0000 (22:30 +0530)]
spi: sifive: Fix QPP transfer
The guessed reason is that the existing logic of filling
tx fifo with data, rx fifo with NULL for tx transfer and
filling rx fifo with data, tx fifo with NULL for rx transfer
is not clear enough to support the Quad Page Program.
 Â
SiFive SPI controllers have specific sets of watermark
registers and SPI I/O directions bits in order to program
SPI controllers clear enough to support all sets of operating
modes.
 Â
Here is the exact programing sequence that would follow on this
patch and tested via SPI-NOR and MMC_SPI.
 Â
- set the frame format proto, endian
- set the frame format dir, set it for tx and clear it for rx
- TX transfer:
 fill tx fifo with data.
 wait for TX watermark bit to clear.
- RX transfer:
 fill tx fifo with 0xff.
 write nbytes to rx watermark register
 wait for rx watermark bit to clear.
 read the rx fifo data.
So, this patch adopts this program sequence and fixes the existing
I/O direction bit.
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
Jagan Teki [Thu, 23 Apr 2020 17:00:54 +0000 (22:30 +0530)]
spi: sifive: Fix format register proto field
SiFive SPI controller has a proto bit field in frame format
register which would be used to configure the SPI I/O protocol
lines used on specific transfer.Â
Right now the driver is configuring this proto using slave->mode,
for all types of transctions. This makes the driver unable to
function since the proto needs to configure dynamically for
each and every transaction separately at runtime.
Now, the controller driver supports per transfer via spi-mem
exec_opo, so add the fmt_proto flag and fill the per transfer
buswidth so that the controller configures the proto bit at
runtime.
This patch fixes the SPI controller works with SPI NOR flash
on quad read with page program.
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
Jagan Teki [Thu, 23 Apr 2020 17:00:53 +0000 (22:30 +0530)]
spi: sifive: Add spi-mem exec op
SiFive SPI controller is responsible to handle the
slave devices like mmc spi and spi nor flash.
The controller is designed such a way that it would
handle the slave transactions based on the I/O protocol
numbers, example if spi nor slave send quad write opcode
it has to send alone with I/O protocol number of 4 and
if it try to send data it has to send I/O protocol number
along with 4 line data.
But the current spi-xfer code from spi-mem is combining
the opcode and address in a single transaction, so the
SPI controller will be unable to identify the I/O protocol
number of opcode vs address.
So, add the spi-mem exec_op with spi-xfer of opcode, address
and data as a separate transaction. This doesn't remove
the .xfer of dm_spi_ops since mmc spi will make use of it.
Note: This code might have moved to the spi-mem core area
once we have done the dedicated tests on other controllers
and have real reason to move.
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
Kuldeep Singh [Fri, 3 Apr 2020 06:57:42 +0000 (12:27 +0530)]
mtd: spi-nor-ids: Add Spansion s25fs512s flash entry
Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on
various platforms as former is not present. Add the entry.
Linux already has both the flashes present. A snippet below:
{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256...},
{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256...},
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 20 Apr 2020 18:04:13 +0000 (23:34 +0530)]
watchdog: kconfig: Enable designware for rk3399
Enable designware watchdog driver for rk3399 if WDT defined.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 20 Apr 2020 10:06:07 +0000 (15:36 +0530)]
mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256
IS25WP256 flash chips do support 4byte address opcodes,
so enable support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
Jagan Teki [Mon, 20 Apr 2020 10:06:06 +0000 (15:36 +0530)]
mtd: spi-nor: Enable QE bit for ISSI flash
Enable QE bit for ISSI flash chips.
QE enablement logic is similar to what Macronix
has, so reuse the existing code itself.
Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 20 Apr 2020 10:33:46 +0000 (16:03 +0530)]
spi: sifive: Tidy up dm_spi_slave_platdata variable
Usually variable name slave is used for spi_slave structure
and slave_plat for the dm_spi_slave_platdata.
Let's follow this meaningful notation by replacing slave
with slave_plat for dm_spi_slave_platdata structure.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Jagan Teki [Fri, 10 Apr 2020 18:26:31 +0000 (23:56 +0530)]
rk3399: Enable SF distro bootcmd
Enable SPI flash(SF) distro boot command in rk3399.
This distro boot will read the boot script at specific
location at the flash and start sourcing the same.
Included the SF device at the last of the target devices
list since all the rest of the devices on the list have
more possibility to boot the distribution due to the
size of the SPI flash is concern.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Thu, 30 Apr 2020 17:00:20 +0000 (13:00 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- DM ACPI support (Part A)
- Improve support for chain-loading x86 U-Boot
Tom Rini [Thu, 30 Apr 2020 15:31:33 +0000 (11:31 -0400)]
Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2020.07-rc2
mmc:
- Fix dt property handling via generic function
clk:
- Fix versal watchdog clock setting
nand:
- Fix zynq nand command comparison
xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose
zynq:
- Kconfig alignments
- Fix nand cse configuration
zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 30 Apr 2020 14:06:54 +0000 (10:06 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb,
ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb.
- Add GICv3 support for ls1028a, ls2088a, ls1088a.
- Add lpuart support on ls1028aqds.
- Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based
platforms.
Simon Glass [Sun, 26 Apr 2020 15:13:01 +0000 (09:13 -0600)]
x86: Add documentation for the chain-load feature
Add a few notes about this feature, which is aimed for development.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:13:00 +0000 (09:13 -0600)]
x86: Use the existing stack when chain-loading
With chromebook_coral we normally run TPL->SPL->U-Boot. This is the
'bare metal' case.
When running from coreboot we put u-boot.bin in the RW_LEGACY portion
of the image, e.g. with:
cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \
-f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \
-c lzma -l 0x1110000 -e 0x1110000
In this case U-Boot is run from coreboot (actually Depthcharge, its
payload) so we cannot access CAR. Use the existing stack instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:12:59 +0000 (09:12 -0600)]
x86: Add a way to detect running from coreboot
If U-Boot is running from coreboot we need to skip low-level init. Add
an way to detect this and to set the gd flag.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:12:58 +0000 (09:12 -0600)]
x86: Move coreboot-table detection into common code
To support detecting booting from coreboot, move the code which locates
the coreboot tables into a common place. Adjust the algorithm slightly to
use a word comparison instead of string, since it is faster.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct the comments to 960KB]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:12:57 +0000 (09:12 -0600)]
board: Add a gd flag for chain loading
When U-Boot is run from another boot loader, much of the low-level init
needs to be skipped.
Add a flag for this and adjust ll_boot_init() to use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:12:56 +0000 (09:12 -0600)]
pci: Avoid auto-config when chain loading
When U-Boot is not the first-stage bootloader we don't want to
re-configure the PCI devices, since this has already been done. Add a
check to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:12:55 +0000 (09:12 -0600)]
x86: cpu: Skip init code when chain loading
When U-Boot is not the first-stage bootloader the interrupt and cache init
must be skipped, as well as init for various peripherals. Update the code
to add checks for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:12:54 +0000 (09:12 -0600)]
x86: apl: Skip init code when chain loading
When U-Boot is not the first-stage bootloader the FSP-S init must be
skipped. Update it to add a check.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:12:53 +0000 (09:12 -0600)]
x86: fsp: Allow skipping init code when chain loading
It is useful to be able to boot the same x86 image on a device with or
without a first-stage bootloader. For example, with chromebook_coral, it
is helpful for testing to be able to boot the same U-Boot (complete with
FSP) on bare metal and from coreboot. It allows checking of things like
CPU speed, comparing registers, ACPI tables and the like.
When U-Boot is not the first-stage bootloader much of this code is not
needed and can break booting. Add checks for this to the FSP code.
Rather than checking for the amount of available SDRAM, just use 1GB in
this situation, which should be safe. Using 2GB may run into a memory
hole on some SoCs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 26 Apr 2020 15:19:53 +0000 (09:19 -0600)]
acpi: Add an acpi command
It is useful to dump ACPI tables in U-Boot to see what has been generated.
Add a command to handle this.
To allow the command to find the tables, add a position into the global
data.
Support subcommands to list and dump the tables.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Sun, 26 Apr 2020 15:19:52 +0000 (09:19 -0600)]
acpi: Move the xsdt pointer to acpi_ctx
Put this in the context along with the other important pointers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Sun, 26 Apr 2020 15:19:51 +0000 (09:19 -0600)]
acpi: Put table-setup code in its own function
We always write three basic tables to ACPI at the start. Move this into
its own function, along with acpi_fill_header(), so we can write a test
for this code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Apr 2020 15:19:50 +0000 (09:19 -0600)]
acpi: Move acpi_add_table() to generic code
Move this code to a generic location so that we can test it with sandbox.
This requires adding a few new fields to acpi_ctx, so drop the local
variables used in the original code.
Also use mapmem to avoid pointer-to-address casts which don't work on
sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Sun, 26 Apr 2020 15:19:49 +0000 (09:19 -0600)]
acpi: Drop code for missing XSDT from acpi_write_rsdp()
We don't actually support tables without an XSDT so we can drop this dead
code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Sun, 26 Apr 2020 15:19:48 +0000 (09:19 -0600)]
x86: Allow devices to write ACPI tables
Call the new core function to permit devices to write their own ACPI
tables. These tables will appear after all other tables.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Sun, 26 Apr 2020 15:19:47 +0000 (09:19 -0600)]
acpi: Convert part of acpi_table to use acpi_ctx
The current code uses an address but a pointer would result in fewer
casts. Also it repeats the alignment code in a lot of places so this would
be better done in a helper function.
Update write_acpi_tables() to make use of the new acpi_ctx structure,
adding a few helpers to clean things up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Sun, 26 Apr 2020 15:19:46 +0000 (09:19 -0600)]
acpi: Add a method to write tables for a device
A device may want to write out ACPI tables to describe itself to Linux.
Add a method to permit this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Sun, 26 Apr 2020 15:19:45 +0000 (09:19 -0600)]
acpi: Add a binding for ACPI settings in the device tree
Devices need to report various identifiers in the ACPI tables. Rather than
hard-coding these in drivers it is typically better to put them in the
device tree.
Add a binding file to describe this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 5 Apr 2020 23:22:38 +0000 (17:22 -0600)]
x86: cbfs: Drop unwanted declaration
The intention here is add a forward declaration, not actually declare a
variable. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Heinrich Schuchardt [Wed, 29 Apr 2020 19:15:08 +0000 (21:15 +0200)]
efi_loader: fix 'efidebug bootorder'
* don't copy GUIDs for no reason
* shorten print format strings by using variable names
* don't use the run-time table to access exported functions
* check the result of malloc() (fixes Coverity CID 300331)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 29 Apr 2020 18:21:39 +0000 (20:21 +0200)]
efi_loader: efidebug, avoid illegal memory access
For EFI_PERSISTENT_MEMORY_TYPE the 'efidebug memmap' command produces an
illegal memory access.
* Add the missing descriptive string for EFI_PERSISTENT_MEMORY_TYPE.
* Replace the check for EFI_MAX_MEMORY_TYPE by the ARRAY_SIZE() macro.
Reported-by: Coverity (CID 300336)
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 29 Apr 2020 17:20:35 +0000 (19:20 +0200)]
efi_loader: fix 'efidebug boot dump'
* Do not recreate a variable name that we already have as u16 string.
* Check the return value of malloc()
* EFI_NOT_FOUND cannot occur for a variable name returned by
GetNextVariableName(). Remove a print statement.
* Don't copy a GUID for no reason.
* Don't use the run-time service table to call exported functions.
* Don't pass NULL to show_efi_boot_opt_data() (fixes Coverity CID 300338).
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 22 Apr 2020 15:53:34 +0000 (17:53 +0200)]
MAINTAINERS: assign test/py/tests/test_efi*/ to EFI PAYLOAD
Some UEFI related files are not assigned currently. Add them to the
EFI PAYLOAD area.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
AKASHI Takahiro [Tue, 21 Apr 2020 00:38:38 +0000 (09:38 +0900)]
efi_loader: remove CONFIG_EFI_SECURE_BOOT in efi_loader.h
The guard doesn't make any difference, so remove it.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 16 Apr 2020 18:31:56 +0000 (20:31 +0200)]
doc/efi: rework secure boot description
Ensure a uniform formatting.
Some rephrasing.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 19 Mar 2020 14:16:31 +0000 (15:16 +0100)]
efi_loader: identify EFI system partition
In subsequent patches UEFI variables shalled be stored on the EFI system
partition. Hence we need to identify the EFI system partition.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 19 Mar 2020 12:49:34 +0000 (13:49 +0100)]
part: detect EFI system partition
Up to now for MBR and GPT partitions the info field 'bootable' was set to 1
if either the partition was an EFI system partition or the bootable flag
was set.
Turn info field 'bootable' into a bit mask with separate bits for bootable
and EFI system partition.
This will allow us to identify the EFI system partition in the UEFI
sub-system.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Mon, 20 Apr 2020 10:44:56 +0000 (12:44 +0200)]
efi_loader: remove superfluous NULL check in bootefi.c
efi_free_pool() and efi_delete_handle() both check if their argument is
NULL. The caller should not duplicate this check.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Tue, 21 Apr 2020 16:44:39 +0000 (18:44 +0200)]
test/py: fix test_efi_secboot/conftest.py
If udisksctl is present
test/py/tests/test_efi_secboot/conftest.py
fails because the disk image is never mounted.
Normal users can only mount fuse file systems. Unfortunately fusefat is
still in an experimental state and seems not to work here correctly.
So as we have to be root or use the sudo command anyway delete all coding
referring to udisksctl.
--
We should not use mount point /mnt as this directory or one of its
sub-directories might already be in use as active mount points. Instead
create a new directory in the build root as mount point.
--
Remove debug print statements that have been commented out. print without
parentheses is anyway invalid in Python 3. And pytest anyway filters out
the output if there is no exception reported.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Wed, 29 Apr 2020 14:39:18 +0000 (10:39 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- rmobile gen2/gen3 DTS sync and defconfig consolidation