oweals/u-boot.git
5 years agoboard/BuR: invalidate ${dtbaddr} before cfgscr
Hannes Schmelzer [Thu, 16 May 2019 15:24:19 +0000 (17:24 +0200)]
board/BuR: invalidate ${dtbaddr} before cfgscr

The first memory location of ${dtbaddr} may be still valid after a warm
restart of the machine and 'fdt addr ${dtbaddr}' doesn't recognize that
the cfgscript didn't run properly and fallback mechanism with copying
the internal fdt ${fdtcontroladdr} to ${dtbaddr} doesn't catch this.

To get sure that we have proper failsafe behaviour we simply zero the
first memory location of ${dtbaddr} for getting sure that the fdt is
invalid if cfgscript didn't run.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
5 years agofs: fat: Fix possible double free of fatbuf
Andrew F. Davis [Thu, 16 May 2019 14:34:31 +0000 (09:34 -0500)]
fs: fat: Fix possible double free of fatbuf

fat_itr_root() allocates fatbuf so we free it on the exit path, if
the function fails we should not free it, check the return value
and skip freeing if the function fails.

Signed-off-by: Andrew F. Davis <afd@ti.com>
5 years agofs: fat: correct file name normalization
Heinrich Schuchardt [Sun, 12 May 2019 07:59:18 +0000 (09:59 +0200)]
fs: fat: correct file name normalization

File names may not contain control characters (< 0x20).
Simplify the coding.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoPrepare v2019.07-rc3 v2019.07-rc3
Tom Rini [Mon, 27 May 2019 18:29:39 +0000 (14:29 -0400)]
Prepare v2019.07-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoMerge branch 'master' of git://git.denx.de/u-boot-marvell
Tom Rini [Mon, 27 May 2019 15:15:39 +0000 (11:15 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-marvell

- defconfig updates to remove the DM-move build warnings for helios4 and
  controlcenterdc (Mario & Stefan)

5 years agoarm: mvebu: controlcenterdc: Update config
Mario Six [Mon, 20 May 2019 12:08:14 +0000 (14:08 +0200)]
arm: mvebu: controlcenterdc: Update config

Several drivers used by the ControlCenterDC board were converted to DM
upstream. But the board had not been using these drivers yet.

Update the board's config file to reflect these changes and use the DM
version of these drivers. No further device tree updates are necessary,
since the devices in question are already present in the device tree.

This especially fixes the three compile warnings about CONFIG_DM_MMC,
CONFIG_DM_USB, and CONFIG_AHCI for the ControlCenterDC board.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
5 years agoarm: mvebu: helios4: Enable CONFIG_BLK and CONFIG_DM_MMC
Stefan Roese [Mon, 20 May 2019 07:53:31 +0000 (09:53 +0200)]
arm: mvebu: helios4: Enable CONFIG_BLK and CONFIG_DM_MMC

This patch enables CONFIG_BLK and CONFIG_DM_MMC on helios4 to remove
these compile warnings:

===================== WARNING ======================
This board does not use CONFIG_DM_MMC. Please update
the board to use CONFIG_DM_MMC before the v2019.04 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dennis Gilmore <dgilmore@redhat.com>
5 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Mon, 27 May 2019 00:18:20 +0000 (20:18 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

- Gen3 PCIe driver + enablement on Salvator-X platforms.
- Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon.
- SDHI HS400 fixes ported from latest BSP and datasheet.

5 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Mon, 27 May 2019 00:15:46 +0000 (20:15 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- SoCFPGA PL310 cleanup + A10 fix, A10 DT cleanup, DW GPIO fix.

5 years agoconfigs: Resync with savedefconfig
Tom Rini [Sun, 26 May 2019 18:45:25 +0000 (14:45 -0400)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoconfigs: Migrate CONFIG_FMAN_ENET and some related options to Kconfig
Tom Rini [Sun, 12 May 2019 11:59:12 +0000 (07:59 -0400)]
configs: Migrate CONFIG_FMAN_ENET and some related options to Kconfig

Move the main symbol for Freescale Fman Ethernet controller option to
Kconfig.  Also migrate the CONFIG_SYS_QE_FMAN_FW_IN_xxx macros and
rename the SPIFLASH one to follow the same format as all of the others.
To do this fully we need to migrate CONFIG_QC, do so.

Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoMerge tag 'efi-2019-07-rc3-3' of git://git.denx.de/u-boot-efi
Tom Rini [Sat, 25 May 2019 15:34:40 +0000 (11:34 -0400)]
Merge tag 'efi-2019-07-rc3-3' of git://git.denx.de/u-boot-efi

Pull request for UEFI sub-system for v2019.07-rc3 (3)

Several bug fixes for the UEFI sub-system are provided.
The SetTime() boottime service is implemented.

5 years agoMerge tag 'mips-pull-2019-05-24' of git://git.denx.de/u-boot-mips
Tom Rini [Sat, 25 May 2019 15:34:31 +0000 (11:34 -0400)]
Merge tag 'mips-pull-2019-05-24' of git://git.denx.de/u-boot-mips

- mtmips: network stability fixes for gardena-smart-gateway
- mtmips: enable CONFIG_USE_PREBOOT and CONFIG_CMD_WDT

5 years agoefi_loader: variable: attributes may not be changed if a variable exists
AKASHI Takahiro [Fri, 24 May 2019 06:59:03 +0000 (15:59 +0900)]
efi_loader: variable: attributes may not be changed if a variable exists

If a variable already exists, efi_set_variable() should not change
the variable's attributes. This patch enforces it.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: variable: return error for APPEND_WRITE
AKASHI Takahiro [Fri, 24 May 2019 06:59:02 +0000 (15:59 +0900)]
efi_loader: variable: return error for APPEND_WRITE

The current efi_st_variable() doesn't support EFI_VARIABLE_APPEND_WRITE
attiribute for now, and so should return an error.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Fix typos is commit message.
Add TODO comment.

Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi: selftest: APPEND_WRITE is not supported
AKASHI Takahiro [Fri, 24 May 2019 06:59:01 +0000 (15:59 +0900)]
efi: selftest: APPEND_WRITE is not supported

The error here should be marked *todo*.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: DEL is an illegal file name character
Heinrich Schuchardt [Fri, 24 May 2019 05:19:18 +0000 (07:19 +0200)]
efi_loader: DEL is an illegal file name character

According to the FAT32 specification 0x7f (DEL) is not a legal character
for file names.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: comments for structs
Heinrich Schuchardt [Tue, 21 May 2019 15:51:35 +0000 (17:51 +0200)]
efi_loader: comments for structs

Change comments for struct efi_open_protocol_info_item and
struct efi_handler to Sphinx format.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: correct device path check
Heinrich Schuchardt [Mon, 20 May 2019 19:55:18 +0000 (19:55 +0000)]
efi_loader: correct device path check

Since commit 226cddbe32f0 ("efi_loader: check device path in
InstallMultipleProtocolInterfaces") iPXE fails to access the network.

LocateDevicePath() returns EFI_SUCCESS even if a shorter path is found as a
partial match. It returns the remaining path. So to be sure that we found a
complete match we need to check that the remaining path refers to an end
node.

Provide debug output if a device path has already been installed.

Fixes: 226cddbe32f0 ("efi_loader: check device path in
       InstallMultipleProtocolInterfaces")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: return values of GetTime()
Heinrich Schuchardt [Sun, 19 May 2019 19:41:28 +0000 (21:41 +0200)]
efi_loader: return values of GetTime()

According to the UEFI spec 2.8 the GetTime() runtime service should return
EFI_UNSUPPORTED if the real time clock is not available.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agoefi_loader: implement SetTime
Heinrich Schuchardt [Sun, 19 May 2019 18:07:39 +0000 (20:07 +0200)]
efi_loader: implement SetTime

Implement the SetTime() runtime service.

Extend the real time clock selftest to check setting the clock.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
5 years agomips: mt76xx: gardena-smart-gateway: Enable CONFIG_USE_PREBOOT
Stefan Roese [Thu, 23 May 2019 05:55:55 +0000 (07:55 +0200)]
mips: mt76xx: gardena-smart-gateway: Enable CONFIG_USE_PREBOOT

Enable CONFIG_USE_PREBOOT on for the gardena mt7688 platforms, so that
this feature can be used here.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agomips: mt76xx: Remove cache workaround and select SYS_MALLOC_CLEAR_ON_INIT
Stefan Roese [Thu, 23 May 2019 05:55:54 +0000 (07:55 +0200)]
mips: mt76xx: Remove cache workaround and select SYS_MALLOC_CLEAR_ON_INIT

With commit 06985289d452 ("watchdog: Implement generic watchdog_reset()
version") the init sequence has changed in arch_misc_init(), resulting
in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena).
When this happens, the first (or sometimes later ones as well) TFTP
command hangs and does not complete correctly. This leads to the
assumption that the d-cache is not in a clean state once the ethernet
driver is called (d-cache is used here for the buffers). The old work-
around with the cache flush somehow does not work any more now with
the new code change.

To fix this issue, this patch now removes the old workaround and selects
CONFIG_SYS_MALLOC_CLEAR_ON_INIT for ARCH_MTMIPS. With this option the
complete malloc area is initialized with zeros (cache lines are touched).
Testing has shown that this also fixes the issue on the MT7688 boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agomips: mt7688: gardena-smart-gateway-mt7688: Enable CMD_WDT
Stefan Roese [Wed, 8 May 2019 12:47:04 +0000 (14:47 +0200)]
mips: mt7688: gardena-smart-gateway-mt7688: Enable CMD_WDT

This patch enables the "wdt" command, which is quite useful for watchdog
testing.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
5 years agoArm: dts: socfpga: Remove invalid property from chose node
Tien Fong Chee [Fri, 24 May 2019 12:14:17 +0000 (20:14 +0800)]
Arm: dts: socfpga: Remove invalid property from chose node

Finding bitstream from cff-file is no longer valid after bitstream is built
into FIT image and loaded by generic firmware loader. Remove cff-file
as this is legacy implementation from A10 downstream.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
5 years agoMerge tag 'u-boot-stm32-20190523' of https://github.com/pchotard/u-boot
Tom Rini [Fri, 24 May 2019 12:13:27 +0000 (08:13 -0400)]
Merge tag 'u-boot-stm32-20190523' of https://github.com/pchotard/u-boot

- Add various STM32MP1 fixes for serial, env, clk, board, i2c ...

- Add STM32MP1 DDR driver update:
These update introduce the DDR interactive mode described in:
https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode

This mode is used by the CubeMX: DDR tuning tool.
https://wiki.st.com/stm32mpu/index.php/STM32CubeMX

The DDR interactive mode is NOT activated by default because
it increase the SPL size and slow down the boot time
(200ms wait added).

5 years agoMerge git://git.denx.de/u-boot-mpc85xx
Tom Rini [Fri, 24 May 2019 12:13:00 +0000 (08:13 -0400)]
Merge git://git.denx.de/u-boot-mpc85xx

- Enable DM for SATA, SDHC, USB in T2080QDS

5 years agoMerge branch '2019-05-24-master-imports'
Tom Rini [Fri, 24 May 2019 12:12:22 +0000 (08:12 -0400)]
Merge branch '2019-05-24-master-imports'

- Import Angelo's series to add basic DT support to m68k

5 years agom68k: add dspi chip-select support
Angelo Dureghello [Wed, 13 Mar 2019 20:46:53 +0000 (21:46 +0100)]
m68k: add dspi chip-select support

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Changes for v5:
- new patch

5 years agom68k: move dspi bus control functions into cf_spi.c driver
Angelo Dureghello [Wed, 13 Mar 2019 20:46:52 +0000 (21:46 +0100)]
m68k: move dspi bus control functions into cf_spi.c driver

This patches move dspi bus-related operations into more
proper location, to avoid the driver to declares them as externs.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
5 years agom68k: add OF control support to m68k
Angelo Dureghello [Wed, 13 Mar 2019 20:46:51 +0000 (21:46 +0100)]
m68k: add OF control support to m68k

Add SUPPORT_OF_CONTROL at this stage, to avoid to break build
bisectability.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
5 years agoconfigs: remove CONFIG_SYS_DSPI_XX references
Angelo Dureghello [Wed, 13 Mar 2019 20:46:50 +0000 (21:46 +0100)]
configs: remove CONFIG_SYS_DSPI_XX references

This patch removes CONFIG_SYS_DSPI_XX options from
include/configs "m68k" .h board files, since CTAR
registers are now set with default values in the cf_spi
driver initialization, and configurable by devicetree.

Note, these options cannot be totally removed from the
whitelist, since still used from boards using fsl_dspi.c
(mostly arm-based boards).

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
5 years agodrivers: serial: mcfuart: add DT support
Angelo Dureghello [Wed, 13 Mar 2019 20:46:49 +0000 (21:46 +0100)]
drivers: serial: mcfuart: add DT support

This patch adds devicetree support to the mcfuart.c driver
and removes non DM code.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
5 years agoconfigs: add DM_SPI config option
Angelo Dureghello [Wed, 13 Mar 2019 20:46:48 +0000 (21:46 +0100)]
configs: add DM_SPI config option

This patch adds CONFIG_DM_SPI for all m68k boards using
the cf_spi.c driver (DSPI module).

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
5 years agodrivers: spi: cf_spi: convert to driver model
Angelo Dureghello [Wed, 13 Mar 2019 20:46:47 +0000 (21:46 +0100)]
drivers: spi: cf_spi: convert to driver model

Converting to driver model and removes non-dm code.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
5 years agodrivers: spi: cf_spi: add Kconfig option
Angelo Dureghello [Wed, 13 Mar 2019 20:46:46 +0000 (21:46 +0100)]
drivers: spi: cf_spi: add Kconfig option

This patch adds cf_spi DM Kconfig option.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
5 years agoconfigs: enable use of DT for all m68k boards
Angelo Dureghello [Wed, 13 Mar 2019 20:46:45 +0000 (21:46 +0100)]
configs: enable use of DT for all m68k boards

Enable DT usage for all m68k boards. To provide a
working single binary, the dts has been kept as embedded.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
5 years agom68k: enabling long jumps on mcf54x5 SoCs
Angelo Dureghello [Wed, 13 Mar 2019 20:46:44 +0000 (21:46 +0100)]
m68k: enabling long jumps on mcf54x5 SoCs

Growing of binary size asks for long assembly jumps.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
5 years agom68k: add initial dts files for all m68k boards
Angelo Dureghello [Wed, 13 Mar 2019 20:46:43 +0000 (21:46 +0100)]
m68k: add initial dts files for all m68k boards

This patch adds basic dts files for all the m68k boards.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
[trini: Add CONFIG_TARGET_M5329EVB dtbs and update M5329EVB defconfigs]
Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agom68k: architecture changes to support fdt
Angelo Dureghello [Wed, 13 Mar 2019 20:46:42 +0000 (21:46 +0100)]
m68k: architecture changes to support fdt

This patch adds fdt support to the m68k architecture.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
5 years agom68k: add basic set of devicetrees
Angelo Dureghello [Wed, 13 Mar 2019 20:46:41 +0000 (21:46 +0100)]
m68k: add basic set of devicetrees

This patch adds a basic group of devicetrees, one for each
cpu family, including actually just uart and dspi devices,
since these are the drivers supporting devicetree (support
added in this patch-set).

Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
5 years agoARM: socfpga: Clear PL310 early in SPL
Marek Vasut [Sat, 9 Mar 2019 21:25:57 +0000 (22:25 +0100)]
ARM: socfpga: Clear PL310 early in SPL

On SoCFPGA A10 systems, it can rarely happen that a reboot from Linux
will result in stale data in PL310 L2 cache controller. Even if the L2
cache controller is disabled via the CTRL register CTRL_EN bit, those
data can interfere with operation of devices using DMA, like e.g. the
DWMMC controller. This can in turn cause e.g. SPL to fail reading data
from SD/MMC.

The obvious solution here would be to fully reset the L2 cache controller
via the reset manager MPUMODRST L2 bit, however this causes bus hang even
if executed entirely from L1 I-cache to avoid generating any bus traffic
through the L2 cache controller.

This patch thus configures and enables the L2 cache controller very early
in the SPL boot process, clears the L2 cache and disables the L2 cache
controller again.

The reason for doing it in SPL is because we need to avoid accessing any
of the potentially stale data in the L2 cache, and we are certain any of
the stale data will be below the OCRAM address range. To further reduce
bus traffic during the L2 cache invalidation, we enable L1 I-cache and
run the invalidation code entirely out of the L1 I-cache.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
5 years agoARM: socfpga: Pull PL310 clearing into common code
Marek Vasut [Thu, 21 Mar 2019 22:05:38 +0000 (23:05 +0100)]
ARM: socfpga: Pull PL310 clearing into common code

Pull the PL310 clearing code into common code, so it can be reused
by Arria10.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
5 years agogpio: dwapb_gpio: fix broken dev->node
Simon Goldschmidt [Tue, 21 May 2019 20:03:12 +0000 (22:03 +0200)]
gpio: dwapb_gpio: fix broken dev->node

commit 1b898ffc040b ("gpio: dwapb_gpio: convert to livetree") introduced
a bug in that dev->node of the gpio chip was accidentally set to the
of_node of its bank subnode.

What it meant to do was assign subdev->node, not dev->node.

While this doesn't affect too many use cases, iterating over the gpio
chip's properties doesn't work any more after that, so fix this.

Fixes: commit 1b898ffc040b ("gpio: dwapb_gpio: convert to livetree")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
5 years agoconfigs: enable sata, eSDHC, USB device module in T2080QDS
Peng Ma [Wed, 27 Mar 2019 09:23:38 +0000 (09:23 +0000)]
configs: enable sata, eSDHC, USB device module in T2080QDS

Enable eSDHC, SATA and USB DM for T2080QDS in uboot

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agopowerpc: mpc85xx: delete FSL_SATA for T2080QDS board.
Peng Ma [Wed, 27 Mar 2019 09:23:33 +0000 (09:23 +0000)]
powerpc: mpc85xx: delete FSL_SATA for T2080QDS board.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoarch: powerpc: add sata node for t2080 dts
Peng Ma [Wed, 27 Mar 2019 09:23:28 +0000 (09:23 +0000)]
arch: powerpc: add sata node for t2080 dts

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoata: fsl_ahci: Add sata DM support for Freescale powerpc socs
Peng Ma [Wed, 27 Mar 2019 09:23:23 +0000 (09:23 +0000)]
ata: fsl_ahci: Add sata DM support for Freescale powerpc socs

This patch is to support Freescale sata driver with dts initialized.
Also resolved the following problems.

===================== WARNING ======================
This board does not use CONFIG_DM_SCSI. Please update
the storage controller to use CONFIG_DM_SCSI before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agousb: ehci: adopt 32 bit address for CONFIG_PPC
Yinbo Zhu [Thu, 11 Apr 2019 11:02:05 +0000 (11:02 +0000)]
usb: ehci: adopt 32 bit address for CONFIG_PPC

adopt 32 bit addr in fsl_esdhc for CONFIG_PPC.
So  adopt 32 bit address for CONFIG_PPC.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoarch: powerpc: add usb node in t2080 dts
Yinbo Zhu [Thu, 11 Apr 2019 11:02:01 +0000 (11:02 +0000)]
arch: powerpc: add usb node in t2080 dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoconfigs: T2080QDS: enable device tree support for pcieboot & secure boot
Yinbo Zhu [Thu, 11 Apr 2019 11:01:54 +0000 (11:01 +0000)]
configs: T2080QDS: enable device tree support for pcieboot & secure boot

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agostm32mp1: ram: add tuning in DDR interactive mode
Patrick Delaunay [Wed, 10 Apr 2019 12:09:29 +0000 (14:09 +0200)]
stm32mp1: ram: add tuning in DDR interactive mode

Add command tuning for DDR interactive mode, used during
board bring-up or with CubeMX DDR tools to execute software
tuning for the DDR configuration:
- software read DQS Gating (replace the built-in one)
- Bit de-skew
- Eye Training or DQS training

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: ram: add tests in DDR interactive mode
Patrick Delaunay [Wed, 10 Apr 2019 12:09:28 +0000 (14:09 +0200)]
stm32mp1: ram: add tests in DDR interactive mode

Add command tests for DDR interactive mode, used during
board bring-up or with CubeMX DDR tools to verify the
DDR configuration.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: ram: add interactive mode for DDR configuration
Patrick Delaunay [Wed, 10 Apr 2019 12:09:27 +0000 (14:09 +0200)]
stm32mp1: ram: add interactive mode for DDR configuration

This debug mode is used by CubeMX DDR tuning tools
or manualy for tests during board bring-up.
It is simple console used to change DDR parameters and check
initialization.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: ram: add support for LPDDR2/LPDDR3
Patrick Delaunay [Wed, 10 Apr 2019 12:09:26 +0000 (14:09 +0200)]
stm32mp1: ram: add support for LPDDR2/LPDDR3

Manage power supply configuration for board using stpmic1
with LPDDR2 or with LPDDR3:
+ VDD_DDR1 = 1.8V with BUCK3 (bypass if possible)
+ VDD_DDR2 = 1.2V with BUCK2

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: ram: update parameter array initialization
Patrick Delaunay [Wed, 10 Apr 2019 12:09:25 +0000 (14:09 +0200)]
stm32mp1: ram: update parameter array initialization

Force alignment of the size of parameters array with
the expected value in the binding, that allows compilation
error when the array size change.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agoARM: dts: stm32mp1: DDR config v1.44
Patrick Delaunay [Wed, 10 Apr 2019 12:09:24 +0000 (14:09 +0200)]
ARM: dts: stm32mp1: DDR config v1.44

Update DDR configuration with the latest update:

- PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte
                        lane 2/3 in 16bit
- fix LPDDR2/3 timing_calc to step RL/WL in relaxed
  timings mode
- remove  LPDDR3 RL3 (optional) support vs  MR0[7]
  because MR0[7] can't be read instead  always apply
  worse RL/WL for LPDDR3 when freq < 166MHz)
- change  MR3 to 48ohm drive  for LPDDR2/3
- change default ZPROG[7:4] = 0x1 for LPDDR2/3 ,
  '0' is not allowed even when ODT not used
- use DQSTRN for LPDDR2/3 (it was not set in PIR)
- LPDDR3: set dqsge/dwsgx gate extension to 2,2
  like LPDDR2
-DDRCTRL.dfitmg0:
  + for LPDDR3 tphy_wrlat = WL (as LPDDR2)
  + improvement for relaxed mode vs  RL/Wl at corner case.
    For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3
    and correction to MR2 accordingly
- DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40,
  for LTDC.
- DDR_PCFGWQOS0_0: change vpr level from
  11 to 12 in order to include the CPU on
  the variable priority queue.
- DDR_SCHED: fix to consider 13 levels  (13 levels - 1 = 0xC)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: ram: change ddr speed to kHz
Patrick Delaunay [Wed, 10 Apr 2019 12:09:23 +0000 (14:09 +0200)]
stm32mp1: ram: change ddr speed to kHz

Allow fractional support in DDR tools.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: ram: increase the delay after reset to 128 cycles
Patrick Delaunay [Wed, 10 Apr 2019 12:09:22 +0000 (14:09 +0200)]
stm32mp1: ram: increase the delay after reset to 128 cycles

Component Notification DDR controller errata (3.00a):9001313030
Synchronization Time Waited After De-assertion of presetn is
128 pclk Cycles.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: ram: update mask for operating mode
Patrick Delaunay [Wed, 10 Apr 2019 12:09:21 +0000 (14:09 +0200)]
stm32mp1: ram: update mask for operating mode

Regression introduced by rebase, when loop
was replaced by readl_poll_timeout() function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agoserial: stm32: remove watchog reset in debug putc
Patrick Delaunay [Thu, 18 Apr 2019 15:32:51 +0000 (17:32 +0200)]
serial: stm32: remove watchog reset in debug putc

For STM32MP, the watchdog is based on DM and the function watchod_reset
call the function uclass_get_device(UCLASS_WDT) to found the driver
associated IWDG2.

As this reset is not mandatory in debug putc (the  uart fifo will be
empty after some us), we can simplify the code by removing this call.

And this patch avoid issue when putc is called before initialization
of DM core, before the parsing of the device tree parsing and each
node bound to driver; that also avoid memory leak.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agoserial: stm32: remove unnecessary trace
Patrick Delaunay [Thu, 18 Apr 2019 15:32:50 +0000 (17:32 +0200)]
serial: stm32: remove unnecessary trace

Remove the trace indicating the end of the DEBUG initialization

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agoenv: solve compilation error in SPL
Patrick Delaunay [Thu, 18 Apr 2019 15:32:49 +0000 (17:32 +0200)]
env: solve compilation error in SPL

Solve compilation issue when cli_simple.o is used in SPL
and CONFIG_SPL_ENV_SUPPORT is not defined.

env/built-in.o:(.data.env_htab+0xc): undefined reference to `env_flags_validate'
u-boot/scripts/Makefile.spl:384: recipe for target 'spl/u-boot-spl' failed
make[2]: *** [spl/u-boot-spl] Error 1
u-boot/Makefile:1649: recipe for target 'spl/u-boot-spl' failed
make[1]: *** [spl/u-boot-spl] Error 2

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agoclk: stm32mp1: add set_rate for DDRPHYC clock
Patrick Delaunay [Thu, 18 Apr 2019 15:32:48 +0000 (17:32 +0200)]
clk: stm32mp1: add set_rate for DDRPHYC clock

Add the DDRPHYC support for clk_set_rate, used in DDR interactive mode

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: add bootstage support
Patrick Delaunay [Thu, 18 Apr 2019 15:32:47 +0000 (17:32 +0200)]
stm32mp1: add bootstage support

Add the needed configurations for bootstage and
activate bootstage command.

BOOTSTAGE_REPORT is not activated by default.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agoarmv7: timer: init timer with bootstage
Patrick Delaunay [Thu, 18 Apr 2019 15:32:46 +0000 (17:32 +0200)]
armv7: timer: init timer with bootstage

In initf_bootstage() we call bootstage_mark_name() which ends up calling
timer_get_us() before timer_init(); that cause crash for stm32mp1.

This patch solve the issue without changing the initialization sequence.
See also commit 97d20f69f53e ("Enable CONFIG_TIMER_EARLY with bootstage")
for other solution when DM is activated for TIMER.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: add bootcount support
Patrick Delaunay [Thu, 18 Apr 2019 15:32:45 +0000 (17:32 +0200)]
stm32mp1: add bootcount support

Activate bootcount and use TAMP register to store the count value.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agomkimage: change stm32image header to manage binary information
Patrick Delaunay [Thu, 18 Apr 2019 15:32:44 +0000 (17:32 +0200)]
mkimage: change stm32image header to manage binary information

To get more information from STM32 Header about the generated binary,
we will add a new byte with the following field:
replace padding byte 255 with 0x00 for "U-Boot"

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agoi2c: stm32f7: improve loopback in timing algorithm
Nicolas Le Bayon [Thu, 18 Apr 2019 15:32:43 +0000 (17:32 +0200)]
i2c: stm32f7: improve loopback in timing algorithm

This avoids useless loops inside the I2C timing algorithm.
Actually, we support only one possible solution per prescaler value.
So after finding a solution with a prescaler, the algorithm can
switch directly to the next prescaler value.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agoi2c: stm32f7: Fix SDADEL minimum formula
Nicolas Le Bayon [Thu, 18 Apr 2019 15:32:42 +0000 (17:32 +0200)]
i2c: stm32f7: Fix SDADEL minimum formula

It conforms with Reference Manual I2C timing section.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: update RCC binding after kernel realignment
Patrick Delaunay [Thu, 18 Apr 2019 15:32:41 +0000 (17:32 +0200)]
stm32mp1: update RCC binding after kernel realignment

RCC is no more a mfd and add a complete example
and alignment with latest TF-A binding

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: psci: add synchronization with ROM code
Patrick Delaunay [Thu, 18 Apr 2019 15:32:40 +0000 (17:32 +0200)]
stm32mp1: psci: add synchronization with ROM code

Use SGI0 interruption  and TAMP_BACKUP_MAGIC_NUMBER
to synchronize the core1 boot sequence requested by
core0 in psci_cpu_on():
- a initial interruption is needed in ROM code after
  RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off)
- the ROM code set to 0 the 2 registers
  + TAMP_BACKUP_BRANCH_ADDRESS
  + TAMP_BACKUP_MAGIC_NUMBER
  when magic is not egual to
  BOOT_API_A7_CORE0_MAGIC_NUMBER

This patch solve issue for cpu1 restart in kernel.
echo 0 > /sys/devices/system/cpu/cpu1/online
echo 1 > /sys/devices/system/cpu/cpu1/online

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: cosmetic: bsec: reorder include files
Patrick Delaunay [Thu, 18 Apr 2019 15:32:39 +0000 (17:32 +0200)]
stm32mp1: cosmetic: bsec: reorder include files

Reorder the include files in alphabetic order.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: migrate PREBOOT to Kconfig
Patrick Delaunay [Thu, 18 Apr 2019 15:32:38 +0000 (17:32 +0200)]
stm32mp1: migrate PREBOOT to Kconfig

Use Kconfig to activate CONFIG_PREBOOT (empty by default).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: Move ENV_SIZE and ENV_OFFSET to Kconfig
Patrick Delaunay [Thu, 18 Apr 2019 15:32:37 +0000 (17:32 +0200)]
stm32mp1: Move ENV_SIZE and ENV_OFFSET to Kconfig

Add arch stm32mp for ENV migration step and drop more
items from include/configs/xxx.h.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostm32mp1: Move config SYS_MALLOC_LEN to Kconfig
Patrick Delaunay [Thu, 18 Apr 2019 15:32:36 +0000 (17:32 +0200)]
stm32mp1: Move config SYS_MALLOC_LEN to Kconfig

This patch moves the the config SYS_MALLOC_LEN to
Kconfig as it is already done for zynq arch in
commit 01aa5b8f0503 ("Kconfig: Move config
SYS_MALLOC_LEN to Kconfig for zynq")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agodriver: mmc: adopt 32 bit addr in fsl_esdhc for CONFIG_PPC
Yinbo Zhu [Thu, 11 Apr 2019 11:01:50 +0000 (11:01 +0000)]
driver: mmc: adopt 32 bit addr in fsl_esdhc for CONFIG_PPC

PowerPC supports 32 bit address.
So adopt 32 bit addr in fsl_esdhc for CONFIG_PPC.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agodriver: mmc: set sdhc clock in fsl_esdhc for CONFIG_PPC
Yinbo Zhu [Thu, 11 Apr 2019 11:01:46 +0000 (11:01 +0000)]
driver: mmc: set sdhc clock in fsl_esdhc for CONFIG_PPC

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoarch: powerpc: add eSDHC node to t2080qds dts
Yinbo Zhu [Thu, 11 Apr 2019 11:01:42 +0000 (11:01 +0000)]
arch: powerpc: add eSDHC node to t2080qds dts

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoMerge tag 'dm-pull-22may19' of git://git.denx.de/u-boot-dm
Tom Rini [Wed, 22 May 2019 16:58:58 +0000 (12:58 -0400)]
Merge tag 'dm-pull-22may19' of git://git.denx.de/u-boot-dm

Various DM fixes
Addition of ofnode_get_addr_size_index()

5 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Wed, 22 May 2019 12:32:24 +0000 (08:32 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq

Changes from rc2 tag
  - Support PCIe Gen4 driver of the Mobiveil IP
  - NXP LS1028A SoC and platform support
  - Few SPI related config updates
  - Distinguish the ecc val by chassis version and move the ecc addr to dts
  - sp805 watchdog support

5 years agoarmv8: lx2160: Drop useless CONFIG_CMDLINE_EDITING from config.h
Andy Shevchenko [Mon, 13 May 2019 14:04:51 +0000 (17:04 +0300)]
armv8: lx2160: Drop useless CONFIG_CMDLINE_EDITING from config.h

commit 58c3e62040be ("armv8: lx2160ardb : Add support for LX2160ARDB
platform") brought a new boards support with redundancy in the config.h.

One of them is CONFIG_CMDLINE_EDITING which is removed by this change.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Peng Ma <peng.ma@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoconfig: enable SP805 watchdog support for LS1028A
Qiang Zhao [Tue, 7 May 2019 03:16:18 +0000 (03:16 +0000)]
config: enable SP805 watchdog support for LS1028A

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoarm: dts: fsl-ls1028a: add sp805 watchdog node
Qiang Zhao [Tue, 7 May 2019 03:16:13 +0000 (03:16 +0000)]
arm: dts: fsl-ls1028a: add sp805 watchdog node

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agodriver: watchdog: add sp805 watchdog support
Qiang Zhao [Tue, 7 May 2019 03:16:09 +0000 (03:16 +0000)]
driver: watchdog: add sp805 watchdog support

sp805 is watchdog on some NXP layerscape SoCs, adding
it's driver. Configs CONFIG_WDT_SP805, CONFIG_WDT, CONFIG_CMD_WDT
needs to be enabled to use it.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoconfigs: Unset CONFIG_SPI_BAR for all LS2080A/LS2081A defconfigs
Rajat Srivastava [Wed, 24 Apr 2019 12:45:12 +0000 (18:15 +0530)]
configs: Unset CONFIG_SPI_BAR for all LS2080A/LS2081A defconfigs

Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoconfigs: Unset CONFIG_SPI_BAR for all LS1046A defconfigs
Rajat Srivastava [Wed, 24 Apr 2019 12:45:11 +0000 (18:15 +0530)]
configs: Unset CONFIG_SPI_BAR for all LS1046A defconfigs

Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoconfigs: Unset CONFIG_SPI_BAR for all LS1088A defconfigs
Ashish Kumar [Wed, 24 Apr 2019 12:45:10 +0000 (18:15 +0530)]
configs: Unset CONFIG_SPI_BAR for all LS1088A defconfigs

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoarmv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE.
Udit Agarwal [Tue, 23 Apr 2019 06:06:04 +0000 (06:06 +0000)]
armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE.

ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on
CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE
is enabled

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoarmv8: Secure Boot: Modify boot_a_script definition
Vinitha V Pillai [Tue, 23 Apr 2019 05:52:17 +0000 (05:52 +0000)]
armv8: Secure Boot: Modify boot_a_script definition

esbc_validate command will not be executed if “load” command for its
header fails and will further execute the source command for bootscript,
without its validation and boot process continues.

To halt the  boot process in case secure boot header is not loaded
successfully, esbc_validate command is invoked separately after “load”
command. The secure boot validation of the bootscript header will fail
(if header is not loaded) and halts the boot process, which prevent source
command from execution.

Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoboard: fsl: lx2160ardb: invert AQR107 pins polarity
Florin Chiculita [Mon, 22 Apr 2019 08:57:47 +0000 (11:57 +0300)]
board: fsl: lx2160ardb: invert AQR107 pins polarity

AQR107 PHYs interrupt pins are active-low, while the GIC expects a
level-high signal.

Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoscsi: ceva: Clean up the driver code
Peng Ma [Wed, 17 Apr 2019 10:10:50 +0000 (10:10 +0000)]
scsi: ceva: Clean up the driver code

Distinguish the ecc val by chassis version and move the ecc addr to dts.
Add ls1028a soc support.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoARM: dts: Freescale: Add ecc addr for sata node
Peng Ma [Wed, 17 Apr 2019 10:10:49 +0000 (10:10 +0000)]
ARM: dts: Freescale: Add ecc addr for sata node

Move the ecc addr from driver to dts.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoconfigs: Enable CONFIG_SPI_FLASH for ls1088ardb_defconfig
Chuanhua Han [Wed, 17 Apr 2019 08:17:19 +0000 (16:17 +0800)]
configs: Enable CONFIG_SPI_FLASH for ls1088ardb_defconfig

Enables CONFIG_SPI_FLASH

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoarmv8: ls1028aqds: Add support of LS1028AQDS
Yuantian Tang [Wed, 10 Apr 2019 08:43:35 +0000 (16:43 +0800)]
armv8: ls1028aqds: Add support of LS1028AQDS

LS1028AQDS Development System is a high-performance
computing, evaluation, and development platform that supports
LS1028A QorIQ Architecture processor.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang yuantian <andy.tang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoarmv8: ls1028ardb: Add support for LS1028ARDB
Yuantian Tang [Wed, 10 Apr 2019 08:43:34 +0000 (16:43 +0800)]
armv8: ls1028ardb: Add support for LS1028ARDB

LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoarmv8: ls1028a: Add NXP LS1028A SoC support
Yuantian Tang [Wed, 10 Apr 2019 08:43:33 +0000 (16:43 +0800)]
armv8: ls1028a: Add NXP LS1028A SoC support

Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
 ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoarmv8: lx2160a: enable PCIe support
Hou Zhiqiang [Mon, 8 Apr 2019 10:16:03 +0000 (10:16 +0000)]
armv8: lx2160a: enable PCIe support

Enable the PCIe Gen4 controller driver and e1000 for LX2160ARDB
and LX2160AQDS boards.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agoarmv8: lx2160a: add PCIe controller DT nodes
Hou Zhiqiang [Mon, 8 Apr 2019 10:15:58 +0000 (10:15 +0000)]
armv8: lx2160a: add PCIe controller DT nodes

The LX2160A integrated 6 PCIe Gen4 controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
5 years agopci: ls_pcie_g4: add device tree fixups for PCI Stream IDs
Hou Zhiqiang [Mon, 8 Apr 2019 10:15:54 +0000 (10:15 +0000)]
pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs

Add the infrastructure for Layerscape SoCs PCIe Gen4 controller
to update device tree nodes to convey SMMU stream IDs in the
device tree.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>