net: zynq_gem: Remove check for Versal
authorSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Mon, 1 Jul 2019 06:49:25 +0000 (12:19 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 8 Oct 2019 07:41:27 +0000 (09:41 +0200)
This patch removes check for Versal platform
in gem driver as it now supports clock setting
through clock framework.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/net/zynq_gem.c

index a35ecab79ee9a70546fa088276ab02912ab127be..a7a6ce987f074c2c02659c0b29deffe4e9c598a5 100644 (file)
@@ -463,7 +463,6 @@ static int zynq_gem_init(struct udevice *dev)
                break;
        }
 
-#if !defined(CONFIG_ARCH_VERSAL)
        ret = clk_set_rate(&priv->clk, clk_rate);
        if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
                dev_err(dev, "failed to set tx clock rate\n");
@@ -475,9 +474,6 @@ static int zynq_gem_init(struct udevice *dev)
                dev_err(dev, "failed to enable tx clock\n");
                return ret;
        }
-#else
-       debug("requested clk_rate %ld\n", clk_rate);
-#endif
 
        setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
                                        ZYNQ_GEM_NWCTRL_TXEN_MASK);