Add support for GL.iNet GL-AR300 (AR9344 based)

diff --git a/Makefile b/Makefile
index 388c6396a5a63133a1cf3d1fdea7d045f49c0bef..f5edb2bcabb37c209fa10e276560bffcd7c4b3b5 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -268,6 +268,7 @@ dragino_v2_ms14:
        @$(call build,192,1,DEVICE_VENDOR=dragino)
 
 engenius_ens202ext \
+gl-inet_gl-ar300 \
 p2w_cpe505n \
 p2w_r602n \
 yuncore_ap90q \

diff --git a/README.md b/README.md
index 5ecbe9ceff121956466e13a693b3eccc105ce9ee..83237b8bbdba0313594443cac3eda94f128b7000 100644 (file)
--- a/README.md
+++ b/README.md
@@ -98,6 +98,7 @@ Currently supported devices:
   - TP-Link TL-WR1041N v2
 
 - **Atheros AR9344**:
+  - GL.iNet GL-AR300
   - TP-Link TL-WDR3500 v1
   - TP-Link TL-WDR3600 v1
   - TP-Link TL-WDR43x0 v1
@@ -142,6 +143,7 @@ More information about supported devices:
 | [EnGenius ENS202EXT](https://wiki.openwrt.org/toh/engenius/engenius_ens202ext_1.0.0) | AR9341 | 16 MiB | 64 MiB DDR1 | 256 KiB | R/W |
 | [GL.iNet 64xxA](http://wiki.openwrt.org/toh/gl-inet/gl-inet) | AR9331 | 8/16 MiB | 64 MiB DDR1 | 64 KiB | RO |
 | GL.iNet GL-AR150 | AR9331 | 16 MiB | 64 MiB DDR2 | 256 KiB | R/W |
+| GL.iNet GL-AR300 | AR9344 | 16 MiB | 128 MiB DDR2 | 256 KiB | R/W |
 | GL.iNet GL-USB150 | AR9331 | 16 MiB | 64 MiB DDR2 | 256 KiB | R/W |
 | GS-Oolite/Elink EL-M150 module | AR9331 | 4/8/16 MiB | 64 MiB DDR2 | 64 KiB, LZMA | RO |
 | P&W CPE505N | QCA9531 | 16 MiB | 64 MiB DDR2 | 256 KiB | R/W |

diff --git a/u-boot/Makefile b/u-boot/Makefile
index db008045c0b8f8af7b43d07f4b75f817c81f1f2c..e27ec7c28c03814c86dbc77b365d6dadb7655661 100644 (file)
--- a/u-boot/Makefile
+++ b/u-boot/Makefile
@@ -474,6 +474,13 @@ gl-inet_gl-ar150: ar933x_common
        @$(call define_add,CONFIG_FOR_GL_AR150,1)
        @$(MKCONFIG) -a ap121 mips mips ap121 ar7240 ar7240
 
+gl-inet_gl-ar300: ar934x_common
+       @$(call config_init,GL.iNet GL-AR300,gl-ar300,16,16,1,QCA_AR9344_SOC)
+       @$(call define_add,CONFIG_FOR_GL_AR300,1)
+       @$(call define_add,CFG_ATHRS27_PHY,1)
+       @$(call define_add,CFG_AG7240_NMACS,2)
+       @$(MKCONFIG) -a db12x mips mips db12x ar7240 ar7240
+
 gl-inet_gl-usb150: ar933x_common
        @$(call config_init,GL.iNet GL-USB150,gl-usb150,16,11,,QCA_AR933X_SOC)
        @$(call define_add,CONFIG_FOR_GL_USB150,1)

diff --git a/u-boot/include/configs/db12x.h b/u-boot/include/configs/db12x.h
index d8f423acf73bfc306ba34b9e62929620e3e66064..15bf6a2c6cc09a52a4d05b8d497a6268704dc117 100644 (file)
--- a/u-boot/include/configs/db12x.h
+++ b/u-boot/include/configs/db12x.h
@@ -29,6 +29,13 @@
        #define CONFIG_QCA_GPIO_MASK_IN         GPIO1
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 
+#elif defined(CONFIG_FOR_GL_AR300)
+
+       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13 | GPIO14
+       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
+       #define CONFIG_QCA_GPIO_MASK_IN         GPIO16
+       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
 #elif defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
       defined(CONFIG_FOR_TPLINK_WDR43X0_V1)
 
@@ -109,6 +116,12 @@
                                "rootfstype=squashfs init=/etc/preinit "\
                                "mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),320k(custom),1536k(kernel),12096k(rootfs),2048k(failsafe),64k(art)ro"
 
+#elif defined(CONFIG_FOR_GL_AR300)
+
+       #define CONFIG_BOOTARGS "console=ttyATH0,115200 root=31:02 "\
+                               "rootfstype=squashfs init=/sbin/init "\
+                               "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(art)ro"
+
 #elif defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\
       defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
       defined(CONFIG_FOR_TPLINK_WDR43X0_V1)
@@ -139,6 +152,8 @@
  */
 #if defined(CONFIG_FOR_ENGENIUS_ENS202EXT)
        #define CFG_LOAD_ADDR           0x9F0A0000
+#elif defined(CONFIG_FOR_GL_AR300)
+       #define CFG_LOAD_ADDR           0x9F050000
 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
        #define CFG_LOAD_ADDR           0x9F680000
 #else
@@ -156,6 +171,10 @@
        #define CFG_ENV_ADDR            0x9F040000
        #define CFG_ENV_SIZE            0x10000
        #define CFG_ENV_SECT_SIZE       0x10000
+#elif defined(CONFIG_FOR_GL_AR300)
+       #define CFG_ENV_ADDR            0x9F040000
+       #define CFG_ENV_SIZE            0xFC00
+       #define CFG_ENV_SECT_SIZE       0x10000
 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
        #define CFG_ENV_ADDR            0x9F020000
        #define CFG_ENV_SIZE            0xFC00
@@ -180,7 +199,8 @@
  * MAC address/es, model and WPS pin offsets in FLASH
  * ==================================================
  */
-#if defined(CONFIG_FOR_YUNCORE_CPE870)
+#if defined(CONFIG_FOR_GL_AR300) ||\
+    defined(CONFIG_FOR_YUNCORE_CPE870)
        #define OFFSET_MAC_DATA_BLOCK           0xFF0000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
        #define OFFSET_MAC_ADDRESS              0x000000
@@ -226,6 +246,8 @@
 /* Firmware size limit */
 #if defined(CONFIG_FOR_ENGENIUS_ENS202EXT)
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (2752 * 1024)
+#elif defined(CONFIG_FOR_GL_AR300)
+       #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (256 * 1024)
 #else
@@ -239,15 +261,20 @@
  */
 #define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200
 
-#if defined(CONFIG_FOR_TPLINK_MR3420_V2)  ||\
-    defined(CONFIG_FOR_TPLINK_WA801ND_V2) ||\
-    defined(CONFIG_FOR_TPLINK_WA830RE_V2) ||\
-    defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
-    defined(CONFIG_FOR_TPLINK_WDR43X0_V1) ||\
-    defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\
-    defined(CONFIG_FOR_TPLINK_WR1041N_V2) ||\
-    defined(CONFIG_FOR_TPLINK_WR841N_V8)  ||\
-    defined(CONFIG_FOR_YUNCORE_CPE870)
+#if defined(CONFIG_FOR_GL_AR300)
+
+       #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x40000
+       #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
+
+#elif defined(CONFIG_FOR_TPLINK_MR3420_V2)  ||\
+      defined(CONFIG_FOR_TPLINK_WA801ND_V2) ||\
+      defined(CONFIG_FOR_TPLINK_WA830RE_V2) ||\
+      defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
+      defined(CONFIG_FOR_TPLINK_WDR43X0_V1) ||\
+      defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\
+      defined(CONFIG_FOR_TPLINK_WR1041N_V2) ||\
+      defined(CONFIG_FOR_TPLINK_WR841N_V8)  ||\
+      defined(CONFIG_FOR_YUNCORE_CPE870)
 
        #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x10000
        #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
@@ -260,6 +287,7 @@
  * ==================================
  */
 #if !defined(CONFIG_FOR_ENGENIUS_ENS202EXT) &&\
+    !defined(CONFIG_FOR_GL_AR300)           &&\
     !defined(CONFIG_FOR_YUNCORE_CPE870)
        #define CONFIG_UPG_UBOOT_SIZE_BACKUP_HEX        0x20000
 #endif