Add support for TP-Link TL-WR1041N v2 (AR9342 based)
author魏亚祥 <weiyaxiang@gmail.com>
Wed, 30 Aug 2017 12:42:31 +0000 (20:42 +0800)
committerPiotr Dymacz <pepe2k@gmail.com>
Wed, 30 Aug 2017 17:45:13 +0000 (19:45 +0200)
Signed-off-by: 魏亚祥 <weiyaxiang@gmail.com>
Makefile
README.md
u-boot/Makefile
u-boot/board/ar7240/common/common.c
u-boot/include/configs/db12x.h
u-boot/include/soc/qca_soc_common.h

index c6ddf2dac69ac46e1219a487cc59463fac3a5524..388c6396a5a63133a1cf3d1fdea7d045f49c0bef 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -276,7 +276,8 @@ zbtlink_zbt-we1526:
        @$(call build,256,1,ETH_CONFIG=_s27)
 
 tp-link_tl-wdr3600_v1 \
-tp-link_tl-wdr43x0_v1:
+tp-link_tl-wdr43x0_v1 \
+tp-link_tl-wr1041n_v2:
        @$(call build,123,1,ETH_CONFIG=_s17)
 
 unwireddevices_unwired-one:
index d83a109ed050f9237540b9d0b077a6086b339c21..5ecbe9ceff121956466e13a693b3eccc105ce9ee 100644 (file)
--- a/README.md
+++ b/README.md
@@ -94,6 +94,9 @@ Currently supported devices:
   - TP-Link TL-WR841N/D v8
   - YunCore CPE870
 
+- **Atheros AR9342**:
+  - TP-Link TL-WR1041N v2
+
 - **Atheros AR9344**:
   - TP-Link TL-WDR3500 v1
   - TP-Link TL-WDR3600 v1
@@ -158,6 +161,7 @@ More information about supported devices:
 | [TP-Link TL-WDR3500 v1](http://wiki.openwrt.org/toh/tp-link/tl-wdr3500) | AR9344 | 8 MiB | 128 MiB DDR2 | 64 KiB, LZMA | RO |
 | [TP-Link TL-WDR3600 v1](http://wiki.openwrt.org/toh/tp-link/tl-wdr3600) | AR9344 | 8 MiB | 128 MiB DDR2 | 64 KiB, LZMA | RO |
 | [TP-Link TL-WDR43x0 v1](http://wiki.openwrt.org/toh/tp-link/tl-wdr4300) | AR9344 | 8 MiB | 128 MiB DDR2 | 64 KiB, LZMA | RO |
+| [TP-Link TL-WR1041N v2](http://wiki.openwrt.org/toh/tp-link/tl-wr1041n) | AR9342 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
 | [TP-Link TL-WR703N](http://wiki.openwrt.org/toh/tp-link/tl-wr703n) | AR9331 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
 | [TP-Link TL-WR710N v1](http://wiki.openwrt.org/toh/tp-link/tl-wr710n) | AR9331 | 8 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
 | [TP-Link TL-WR720N v3](http://wiki.openwrt.org/toh/tp-link/tl-wr720n) | AR9331 | 4 MiB | 32 MiB DDR1 | 64 KiB, LZMA | RO |
index 2546eacc94283cc1afde58f1eac35135ac96ceef..db008045c0b8f8af7b43d07f4b75f817c81f1f2c 100644 (file)
@@ -598,6 +598,14 @@ tp-link_tl-wdr43x0_v1: ar934x_common lsdk_kernel
        @$(call define_add,CFG_DUAL_PHY_SUPPORT,1)
        @$(MKCONFIG) -a db12x mips mips db12x ar7240 ar7240
 
+tp-link_tl-wr1041n_v2: ar934x_common lsdk_kernel
+       @$(call config_init,TP-Link TL-WR1041N v2,tl-wr1041n-v2,4,14,1,QCA_AR9342_SOC)
+       @$(call define_add,CONFIG_FOR_TPLINK_WR1041N_V2,1)
+       @$(call define_add,CFG_ATHRS17_PHY,1)
+       @$(call define_add,CFG_AG7240_NMACS,1)
+       @$(call define_add,CFG_DUAL_PHY_SUPPORT,1)
+       @$(MKCONFIG) -a db12x mips mips db12x ar7240 ar7240
+
 tp-link_tl-wr703n_v1: ar933x_common lsdk_kernel
        @$(call config_init,TP-Link TL-WR703N v1,tl-wr703n-v1,4,11,,QCA_AR933X_SOC)
        @$(call define_add,CONFIG_FOR_TPLINK_WR703N_V1,1)
index 1ae64b120b1a4a54a326e5bfbbc7383fa4815cfb..941007515717c933042b78be9859cd9c4d3da5a9 100644 (file)
@@ -53,6 +53,9 @@ void qca_soc_name_rev(char *buf)
        case QCA_RST_REVISION_ID_MAJOR_AR9341_VAL:
                sprintf(buf, "AR9341 rev. %d", rev);
                break;
+       case QCA_RST_REVISION_ID_MAJOR_AR9342_VAL:
+               sprintf(buf, "AR9342 rev. %d", rev);
+               break;
        case QCA_RST_REVISION_ID_MAJOR_AR9344_VAL:
                sprintf(buf, "AR9344 rev. %d", rev);
                break;
index 095d7f8305bb96c64d4cda3fb1aaad389cb50721..d8f423acf73bfc306ba34b9e62929620e3e66064 100644 (file)
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO12 |\
                                                CONFIG_QCA_GPIO_MASK_LED_ACT_L
 
+#elif defined(CONFIG_FOR_TPLINK_WR1041N_V2)
+
+       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13
+       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
+       #define CONFIG_QCA_GPIO_MASK_IN         GPIO14
+       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
 #elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
 
        #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13 |\
     defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
     defined(CONFIG_FOR_TPLINK_WDR43X0_V1) ||\
     defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\
+    defined(CONFIG_FOR_TPLINK_WR1041N_V2) ||\
     defined(CONFIG_FOR_TPLINK_WR841N_V8)  ||\
     defined(CONFIG_FOR_YUNCORE_CPE870)
 
index c7d64b6539fc26c504286d7de7de22ca6dce66e9..4a6ef0a45f79222b07c061b0611bf2fb3c0f1f49 100644 (file)
 #define QCA_RST_REVISION_ID_MAJOR_AR9330_VAL           0x0110
 #define QCA_RST_REVISION_ID_MAJOR_AR9331_VAL           0x1110
 #define QCA_RST_REVISION_ID_MAJOR_AR9341_VAL           0x0120
+#define QCA_RST_REVISION_ID_MAJOR_AR9342_VAL           0x1120
 #define QCA_RST_REVISION_ID_MAJOR_AR9344_VAL           0x2120
 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL          0x0140
 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL       0x0160