Migrate the arbiter configuration to Kconfig.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig"
source "arch/powerpc/cpu/mpc83xx/hid/Kconfig"
source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
menu "Legacy options"
--- /dev/null
+menu "Arbiter"
+
+choice
+ prompt "Pipeline depth"
+
+config ACR_PIPE_DEP_UNSET
+ bool "Don't set value"
+
+config ACR_PIPE_DEP_1
+ bool "1"
+
+config ACR_PIPE_DEP_2
+ bool "2"
+
+config ACR_PIPE_DEP_3
+ bool "3"
+
+config ACR_PIPE_DEP_4
+ bool "4"
+
+endchoice
+
+choice
+ prompt "Repeat count"
+
+config ACR_RPTCNT_UNSET
+ bool "Don't set value"
+
+config ACR_RPTCNT_1
+ bool "1"
+
+config ACR_RPTCNT_2
+ bool "2"
+
+config ACR_RPTCNT_3
+ bool "3"
+
+config ACR_RPTCNT_4
+ bool "4"
+
+config ACR_RPTCNT_5
+ bool "5"
+
+config ACR_RPTCNT_6
+ bool "6"
+
+config ACR_RPTCNT_7
+ bool "7"
+
+config ACR_RPTCNT_8
+ bool "8"
+
+endchoice
+
+choice
+ prompt "Address parking"
+
+config ACR_APARK_UNSET
+ bool "Don't set value"
+
+config ACR_APARK_MASTER
+ bool "Park to master"
+
+config ACR_APARK_LAST
+ bool "Park to last owner"
+
+config ACR_APARK_DISABLE
+ bool "Disabled"
+
+endchoice
+
+choice
+ prompt "Parking master"
+
+config ACR_PARKM_UNSET
+ bool "Don't set value"
+
+config ACR_PARKM_E300
+ bool "e300 core"
+
+config ACR_PARKM_TSEC_1_2
+ bool "TSEC1, TSEC2"
+
+config ACR_PARKM_USB_I2C1_BOOT
+ bool "USB/I2C1_BOOT"
+
+config ACR_PARKM_DMA_ESDHC_USB
+ bool "DMA, ESDHC, USB"
+
+config ACR_PARKM_PEX
+ bool "PCI Express"
+
+if MPC83XX_QUICC_ENGINE
+
+config ACR_PARKM_ENC_CORE
+ bool "Encryption core"
+
+endif
+
+endchoice
+
+config ACR_PIPE_DEP
+ hex
+ default 0x0 if ACR_PIPE_DEP_UNSET
+ default 0x0 if ACR_PIPE_DEP_1
+ default 0x10000 if ACR_PIPE_DEP_2
+ default 0x20000 if ACR_PIPE_DEP_3
+ default 0x30000 if ACR_PIPE_DEP_4
+
+config ACR_RPTCNT
+ hex
+ default 0x0 if ACR_RPTCNT_UNSET
+ default 0x0 if ACR_RPTCNT_1
+ default 0x100 if ACR_RPTCNT_2
+ default 0x200 if ACR_RPTCNT_3
+ default 0x300 if ACR_RPTCNT_4
+ default 0x400 if ACR_RPTCNT_5
+ default 0x500 if ACR_RPTCNT_6
+ default 0x600 if ACR_RPTCNT_7
+ default 0x700 if ACR_RPTCNT_8
+
+config ACR_APARK
+ hex
+ default 0x0 if ACR_APARK_UNSET
+ default 0x0 if ACR_APARK_MASTER
+ default 0x10 if ACR_APARK_LAST
+ default 0x20 if ACR_APARK_DISABLE
+
+config ACR_PARKM
+ hex
+ default 0x0 if ACR_PARKM_UNSET
+ default 0x0 if ACR_PARKM_E300
+ default 0x2 if ACR_PARKM_TSEC_1_2
+ default 0x3 if ACR_PARKM_USB_I2C1_BOOT
+ default 0x4 if ACR_PARKM_DMA_ESDHC_USB
+ default 0x5 if ACR_PARKM_PEX
+ default 0x5 if ACR_PARKM_ENC_CORE
+
+endmenu
--- /dev/null
+ const __be32 acr_mask =
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
+ ACR_PIPE_DEP |
+#endif
+#ifndef CONFIG_ACR_RPTCNT_UNSET
+ ACR_RPTCNT |
+#endif
+#ifndef CONFIG_ACR_APARK_UNSET
+ ACR_APARK |
+#endif
+#ifndef CONFIG_ACR_PARKM_UNSET
+ ACR_PARKM |
+#endif
+ 0;
+ const __be32 acr_val =
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
+ CONFIG_ACR_PIPE_DEP |
+#endif
+#ifndef CONFIG_ACR_RPTCNT_UNSET
+ CONFIG_ACR_RPTCNT |
+#endif
+#ifndef CONFIG_ACR_APARK_UNSET
+ CONFIG_ACR_APARK |
+#endif
+#ifndef CONFIG_ACR_PARKM_UNSET
+ CONFIG_ACR_PARKM |
+#endif
+ 0;
#include "lblaw/lblaw.h"
#include "elbc/elbc.h"
#include "sysio/sysio.h"
+#include "arbiter/arbiter.h"
DECLARE_GLOBAL_DATA_PTR;
*/
void cpu_init_f (volatile immap_t * im)
{
- __be32 acr_mask =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
- ACR_PIPE_DEP |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
- ACR_RPTCNT |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
- ACR_APARK |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
- ACR_PARKM |
-#endif
- 0;
- __be32 acr_val =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
- (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
- (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
-#endif
- 0;
__be32 spcr_mask =
#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
SPCR_OPT |
/* system performance tweaking */
-#ifdef CONFIG_SYS_ACR_PIPE_DEP
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
/* Arbiter pipeline depth */
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ CONFIG_ACR_PIPE_DEP;
#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT
+#ifndef CONFIG_ACR_RPTCNT_UNSET
/* Arbiter repeat count */
im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
+ CONFIG_ACR_RPTCNT;
#endif
#ifdef CONFIG_SYS_SPCR_OPT
CONFIG_SICR_GPIOSEL_IEEE1588=y
CONFIG_SICR_TMSOBI1_2_5_V=y
CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_PCI_ONE_PCI1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_PCI_ONE_PCI1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_LBLAW3_LENGTH_64_KBYTES=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"
CONFIG_LBLAW3_LENGTH_64_KBYTES=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_LBLAW3_LENGTH_64_KBYTES=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCIE"
CONFIG_SICR_GPIOSEL_IEEE1588=y
CONFIG_SICR_TMSOBI1_2_5_V=y
CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SICR_GPIOSEL_IEEE1588=y
CONFIG_SICR_TMSOBI1_2_5_V=y
CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_IMAGE_FORMAT_LEGACY=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
CONFIG_SICR_IEEE1588_A_GPIO=y
CONFIG_SICR_GTM_GPIO=y
CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=5
CONFIG_SICR_GPIOSEL_IEEE1588=y
CONFIG_SICR_TMSOBI1_2_5_V=y
CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SICR_GPIOSEL_IEEE1588=y
CONFIG_SICR_TMSOBI1_2_5_V=y
CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SICR_GPIOSEL_IEEE1588=y
CONFIG_SICR_TMSOBI1_2_5_V=y
CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SICR_GPIOSEL_IEEE1588=y
CONFIG_SICR_TMSOBI1_2_5_V=y
CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
*/
#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
/*
* Device configurations
*/
*/
#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
/*
* Device configurations
*/
#define CONFIG_HWCONFIG
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
*/
#define CONFIG_SYS_SICRL 0x00000000
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
#define CONFIG_SYS_SPCR_OPT 1
/*
* System performance
*/
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
/*
* System performance
*/
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
/*
* System performance
*/
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
*/
#define CONFIG_E300 1 /* E300 family */
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-
/* System Priority Control Register */
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
/* System performance - define the value i.e. CONFIG_SYS_XXX
*/
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
/* System Priority Control Regsiter */
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
#define CONFIG_BOOT_RETRY_MIN 30
#define CONFIG_RESET_TO_RETRY
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
#define CONFIG_SYS_SICRH 0x00000000
#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
/*
* DDR Setup
*/
#include "km/keymile-common.h"
#include "km/km-powerpc.h"
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
/*
* DDR Setup
*/
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
/*
* DDR Setup
*/
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
/*
* DDR Setup
*/
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
/*
* DDR Setup
*/
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
/*
* DDR Setup
*/
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
/*
* DDR Setup
*/
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
/*
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
/*
* DDR Setup
*/
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
/*
* DDR Setup
*/
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
/*
* DDR Setup
*/
#define CONFIG_SYS_MEMTEST_START 0x00001000
#define CONFIG_SYS_MEMTEST_END 0x07000000
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
-
/*
* Device configurations
*/
CONFIG_SYS_66MHZ
CONFIG_SYS_8313ERDB_BROKEN_PMC
CONFIG_SYS_83XX_DDR_USES_CS0
-CONFIG_SYS_ACR_APARK
-CONFIG_SYS_ACR_PARKM
-CONFIG_SYS_ACR_PIPE_DEP
-CONFIG_SYS_ACR_RPTCNT
CONFIG_SYS_ADDRESS_MAP_A
CONFIG_SYS_ADV7611_I2C
CONFIG_SYS_ALT_BOOT