imx8mm: Load fuse for TMU TCALIV and TASR
authorYe Li <ye.li@nxp.com>
Sun, 3 May 2020 14:19:52 +0000 (22:19 +0800)
committerStefano Babic <sbabic@denx.de>
Sun, 10 May 2020 18:55:20 +0000 (20:55 +0200)
On iMX8MM, the default value of TMU registers TCALIV and TASR need
be loaded from fuse. HW won't do this, it expect SW loads them before
using TMU.

Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
arch/arm/mach-imx/imx8m/soc.c

index 89229da3b62ac131a651711164a3178b40f11e11..dcec83e62488852d050be5a1430b73fd84c4ef94 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
  *
  * Peng Fan <peng.fan@nxp.com>
  */
@@ -448,3 +448,29 @@ int arch_misc_init(void)
        return 0;
 }
 #endif
+
+void imx_tmu_arch_init(void *reg_base)
+{
+       if (is_imx8mm()) {
+               /* Load TCALIV and TASR from fuses */
+               struct ocotp_regs *ocotp =
+                       (struct ocotp_regs *)OCOTP_BASE_ADDR;
+               struct fuse_bank *bank = &ocotp->bank[3];
+               struct fuse_bank3_regs *fuse =
+                       (struct fuse_bank3_regs *)bank->fuse_regs;
+
+               u32 tca_rt, tca_hr, tca_en;
+               u32 buf_vref, buf_slope;
+
+               tca_rt = fuse->ana0 & 0xFF;
+               tca_hr = (fuse->ana0 & 0xFF00) >> 8;
+               tca_en = (fuse->ana0 & 0x2000000) >> 25;
+
+               buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
+               buf_slope = (fuse->ana0 & 0xF0000) >> 16;
+
+               writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
+               writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
+                      (ulong)reg_base + 0x30);
+       }
+}