optimize aarch64 dynamic tlsdesc function to spill fewer registers

with the glibc generation counter model for reusing dynamic tls slots
after dlclose, it's really not possible to get away with fewer than 4
working registers. for us however it's always been possible, but
tricky, and only became apparent after the switch to installing new
dynamic tls at dlopen time. by merging the negated thread pointer into
the addend early, the register holding the thread pointer can
immediately be reused, bringing the working register count down to
three. this allows saving/restoring via a single stp/ldp pair, since
the return register x0 does not need to be saved.

net reduction of 3 instructions, 2 of which were push/pop.

diff --git a/src/ldso/aarch64/tlsdesc.s b/src/ldso/aarch64/tlsdesc.s
index c91baa453331cf91ba6d90b0f78f0a0f9847af12..04d97e730431a957dab6c2bbc7dfa0242265c20e 100644 (file)
--- a/src/ldso/aarch64/tlsdesc.s
+++ b/src/ldso/aarch64/tlsdesc.s
@@ -23,16 +23,13 @@ __tlsdesc_static:
 .hidden __tlsdesc_dynamic
 .type __tlsdesc_dynamic,@function
 __tlsdesc_dynamic:
-       stp x1,x2,[sp,#-32]!
-       stp x3,x4,[sp,#16]
+       stp x1,x2,[sp,#-16]!
        mrs x1,tpidr_el0      // tp
        ldr x0,[x0,#8]        // p
-       ldr x2,[x0]           // p->modidx
-       ldr x3,[x1,#-8]       // dtv
-       ldr x2,[x3,x2,lsl #3] // dtv[p->modidx]
-       ldr x0,[x0,#8]        // p->off
-       add x0,x0,x2
-       sub x0,x0,x1
-       ldp x3,x4,[sp,#16]
-       ldp x1,x2,[sp],#32
+       ldp x0,x2,[x0]        // p->modidx, p->off
+       sub x2,x2,x1          // p->off - tp
+       ldr x1,[x1,#-8]       // dtv
+       ldr x1,[x1,x0,lsl #3] // dtv[p->modidx]
+       add x0,x1,x2          // dtv[p->modidx] + p->off - tp
+       ldp x1,x2,[sp],#16
        ret