phy: atheros: Clarify the intention of ar8021_config

Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the common
function.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3e59c3f39150f912bda27f848298308d32ec0df3..3cc162828ca007aa94c758f57665f76d38ada039 100644 (file)
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -56,10 +56,10 @@ static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
 
 static int ar8021_config(struct phy_device *phydev)
 {
-       phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
-       phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
-                 AR803x_DEBUG_REG_5);
-       phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 0x3D47);
+       phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
+                 BMCR_ANENABLE | BMCR_ANRESTART);
+
+       ar803x_enable_tx_delay(phydev, true);
 
        phydev->supported = phydev->drv->features;
        return 0;