riscv: Remove unnecessary instruction

The add instruction on risc-v can have any three sources and targets, so there
is no need for an intermediate mov.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index f3dccdbe4c55a3279e0e3f6eb3d8d81b030ab8cd..6b3ff99c3882e9b4d30009842a0e14a09ff6ee81 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -359,9 +359,8 @@ relocate_secondary_harts:
 call_board_init_r:
        jal     invalidate_icache_all
        jal     flush_dcache_all
-       la      t0, board_init_r
-       mv      t4, t0                  /* offset of board_init_r() */
-       add     t4, t4, t6              /* real address of board_init_r() */
+       la      t0, board_init_r        /* offset of board_init_r() */
+       add     t4, t0, t6              /* real address of board_init_r() */
 /*
  * setup parameters for board_init_r
  */