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(parent: 1a28c6e) | patch
fix riscv64 syscall asm constraint
authorRich Felker <dalias@aerifal.cx>
Wed, 17 Jul 2019 22:50:15 +0000 (18:50 -0400)
committerRich Felker <dalias@aerifal.cx>
Wed, 17 Jul 2019 22:50:15 +0000 (18:50 -0400)
commit8eb49e0485fc547eead9e47200bbee6d81f391c1
tree393cbf5431a7d053eef7d2a36e031ea8e62421d8tree | snapshot
parent1a28c6eade3046e73da0e80bbb7c377f24f514c7commit | diff
fix riscv64 syscall asm constraint

having "+r"(a0) is redundant with "0"(a0) in syscalls with at least 1
arg, which is arguably a constraint violation (clang treats it as
such), and an invalid input with indeterminate value in the 0-arg
case. use the "=r"(a0) form instead.
arch/riscv64/syscall_arch.h diff | blob | history
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