armv8: lx2160a: Add LX2160A SoC Support

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / config.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index bd4ca88e1669c92e6407e8cff7481770d15571cf..d4f80a24cd713fff76ce5862e30df5bba87de1c0 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * Copyright 2016-2018 NXP
  * Copyright 2015, Freescale Semiconductor
  */
 
@@ -176,6 +177,61 @@
 #define SYS_FSL_OCRAM_SPACE_SIZE       0x00200000 /* 2M space */
 #define CONFIG_SYS_FSL_OCRAM_SIZE      0x00020000 /* Real size 128K */
 
+/* LX2160A Soc Support */
+#elif defined(CONFIG_ARCH_LX2160A)
+#define TZPC_BASE                              0x02200000
+#define TZPCDECPROT_0_SET_BASE                 (TZPC_BASE + 0x804)
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define SRDS_MAX_LANES  8
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT         6
+#define L1_CACHE_BYTES         BIT(L1_CACHE_SHIFT)
+#endif
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER       2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 1, 1, 4, 4, 4, 4 }
+#define CONFIG_SYS_FSL_NUM_CC_PLLS             4
+
+#define CONFIG_SYS_PAGE_SIZE                   0x10000
+
+#define CONFIG_SYS_FSL_OCRAM_BASE              0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE               0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE              0x00040000 /* Real size 256K */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE                              0x06000000
+#define GICR_BASE                              0x06200000
+
+/* SMMU Definitions */
+#define SMMU_BASE                              0x05000000 /* GR0 Base */
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
+
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE               0x00200000 /* 2M space */