+# 0x30 mUsbEPMap EP1
+# 0x31 mUsbEPMap EP2
+# 0x32 mUsbEPMap EP3
+# 0x33 mUsbEPMap EP4
+# 0x34 mUsbEPMap EP5
+# 0x35 mUsbEPMap EP6
+# 0x36 mUsbEPMap EP7
+# 0x37 mUsbEPMap EP8
+# 0x38 mUsbEPMap EP9
+# 0x39 mUsbEPMap EP10
+# 0x3a mUsbEPMap EP11
+# 0x3b mUsbEPMap EP12
+# 0x3c mUsbEPMap EP13
+# 0x3d mUsbEPMap EP14
+# 0x3e mUsbEPMap EP15
+
+# 0x3E ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP0
+* BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_IN_MAX_SIZE_LOW_OFFSET + ZM_EP_IN_MAX_SIZE_HIGH_OFFSET)
+
+# 0x3F ZM_EP_IN_MAX_SIZE_HIGH_OFFSET EP0
+* BIT7
+* BIT6
+* BIT5
+* BIT4 - mUsbEPinRsTgSet
+* BIT3 - mUsbEPinStallSet
+* BIT0 - BIT2; High size regs
+These offset + 2 Byte step for each endpoint.
+For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
+
+
+# 0x40 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP1
+# 0x42 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP2
+# 0x44 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP3
+# 0x46 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP4
+# 0x48 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP5
+# 0x4A ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP6
+# 0x4C ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP7
+# 0x4E ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP8
+# 0x50 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP9
+# 0x52 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP10
+# 0x54 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP11
+# 0x56 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP12
+# 0x58 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP13
+# 0x5A ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP14
+# 0x5C ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP15
+
+# 0x5E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP0
+* BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_OUT_MAX_SIZE_LOW_OFFSET + ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET)
+
+# 0x5F ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET EP0
+* BIT7
+* BIT6
+* BIT5
+* BIT4 - mUsbEPoutRsTgSet
+* BIT3 - mUsbEPoutStallSet
+* BIT0 - BIT2; High size regs
+
+These offset + 2 Byte step for each endpoint.
+For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
+
+# 0x60 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP1
+# 0x62 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP2
+# 0x64 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP3
+# 0x66 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP4
+# 0x68 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP5
+# 0x6A ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP6
+# 0x6C ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP7
+# 0x6E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP8
+# 0x70 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP9
+# 0x72 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP10
+# 0x74 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP11
+# 0x76 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP12
+# 0x78 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP13
+# 0x7A ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP14
+# 0x7C ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP15
+
+# 0x80 mUsbFIFOMap FIFO0
+* BIT7
+* BIT6
+* BIT5
+* BIT4 - Direction: 0 - OUT; 1 - IN.
+* BIT0 - BIT3: assigned EP number.
+
+Current layout:
+* 0x80 0x01 - EP1 OUT
+* 0x81 0x01 - EP1 OUT
+* 0x82 0x12 - EP2 IN
+* 0x83 0x12 - EP2 IN
+* 0x84 0x05
+* 0x85 0x05
+* 0x86 0x06
+* 0x87 0x06
+* 0x88 0x00
+* 0x89 0x00
+* 0x8a 0x00
+* 0x8b 0x00
+* 0x8c 0x00
+* 0x8d 0x00
+* 0x8e 0x13
+* 0x8f 0x04
+
+# 0x81 mUsbFIFOMap FIFO1
+# 0x82 mUsbFIFOMap FIFO2
+# 0x83 mUsbFIFOMap FIFO3
+# 0x84 mUsbFIFOMap FIFO4
+# 0x85 mUsbFIFOMap FIFO5
+# 0x86 mUsbFIFOMap FIFO6
+# 0x87 mUsbFIFOMap FIFO7
+# 0x88 mUsbFIFOMap FIFO8
+# 0x89 mUsbFIFOMap FIFO9
+# 0x8a mUsbFIFOMap FIFO10
+# 0x8b mUsbFIFOMap FIFO11
+# 0x8c mUsbFIFOMap FIFO12
+# 0x8d mUsbFIFOMap FIFO13
+# 0x8e mUsbFIFOMap FIFO14
+# 0x8f mUsbFIFOMap FIFO15
+
+# 0x90 mUsbFIFOConfig FIFO0
+* BIT7 - If EPn use more then one FIFO, then this bit should be on the first
+* BIT6
+* BIT5
+* BIT4 - Block size: 0 - 64/512; 1 - 128/1024. It depends on initial FIFO size.
+* BIT2 - BIT3; number of FIFO blocks or better to say extra blocks? 0 - no more blocks; 1 - one block; 2 - two blocks.
+* BIT0 - BIT1; EP type: 0x1 - Iso; 0x2 - Bulk, 0x3 - Intr;
+
+* 0x90 0x86 <- FIFO0: Bulk | + one block (0x91) | size 512
+* 0x91 0x06
+* 0x92 0x86
+* 0x93 0x06
+* 0x94 0x86
+* 0x95 0x06
+* 0x96 0x86
+* 0x97 0x06
+* 0x98 0x00
+* 0x99 0x00
+* 0x9a 0x00
+* 0x9b 0x00
+* 0x9c 0x00
+* 0x9d 0x00
+* 0x9e 0x83
+* 0x9f 0x83
+
+# 0x91 mUsbFIFOConfig FIFO1
+# 0x92 mUsbFIFOConfig FIFO2
+# 0x93 mUsbFIFOConfig FIFO3
+# 0x94 mUsbFIFOConfig FIFO4
+# 0x95 mUsbFIFOConfig FIFO5
+# 0x96 mUsbFIFOConfig FIFO6
+# 0x97 mUsbFIFOConfig FIFO7
+# 0x98 mUsbFIFOConfig FIFO8
+# 0x99 mUsbFIFOConfig FIFO9
+# 0x9a mUsbFIFOConfig FIFO10
+# 0x9b mUsbFIFOConfig FIFO11
+# 0x9c mUsbFIFOConfig FIFO12
+# 0x9d mUsbFIFOConfig FIFO13
+# 0x9e mUsbFIFOConfig FIFO14
+# 0x9f mUsbFIFOConfig FIFO15