target/linux/layerscape/patches-4.9/817-usb-support-layerscape.patch

   1 From a2a97f0d2c07a772899ca09967547bea6c9124c5 Mon Sep 17 00:00:00 2001
   2 From: Yangbo Lu <yangbo.lu@nxp.com>
   3 Date: Wed, 17 Jan 2018 15:46:03 +0800
   4 Subject: [PATCH 29/30] usb: support layerscape
   5
   6 This is an integrated patch for layerscape usb support.
   7
   8 Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
   9 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
  10 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
  11 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
  12 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
  13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
  14 Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
  15 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
  16 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  17 ---
  18  drivers/net/usb/cdc_ether.c           |   8 +
  19  drivers/net/usb/r8152.c               |   6 +
  20  drivers/usb/common/common.c           |  50 ++++++
  21  drivers/usb/core/hub.c                |   8 +
  22  drivers/usb/dwc3/core.c               | 243 ++++++++++++++++++++++++++++-
  23  drivers/usb/dwc3/core.h               |  51 ++++++-
  24  drivers/usb/dwc3/ep0.c                |   4 +-
  25  drivers/usb/dwc3/gadget.c             |   7 +
  26  drivers/usb/dwc3/host.c               |  24 ++-
  27  drivers/usb/gadget/udc/fsl_udc_core.c |  46 +++---
  28  drivers/usb/gadget/udc/fsl_usb2_udc.h |  16 +-
  29  drivers/usb/host/Kconfig              |   2 +-
  30  drivers/usb/host/ehci-fsl.c           | 279 +++++++++++++++++++++++++++++++---
  31  drivers/usb/host/ehci-fsl.h           |   3 +
  32  drivers/usb/host/ehci-hub.c           |   4 +
  33  drivers/usb/host/ehci.h               |   9 ++
  34  drivers/usb/host/fsl-mph-dr-of.c      |  12 ++
  35  drivers/usb/host/xhci-plat.c          |  10 ++
  36  drivers/usb/host/xhci-ring.c          |  29 +++-
  37  drivers/usb/host/xhci.c               |  38 ++++-
  38  drivers/usb/host/xhci.h               |   5 +-
  39  drivers/usb/phy/phy-fsl-usb.c         |  59 +++++--
  40  drivers/usb/phy/phy-fsl-usb.h         |   8 +
  41  include/linux/usb.h                   |   1 +
  42  include/linux/usb/of.h                |   2 +
  43  25 files changed, 836 insertions(+), 88 deletions(-)
  44
  45 --- a/drivers/net/usb/cdc_ether.c
  46 +++ b/drivers/net/usb/cdc_ether.c
  47 @@ -540,6 +540,7 @@ static const struct driver_info wwan_inf
  48  #define LINKSYS_VENDOR_ID      0x13b1
  49  #define NVIDIA_VENDOR_ID       0x0955
  50  #define HP_VENDOR_ID           0x03f0
  51 +#define TPLINK_VENDOR_ID       0x2357
  52
  53  static const struct usb_device_id      products[] = {
  54  /* BLACKLIST !!
  55 @@ -749,6 +750,13 @@ static const struct usb_device_id  produc
  56                         USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
  57         .driver_info = 0,
  58  },
  59 +
  60 +       /* TP-LINK UE300 USB 3.0 Ethernet Adapters (based on Realtek RTL8153) */
  61 +{
  62 +       USB_DEVICE_AND_INTERFACE_INFO(TPLINK_VENDOR_ID, 0x0601, USB_CLASS_COMM,
  63 +                       USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
  64 +       .driver_info = 0,
  65 +},
  66
  67  /* WHITELIST!!!
  68   *
  69 --- a/drivers/net/usb/r8152.c
  70 +++ b/drivers/net/usb/r8152.c
  71 @@ -521,6 +521,7 @@ enum rtl8152_flags {
  72  #define VENDOR_ID_LENOVO               0x17ef
  73  #define VENDOR_ID_LINKSYS              0x13b1
  74  #define VENDOR_ID_NVIDIA               0x0955
  75 +#define VENDOR_ID_TPLINK               0x2357
  76
  77  #define MCU_TYPE_PLA                   0x0100
  78  #define MCU_TYPE_USB                   0x0000
  79 @@ -1820,6 +1821,10 @@ static int rx_bottom(struct r8152 *tp, i
  80                         unsigned int pkt_len;
  81                         struct sk_buff *skb;
  82
  83 +                       /* limite the skb numbers for rx_queue */
  84 +                       if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
  85 +                               break;
  86 +
  87                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  88                         if (pkt_len < ETH_ZLEN)
  89                                 break;
  90 @@ -4516,6 +4521,7 @@ static struct usb_device_id rtl8152_tabl
  91         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
  92         {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
  93         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
  94 +       {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
  95         {}
  96  };
  97
  98 --- a/drivers/usb/common/common.c
  99 +++ b/drivers/usb/common/common.c
 100 @@ -105,6 +105,56 @@ static const char *const usb_dr_modes[]
 101         [USB_DR_MODE_OTG]               = "otg",
 102  };
 103
 104 +/**
 105 + * of_usb_get_dr_mode - Get dual role mode for given device_node
 106 + * @np:        Pointer to the given device_node
 107 + *
 108 + * The function gets phy interface string from property 'dr_mode',
 109 + * and returns the correspondig enum usb_dr_mode
 110 + */
 111 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
 112 +{
 113 +       const char *dr_mode;
 114 +       int err, i;
 115 +
 116 +       err = of_property_read_string(np, "dr_mode", &dr_mode);
 117 +       if (err < 0)
 118 +               return USB_DR_MODE_UNKNOWN;
 119 +
 120 +       for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
 121 +               if (!strcmp(dr_mode, usb_dr_modes[i]))
 122 +                       return i;
 123 +
 124 +       return USB_DR_MODE_UNKNOWN;
 125 +}
 126 +EXPORT_SYMBOL_GPL(of_usb_get_dr_mode);
 127 +
 128 +/**
 129 + * of_usb_get_maximum_speed - Get maximum requested speed for a given USB
 130 + * controller.
 131 + * @np: Pointer to the given device_node
 132 + *
 133 + * The function gets the maximum speed string from property "maximum-speed",
 134 + * and returns the corresponding enum usb_device_speed.
 135 + */
 136 +enum usb_device_speed of_usb_get_maximum_speed(struct device_node *np)
 137 +{
 138 +       const char *maximum_speed;
 139 +       int err;
 140 +       int i;
 141 +
 142 +       err = of_property_read_string(np, "maximum-speed", &maximum_speed);
 143 +       if (err < 0)
 144 +               return USB_SPEED_UNKNOWN;
 145 +
 146 +       for (i = 0; i < ARRAY_SIZE(speed_names); i++)
 147 +               if (strcmp(maximum_speed, speed_names[i]) == 0)
 148 +                       return i;
 149 +
 150 +               return USB_SPEED_UNKNOWN;
 151 +}
 152 +EXPORT_SYMBOL_GPL(of_usb_get_maximum_speed);
 153 +
 154  static enum usb_dr_mode usb_get_dr_mode_from_string(const char *str)
 155  {
 156         int ret;
 157 --- a/drivers/usb/core/hub.c
 158 +++ b/drivers/usb/core/hub.c
 159 @@ -4454,6 +4454,14 @@ hub_port_init(struct usb_hub *hub, struc
 160         else
 161                 speed = usb_speed_string(udev->speed);
 162
 163 +#if !defined(CONFIG_FSL_USB2_OTG) && !defined(CONFIG_FSL_USB2_OTG_MODULE)
 164 +if (udev->speed != USB_SPEED_SUPER)
 165 +       dev_info(&udev->dev,
 166 +       "%s %s USB device number %d using %s\n",
 167 +        (udev->config) ? "reset" : "new", speed,
 168 +       devnum, udev->bus->controller->driver->name);
 169 +#endif
 170 +
 171         if (udev->speed < USB_SPEED_SUPER)
 172                 dev_info(&udev->dev,
 173                                 "%s %s USB device number %d using %s\n",
 174 --- a/drivers/usb/dwc3/core.c
 175 +++ b/drivers/usb/dwc3/core.c
 176 @@ -58,6 +58,7 @@ static int dwc3_get_dr_mode(struct dwc3
 177         enum usb_dr_mode mode;
 178         struct device *dev = dwc->dev;
 179         unsigned int hw_mode;
 180 +       struct device_node      *node = dev->of_node;
 181
 182         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 183                 dwc->dr_mode = USB_DR_MODE_OTG;
 184 @@ -83,6 +84,24 @@ static int dwc3_get_dr_mode(struct dwc3
 185                 mode = USB_DR_MODE_HOST;
 186                 break;
 187         default:
 188 +               /* Adjust Frame Length */
 189 +               if (dwc->configure_gfladj)
 190 +               dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
 191 +                               GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
 192 +
 193 +       /* Change burst beat and outstanding pipelined transfers requests */
 194 +       dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
 195 +               (dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) & ~0xff) | 0xf);
 196 +       dwc3_writel(dwc->regs, DWC3_GSBUSCFG1,
 197 +               dwc3_readl(dwc->regs, DWC3_GSBUSCFG1) | 0xf00);
 198 +
 199 +       /* Enable Snooping */
 200 +       if (node && of_dma_is_coherent(node)) {
 201 +               dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
 202 +               dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) | 0x22220000);
 203 +               dev_dbg(dev, "enabled snooping for usb\n");
 204 +       }
 205 +
 206                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
 207                         mode = USB_DR_MODE_HOST;
 208                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 209 @@ -598,6 +617,99 @@ static int dwc3_phy_setup(struct dwc3 *d
 210         return 0;
 211  }
 212
 213 +/* set global soc bus configuration registers */
 214 +static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
 215 +{
 216 +       struct device *dev = dwc->dev;
 217 +       u32 *vals;
 218 +       u32 cfg;
 219 +       int ntype;
 220 +       int ret;
 221 +       int i;
 222 +
 223 +       cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 224 +
 225 +       /*
 226 +        * Handle property "snps,incr-burst-type-adjustment".
 227 +        * Get the number of value from this property:
 228 +        * result <= 0, means this property is not supported.
 229 +        * result = 1, means INCRx burst mode supported.
 230 +        * result > 1, means undefined length burst mode supported.
 231 +        */
 232 +       ntype = device_property_read_u32_array(dev,
 233 +                       "snps,incr-burst-type-adjustment", NULL, 0);
 234 +       if (ntype > 0) {
 235 +               vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 236 +               if (!vals) {
 237 +                       dev_err(dev, "Error to get memory\n");
 238 +                       return;
 239 +               }
 240 +               /* Get INCR burst type, and parse it */
 241 +               ret = device_property_read_u32_array(dev,
 242 +                       "snps,incr-burst-type-adjustment", vals, ntype);
 243 +               if (ret) {
 244 +                       dev_err(dev, "Error to get property\n");
 245 +                       return;
 246 +               }
 247 +               *(dwc->incrx_type + 1) = vals[0];
 248 +               if (ntype > 1) {
 249 +                       *dwc->incrx_type = 1;
 250 +                       for (i = 1; i < ntype; i++) {
 251 +                               if (vals[i] > *(dwc->incrx_type + 1))
 252 +                                       *(dwc->incrx_type + 1) = vals[i];
 253 +                       }
 254 +               } else
 255 +                       *dwc->incrx_type = 0;
 256 +
 257 +               /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 258 +               cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 259 +               if (*dwc->incrx_type)
 260 +                       cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 261 +               switch (*(dwc->incrx_type + 1)) {
 262 +               case 256:
 263 +                       cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 264 +                       break;
 265 +               case 128:
 266 +                       cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 267 +                       break;
 268 +               case 64:
 269 +                       cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 270 +                       break;
 271 +               case 32:
 272 +                       cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 273 +                       break;
 274 +               case 16:
 275 +                       cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 276 +                       break;
 277 +               case 8:
 278 +                       cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 279 +                       break;
 280 +               case 4:
 281 +                       cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 282 +                       break;
 283 +               case 1:
 284 +                       break;
 285 +               default:
 286 +                       dev_err(dev, "Invalid property\n");
 287 +                       break;
 288 +               }
 289 +       }
 290 +
 291 +       /* Handle usb snooping */
 292 +       if (dwc->dma_snooping_quirk) {
 293 +               cfg &= ~DWC3_GSBUSCFG0_SNP_MASK;
 294 +               cfg |= (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATARD_SHIFT) |
 295 +                       (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCRD_SHIFT) |
 296 +                       (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATAWR_SHIFT) |
 297 +                       (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCWR_SHIFT);
 298 +       }
 299 +
 300 +       dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 301 +
 302 +}
 303 +
 304 +
 305 +
 306  static void dwc3_core_exit(struct dwc3 *dwc)
 307  {
 308         dwc3_event_buffers_cleanup(dwc);
 309 @@ -740,6 +852,8 @@ static int dwc3_core_init(struct dwc3 *d
 310         if (ret)
 311                 goto err1;
 312
 313 +       dwc3_set_soc_bus_cfg(dwc);
 314 +
 315         /* Adjust Frame Length */
 316         dwc3_frame_length_adjustment(dwc);
 317
 318 @@ -938,11 +1052,117 @@ static void dwc3_core_exit_mode(struct d
 319         }
 320  }
 321
 322 +static void dwc3_get_properties(struct dwc3 *dwc)
 323 +{
 324 +       struct device           *dev = dwc->dev;
 325 +       struct device_node      *node = dev->of_node;
 326 +       u8                      lpm_nyet_threshold;
 327 +       u8                      tx_de_emphasis;
 328 +       u8                      hird_threshold;
 329 +
 330 +       /* default to highest possible threshold */
 331 +       lpm_nyet_threshold = 0xff;
 332 +
 333 +       /* default to -3.5dB de-emphasis */
 334 +       tx_de_emphasis = 1;
 335 +
 336 +       /*
 337 +        * default to assert utmi_sleep_n and use maximum allowed HIRD
 338 +        * threshold value of 0b1100
 339 +        */
 340 +       hird_threshold = 12;
 341 +
 342 +       dwc->maximum_speed = usb_get_maximum_speed(dev);
 343 +       dwc->dr_mode = usb_get_dr_mode(dev);
 344 +       dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
 345 +
 346 +       dwc->sysdev_is_parent = device_property_read_bool(dev,
 347 +                               "linux,sysdev_is_parent");
 348 +       if (dwc->sysdev_is_parent)
 349 +               dwc->sysdev = dwc->dev->parent;
 350 +       else
 351 +               dwc->sysdev = dwc->dev;
 352 +
 353 +       dwc->has_lpm_erratum = device_property_read_bool(dev,
 354 +                               "snps,has-lpm-erratum");
 355 +       device_property_read_u8(dev, "snps,lpm-nyet-threshold",
 356 +                               &lpm_nyet_threshold);
 357 +       dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
 358 +                               "snps,is-utmi-l1-suspend");
 359 +       device_property_read_u8(dev, "snps,hird-threshold",
 360 +                               &hird_threshold);
 361 +       dwc->usb3_lpm_capable = device_property_read_bool(dev,
 362 +                               "snps,usb3_lpm_capable");
 363 +       dwc->quirk_reverse_in_out = device_property_read_bool(dev,
 364 +                               "snps,quirk_reverse_in_out");
 365 +       dwc->quirk_stop_transfer_in_block = device_property_read_bool(dev,
 366 +                               "snps,quirk_stop_transfer_in_block");
 367 +       dwc->quirk_stop_ep_in_u1 = device_property_read_bool(dev,
 368 +                               "snps,quirk_stop_ep_in_u1");
 369 +
 370 +       dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
 371 +
 372 +       dwc->configure_gfladj =
 373 +                               of_property_read_bool(node, "configure-gfladj");
 374 +       dwc->dr_mode = usb_get_dr_mode(dev);
 375 +
 376 +       dwc->disable_scramble_quirk = device_property_read_bool(dev,
 377 +                               "snps,disable_scramble_quirk");
 378 +       dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
 379 +                               "snps,u2exit_lfps_quirk");
 380 +       dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
 381 +                               "snps,u2ss_inp3_quirk");
 382 +       dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
 383 +                               "snps,req_p1p2p3_quirk");
 384 +       dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
 385 +                               "snps,del_p1p2p3_quirk");
 386 +       dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
 387 +                               "snps,del_phy_power_chg_quirk");
 388 +       dwc->lfps_filter_quirk = device_property_read_bool(dev,
 389 +                               "snps,lfps_filter_quirk");
 390 +       dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
 391 +                               "snps,rx_detect_poll_quirk");
 392 +       dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
 393 +                               "snps,dis_u3_susphy_quirk");
 394 +       dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
 395 +                               "snps,dis_u2_susphy_quirk");
 396 +       dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
 397 +                               "snps,dis_enblslpm_quirk");
 398 +       dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
 399 +                               "snps,dis_rxdet_inp3_quirk");
 400 +       dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
 401 +                               "snps,dis-u2-freeclk-exists-quirk");
 402 +       dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
 403 +                               "snps,dis-del-phy-power-chg-quirk");
 404 +       dwc->dma_snooping_quirk = device_property_read_bool(dev,
 405 +                               "snps,dma-snooping");
 406 +
 407 +       dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 408 +                               "snps,tx_de_emphasis_quirk");
 409 +       dwc->disable_devinit_u1u2_quirk = device_property_read_bool(dev,
 410 +                               "snps,disable_devinit_u1u2");
 411 +       device_property_read_u8(dev, "snps,tx_de_emphasis",
 412 +                               &tx_de_emphasis);
 413 +       device_property_read_string(dev, "snps,hsphy_interface",
 414 +                               &dwc->hsphy_interface);
 415 +       device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
 416 +                               &dwc->fladj);
 417 +
 418 +       dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 419 +       dwc->tx_de_emphasis = tx_de_emphasis;
 420 +
 421 +       dwc->hird_threshold = hird_threshold
 422 +               | (dwc->is_utmi_l1_suspend << 4);
 423 +
 424 +       dwc->imod_interval = 0;
 425 +}
 426 +
 427  #define DWC3_ALIGN_MASK                (16 - 1)
 428
 429  static int dwc3_probe(struct platform_device *pdev)
 430  {
 431         struct device           *dev = &pdev->dev;
 432 +       struct device_node      *node = dev->of_node;
 433         struct resource         *res;
 434         struct dwc3             *dwc;
 435         u8                      lpm_nyet_threshold;
 436 @@ -974,6 +1194,11 @@ static int dwc3_probe(struct platform_de
 437         dwc->xhci_resources[0].flags = res->flags;
 438         dwc->xhci_resources[0].name = res->name;
 439
 440 +       if (node) {
 441 +               dwc->configure_gfladj =
 442 +                       of_property_read_bool(node, "configure-gfladj");
 443 +       }
 444 +
 445         res->start += DWC3_GLOBALS_REGS_START;
 446
 447         /*
 448 @@ -1016,6 +1241,12 @@ static int dwc3_probe(struct platform_de
 449         dwc->usb3_lpm_capable = device_property_read_bool(dev,
 450                                 "snps,usb3_lpm_capable");
 451
 452 +       dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
 453 +
 454 +       dwc->configure_gfladj =
 455 +                       of_property_read_bool(node, "configure-gfladj");
 456 +       dwc->dr_mode = of_usb_get_dr_mode(node);
 457 +
 458         dwc->disable_scramble_quirk = device_property_read_bool(dev,
 459                                 "snps,disable_scramble_quirk");
 460         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
 461 @@ -1060,6 +1291,8 @@ static int dwc3_probe(struct platform_de
 462         dwc->hird_threshold = hird_threshold
 463                 | (dwc->is_utmi_l1_suspend << 4);
 464
 465 +       dwc3_get_properties(dwc);
 466 +
 467         platform_set_drvdata(pdev, dwc);
 468         dwc3_cache_hwparams(dwc);
 469
 470 @@ -1083,6 +1316,11 @@ static int dwc3_probe(struct platform_de
 471         if (ret < 0)
 472                 goto err1;
 473
 474 +       /* Adjust Frame Length */
 475 +       if (dwc->configure_gfladj)
 476 +       dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
 477 +                   GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
 478 +
 479         pm_runtime_forbid(dev);
 480
 481         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 482 --- a/drivers/usb/dwc3/core.h
 483 +++ b/drivers/usb/dwc3/core.h
 484 @@ -26,6 +26,7 @@
 485  #include <linux/dma-mapping.h>
 486  #include <linux/mm.h>
 487  #include <linux/debugfs.h>
 488 +#include <linux/of_address.h>
 489
 490  #include <linux/usb/ch9.h>
 491  #include <linux/usb/gadget.h>
 492 @@ -154,6 +155,32 @@
 493
 494  /* Bit fields */
 495
 496 +/* Global SoC Bus Configuration Register 0 */
 497 +#define AXI3_CACHE_TYPE_AW             0x8 /* write allocate */
 498 +#define AXI3_CACHE_TYPE_AR             0x4 /* read allocate */
 499 +#define AXI3_CACHE_TYPE_SNP            0x2 /* cacheable */
 500 +#define AXI3_CACHE_TYPE_BUF            0x1 /* bufferable */
 501 +#define DWC3_GSBUSCFG0_DATARD_SHIFT    28
 502 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT    24
 503 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT    20
 504 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT    16
 505 +#define DWC3_GSBUSCFG0_SNP_MASK                0xffff0000
 506 +#define DWC3_GSBUSCFG0_DATABIGEND      (1 << 11)
 507 +#define DWC3_GSBUSCFG0_DESCBIGEND      (1 << 10)
 508 +#define DWC3_GSBUSCFG0_INCR256BRSTENA  (1 << 7) /* INCR256 burst */
 509 +#define DWC3_GSBUSCFG0_INCR128BRSTENA  (1 << 6) /* INCR128 burst */
 510 +#define DWC3_GSBUSCFG0_INCR64BRSTENA   (1 << 5) /* INCR64 burst */
 511 +#define DWC3_GSBUSCFG0_INCR32BRSTENA   (1 << 4) /* INCR32 burst */
 512 +#define DWC3_GSBUSCFG0_INCR16BRSTENA   (1 << 3) /* INCR16 burst */
 513 +#define DWC3_GSBUSCFG0_INCR8BRSTENA    (1 << 2) /* INCR8 burst */
 514 +#define DWC3_GSBUSCFG0_INCR4BRSTENA    (1 << 1) /* INCR4 burst */
 515 +#define DWC3_GSBUSCFG0_INCRBRSTENA     (1 << 0) /* undefined length enable */
 516 +#define DWC3_GSBUSCFG0_INCRBRST_MASK   0xff
 517 +
 518 +/* Global SoC Bus Configuration Register 1 */
 519 +#define DWC3_GSBUSCFG1_1KPAGEENA       (1 << 12) /* 1K page boundary enable */
 520 +#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK        0xf00
 521 +
 522  /* Global Debug Queue/FIFO Space Available Register */
 523  #define DWC3_GDBGFIFOSPACE_NUM(n)      ((n) & 0x1f)
 524  #define DWC3_GDBGFIFOSPACE_TYPE(n)     (((n) << 5) & 0x1e0)
 525 @@ -182,7 +209,6 @@
 526  #define DWC3_GCTL_CLK_PIPE     (1)
 527  #define DWC3_GCTL_CLK_PIPEHALF (2)
 528  #define DWC3_GCTL_CLK_MASK     (3)
 529 -
 530  #define DWC3_GCTL_PRTCAP(n)    (((n) & (3 << 12)) >> 12)
 531  #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
 532  #define DWC3_GCTL_PRTCAP_HOST  1
 533 @@ -294,6 +320,10 @@
 534  /* Global Frame Length Adjustment Register */
 535  #define DWC3_GFLADJ_30MHZ_SDBND_SEL            (1 << 7)
 536  #define DWC3_GFLADJ_30MHZ_MASK                 0x3f
 537 +#define GFLADJ_30MHZ_REG_SEL           (1 << 7)
 538 +#define GFLADJ_30MHZ(n)                        ((n) & 0x3f)
 539 +#define GFLADJ_30MHZ_DEFAULT           0x20
 540 +
 541
 542  /* Global User Control Register 2 */
 543  #define DWC3_GUCTL2_RST_ACTBITLATER            (1 << 14)
 544 @@ -758,6 +788,7 @@ struct dwc3_scratchpad_array {
 545   * @regs: base address for our registers
 546   * @regs_size: address space size
 547   * @fladj: frame length adjustment
 548 + * @incrx_type: INCR burst type adjustment
 549   * @irq_gadget: peripheral controller's IRQ number
 550   * @nr_scratch: number of scratch buffers
 551   * @u1u2: only used on revisions <1.83a for workaround
 552 @@ -834,6 +865,7 @@ struct dwc3_scratchpad_array {
 553   *     1       - -3.5dB de-emphasis
 554   *     2       - No de-emphasis
 555   *     3       - Reserved
 556 + * @disable_devinit_u1u2_quirk: disable device-initiated U1/U2 request.
 557   */
 558  struct dwc3 {
 559         struct usb_ctrlrequest  *ctrl_req;
 560 @@ -852,6 +884,7 @@ struct dwc3 {
 561         spinlock_t              lock;
 562
 563         struct device           *dev;
 564 +       struct device           *sysdev;
 565
 566         struct platform_device  *xhci;
 567         struct resource         xhci_resources[DWC3_XHCI_RESOURCES_NUM];
 568 @@ -877,6 +910,12 @@ struct dwc3 {
 569         enum usb_phy_interface  hsphy_mode;
 570
 571         u32                     fladj;
 572 +       /*
 573 +        * For INCR burst type.
 574 +        * First field: for undefined length INCR burst type enable.
 575 +        * Second field: for INCRx burst type enable
 576 +        */
 577 +       u32                     incrx_type[2];
 578         u32                     irq_gadget;
 579         u32                     nr_scratch;
 580         u32                     u1u2;
 581 @@ -953,9 +992,12 @@ struct dwc3 {
 582         unsigned                ep0_bounced:1;
 583         unsigned                ep0_expect_in:1;
 584         unsigned                has_hibernation:1;
 585 +       unsigned                sysdev_is_parent:1;
 586         unsigned                has_lpm_erratum:1;
 587         unsigned                is_utmi_l1_suspend:1;
 588         unsigned                is_fpga:1;
 589 +       unsigned                needs_fifo_resize:1;
 590 +       unsigned                configure_gfladj:1;
 591         unsigned                pending_events:1;
 592         unsigned                pullups_connected:1;
 593         unsigned                setup_packet_pending:1;
 594 @@ -976,9 +1018,16 @@ struct dwc3 {
 595         unsigned                dis_rxdet_inp3_quirk:1;
 596         unsigned                dis_u2_freeclk_exists_quirk:1;
 597         unsigned                dis_del_phy_power_chg_quirk:1;
 598 +       unsigned                dma_snooping_quirk:1;
 599
 600         unsigned                tx_de_emphasis_quirk:1;
 601         unsigned                tx_de_emphasis:2;
 602 +       unsigned                disable_devinit_u1u2_quirk:1;
 603 +       unsigned                quirk_reverse_in_out:1;
 604 +       unsigned                quirk_stop_transfer_in_block:1;
 605 +       unsigned                quirk_stop_ep_in_u1:1;
 606 +
 607 +       u16                     imod_interval;
 608  };
 609
 610  /* -------------------------------------------------------------------------- */
 611 --- a/drivers/usb/dwc3/ep0.c
 612 +++ b/drivers/usb/dwc3/ep0.c
 613 @@ -360,9 +360,9 @@ static int dwc3_ep0_handle_status(struct
 614                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 615                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 616                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 617 -                       if (reg & DWC3_DCTL_INITU1ENA)
 618 +                       if ((reg & DWC3_DCTL_INITU1ENA) && !dwc->disable_devinit_u1u2_quirk)
 619                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 620 -                       if (reg & DWC3_DCTL_INITU2ENA)
 621 +                       if ((reg & DWC3_DCTL_INITU2ENA) && !dwc->disable_devinit_u1u2_quirk)
 622                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 623                 }
 624
 625 --- a/drivers/usb/dwc3/gadget.c
 626 +++ b/drivers/usb/dwc3/gadget.c
 627 @@ -2928,6 +2928,7 @@ static irqreturn_t dwc3_interrupt(int ir
 628  int dwc3_gadget_init(struct dwc3 *dwc)
 629  {
 630         int ret, irq;
 631 +       u32     reg;
 632         struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
 633
 634         irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
 635 @@ -3042,6 +3043,12 @@ int dwc3_gadget_init(struct dwc3 *dwc)
 636                 goto err5;
 637         }
 638
 639 +       if (dwc->disable_devinit_u1u2_quirk) {
 640 +               reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 641 +               reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
 642 +               dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 643 +       }
 644 +
 645         return 0;
 646
 647  err5:
 648 --- a/drivers/usb/dwc3/host.c
 649 +++ b/drivers/usb/dwc3/host.c
 650 @@ -17,6 +17,8 @@
 651
 652  #include <linux/platform_device.h>
 653
 654 +#include <linux/of_device.h>
 655 +
 656  #include "core.h"
 657
 658  int dwc3_host_init(struct dwc3 *dwc)
 659 @@ -73,12 +75,21 @@ int dwc3_host_init(struct dwc3 *dwc)
 660                 return -ENOMEM;
 661         }
 662
 663 -       dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
 664 +       if (IS_ENABLED(CONFIG_OF) && dwc->dev->of_node)
 665 +               of_dma_configure(&xhci->dev, dwc->dev->of_node);
 666 +       else
 667 +               dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
 668
 669 -       xhci->dev.parent        = dwc->dev;
 670 +       xhci->dev.parent        = dwc->dev;
 671         xhci->dev.dma_mask      = dwc->dev->dma_mask;
 672         xhci->dev.dma_parms     = dwc->dev->dma_parms;
 673
 674 +       /* set DMA operations */
 675 +       if (dwc->dev->of_node && of_dma_is_coherent(dwc->dev->of_node)) {
 676 +               xhci->dev.archdata.dma_ops = dwc->dev->archdata.dma_ops;
 677 +               dev_dbg(dwc->dev, "set dma_ops for usb\n");
 678 +       }
 679 +
 680         dwc->xhci = xhci;
 681
 682         ret = platform_device_add_resources(xhci, dwc->xhci_resources,
 683 @@ -90,6 +101,15 @@ int dwc3_host_init(struct dwc3 *dwc)
 684
 685         memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
 686
 687 +       if (dwc->quirk_reverse_in_out)
 688 +               props[prop_idx++].name = "quirk-reverse-in-out";
 689 +
 690 +       if (dwc->quirk_stop_transfer_in_block)
 691 +               props[prop_idx++].name = "quirk-stop-transfer-in-block";
 692 +
 693 +       if (dwc->quirk_stop_ep_in_u1)
 694 +               props[prop_idx++].name = "quirk-stop-ep-in-u1";
 695 +
 696         if (dwc->usb3_lpm_capable)
 697                 props[prop_idx++].name = "usb3-lpm-capable";
 698
 699 --- a/drivers/usb/gadget/udc/fsl_udc_core.c
 700 +++ b/drivers/usb/gadget/udc/fsl_udc_core.c
 701 @@ -198,7 +198,11 @@ __acquires(ep->udc->lock)
 702
 703         spin_unlock(&ep->udc->lock);
 704
 705 -       usb_gadget_giveback_request(&ep->ep, &req->req);
 706 +       /* this complete() should a func implemented by gadget layer,
 707 +        * eg fsg->bulk_in_complete()
 708 +        */
 709 +       if (req->req.complete)
 710 +               usb_gadget_giveback_request(&ep->ep, &req->req);
 711
 712         spin_lock(&ep->udc->lock);
 713         ep->stopped = stopped;
 714 @@ -245,10 +249,10 @@ static int dr_controller_setup(struct fs
 715                 if (udc->pdata->have_sysif_regs) {
 716                         if (udc->pdata->controller_ver) {
 717                                 /* controller version 1.6 or above */
 718 -                               ctrl = __raw_readl(&usb_sys_regs->control);
 719 +                               ctrl = ioread32be(&usb_sys_regs->control);
 720                                 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
 721                                 ctrl |= USB_CTRL_USB_EN;
 722 -                               __raw_writel(ctrl, &usb_sys_regs->control);
 723 +                               iowrite32be(ctrl, &usb_sys_regs->control);
 724                         }
 725                 }
 726                 portctrl |= PORTSCX_PTS_ULPI;
 727 @@ -257,13 +261,14 @@ static int dr_controller_setup(struct fs
 728                 portctrl |= PORTSCX_PTW_16BIT;
 729                 /* fall through */
 730         case FSL_USB2_PHY_UTMI:
 731 +       case FSL_USB2_PHY_UTMI_DUAL:
 732                 if (udc->pdata->have_sysif_regs) {
 733                         if (udc->pdata->controller_ver) {
 734                                 /* controller version 1.6 or above */
 735 -                               ctrl = __raw_readl(&usb_sys_regs->control);
 736 +                               ctrl = ioread32be(&usb_sys_regs->control);
 737                                 ctrl |= (USB_CTRL_UTMI_PHY_EN |
 738                                         USB_CTRL_USB_EN);
 739 -                               __raw_writel(ctrl, &usb_sys_regs->control);
 740 +                               iowrite32be(ctrl, &usb_sys_regs->control);
 741                                 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
 742                                         PHY CLK to become stable - 10ms*/
 743                         }
 744 @@ -329,22 +334,22 @@ static int dr_controller_setup(struct fs
 745         /* Config control enable i/o output, cpu endian register */
 746  #ifndef CONFIG_ARCH_MXC
 747         if (udc->pdata->have_sysif_regs) {
 748 -               ctrl = __raw_readl(&usb_sys_regs->control);
 749 +               ctrl = ioread32be(&usb_sys_regs->control);
 750                 ctrl |= USB_CTRL_IOENB;
 751 -               __raw_writel(ctrl, &usb_sys_regs->control);
 752 +               iowrite32be(ctrl, &usb_sys_regs->control);
 753         }
 754  #endif
 755
 756 -#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
 757 +#if !defined(CONFIG_NOT_COHERENT_CACHE)
 758         /* Turn on cache snooping hardware, since some PowerPC platforms
 759          * wholly rely on hardware to deal with cache coherent. */
 760
 761         if (udc->pdata->have_sysif_regs) {
 762                 /* Setup Snooping for all the 4GB space */
 763                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
 764 -               __raw_writel(tmp, &usb_sys_regs->snoop1);
 765 +               iowrite32be(tmp, &usb_sys_regs->snoop1);
 766                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
 767 -               __raw_writel(tmp, &usb_sys_regs->snoop2);
 768 +               iowrite32be(tmp, &usb_sys_regs->snoop2);
 769         }
 770  #endif
 771
 772 @@ -1057,7 +1062,7 @@ static int fsl_ep_fifo_status(struct usb
 773         struct ep_queue_head *qh;
 774
 775         ep = container_of(_ep, struct fsl_ep, ep);
 776 -       if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
 777 +       if (!_ep || !ep->ep.desc || (ep_index(ep) == 0))
 778                 return -ENODEV;
 779
 780         udc = (struct fsl_udc *)ep->udc;
 781 @@ -1599,14 +1604,13 @@ static int process_ep_req(struct fsl_udc
 782                 struct fsl_req *curr_req)
 783  {
 784         struct ep_td_struct *curr_td;
 785 -       int     td_complete, actual, remaining_length, j, tmp;
 786 +       int     actual, remaining_length, j, tmp;
 787         int     status = 0;
 788         int     errors = 0;
 789         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
 790         int direction = pipe % 2;
 791
 792         curr_td = curr_req->head;
 793 -       td_complete = 0;
 794         actual = curr_req->req.length;
 795
 796         for (j = 0; j < curr_req->dtd_count; j++) {
 797 @@ -1651,11 +1655,9 @@ static int process_ep_req(struct fsl_udc
 798                                 status = -EPROTO;
 799                                 break;
 800                         } else {
 801 -                               td_complete++;
 802                                 break;
 803                         }
 804                 } else {
 805 -                       td_complete++;
 806                         VDBG("dTD transmitted successful");
 807                 }
 808
 809 @@ -1698,7 +1700,7 @@ static void dtd_complete_irq(struct fsl_
 810                 curr_ep = get_ep_by_pipe(udc, i);
 811
 812                 /* If the ep is configured */
 813 -               if (!curr_ep->ep.name) {
 814 +               if (strncmp(curr_ep->name, "ep", 2)) {
 815                         WARNING("Invalid EP?");
 816                         continue;
 817                 }
 818 @@ -2420,10 +2422,12 @@ static int fsl_udc_probe(struct platform
 819                 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
 820  #endif
 821
 822 +#ifdef CONFIG_ARCH_MXC
 823         /* Initialize USB clocks */
 824         ret = fsl_udc_clk_init(pdev);
 825         if (ret < 0)
 826                 goto err_iounmap_noclk;
 827 +#endif
 828
 829         /* Read Device Controller Capability Parameters register */
 830         dccparams = fsl_readl(&dr_regs->dccparams);
 831 @@ -2463,9 +2467,11 @@ static int fsl_udc_probe(struct platform
 832                 dr_controller_setup(udc_controller);
 833         }
 834
 835 +#ifdef CONFIG_ARCH_MXC
 836         ret = fsl_udc_clk_finalize(pdev);
 837         if (ret)
 838                 goto err_free_irq;
 839 +#endif
 840
 841         /* Setup gadget structure */
 842         udc_controller->gadget.ops = &fsl_gadget_ops;
 843 @@ -2478,6 +2484,7 @@ static int fsl_udc_probe(struct platform
 844         /* Setup gadget.dev and register with kernel */
 845         dev_set_name(&udc_controller->gadget.dev, "gadget");
 846         udc_controller->gadget.dev.of_node = pdev->dev.of_node;
 847 +       set_dma_ops(&udc_controller->gadget.dev, pdev->dev.archdata.dma_ops);
 848
 849         if (!IS_ERR_OR_NULL(udc_controller->transceiver))
 850                 udc_controller->gadget.is_otg = 1;
 851 @@ -2529,7 +2536,9 @@ err_free_irq:
 852  err_iounmap:
 853         if (pdata->exit)
 854                 pdata->exit(pdev);
 855 +#ifdef CONFIG_ARCH_MXC
 856         fsl_udc_clk_release();
 857 +#endif
 858  err_iounmap_noclk:
 859         iounmap(dr_regs);
 860  err_release_mem_region:
 861 @@ -2557,8 +2566,9 @@ static int fsl_udc_remove(struct platfor
 862         udc_controller->done = &done;
 863         usb_del_gadget_udc(&udc_controller->gadget);
 864
 865 +#ifdef CONFIG_ARCH_MXC
 866         fsl_udc_clk_release();
 867 -
 868 +#endif
 869         /* DR has been stopped in usb_gadget_unregister_driver() */
 870         remove_proc_file();
 871
 872 --- a/drivers/usb/gadget/udc/fsl_usb2_udc.h
 873 +++ b/drivers/usb/gadget/udc/fsl_usb2_udc.h
 874 @@ -20,6 +20,10 @@
 875  #define USB_MAX_CTRL_PAYLOAD           64
 876  #define USB_DR_SYS_OFFSET              0x400
 877
 878 +#ifdef CONFIG_SOC_LS1021A
 879 +#undef CONFIG_ARCH_MXC
 880 +#endif
 881 +
 882   /* USB DR device mode registers (Little Endian) */
 883  struct usb_dr_device {
 884         /* Capability register */
 885 @@ -597,18 +601,6 @@ struct platform_device;
 886  int fsl_udc_clk_init(struct platform_device *pdev);
 887  int fsl_udc_clk_finalize(struct platform_device *pdev);
 888  void fsl_udc_clk_release(void);
 889 -#else
 890 -static inline int fsl_udc_clk_init(struct platform_device *pdev)
 891 -{
 892 -       return 0;
 893 -}
 894 -static inline int fsl_udc_clk_finalize(struct platform_device *pdev)
 895 -{
 896 -       return 0;
 897 -}
 898 -static inline void fsl_udc_clk_release(void)
 899 -{
 900 -}
 901  #endif
 902
 903  #endif
 904 --- a/drivers/usb/host/Kconfig
 905 +++ b/drivers/usb/host/Kconfig
 906 @@ -165,7 +165,7 @@ config XPS_USB_HCD_XILINX
 907
 908  config USB_EHCI_FSL
 909         tristate "Support for Freescale PPC on-chip EHCI USB controller"
 910 -       depends on FSL_SOC
 911 +       depends on USB_EHCI_HCD
 912         select USB_EHCI_ROOT_HUB_TT
 913         ---help---
 914           Variation of ARC USB block used in some Freescale chips.
 915 --- a/drivers/usb/host/ehci-fsl.c
 916 +++ b/drivers/usb/host/ehci-fsl.c
 917 @@ -36,15 +36,127 @@
 918  #include <linux/platform_device.h>
 919  #include <linux/fsl_devices.h>
 920  #include <linux/of_platform.h>
 921 +#include <linux/io.h>
 922 +
 923 +#ifdef CONFIG_PPC
 924 +#include <asm/fsl_pm.h>
 925 +#include <linux/suspend.h>
 926 +#endif
 927
 928  #include "ehci.h"
 929  #include "ehci-fsl.h"
 930
 931 +#define FSL_USB_PHY_ADDR       0xffe214000
 932 +
 933 +struct ccsr_usb_port_ctrl {
 934 +       u32     ctrl;
 935 +       u32     drvvbuscfg;
 936 +       u32     pwrfltcfg;
 937 +       u32     sts;
 938 +       u8      res_14[0xc];
 939 +       u32     bistcfg;
 940 +       u32     biststs;
 941 +       u32     abistcfg;
 942 +       u32     abiststs;
 943 +       u8      res_30[0x10];
 944 +       u32     xcvrprg;
 945 +       u32     anaprg;
 946 +       u32     anadrv;
 947 +       u32     anasts;
 948 +};
 949 +
 950 +struct ccsr_usb_phy {
 951 +       u32     id;
 952 +       struct ccsr_usb_port_ctrl port1;
 953 +       u8      res_50[0xc];
 954 +       u32     tvr;
 955 +       u32     pllprg[4];
 956 +       u8      res_70[0x4];
 957 +       u32     anaccfg;
 958 +       u32     dbg;
 959 +       u8      res_7c[0x4];
 960 +       struct ccsr_usb_port_ctrl port2;
 961 +       u8      res_dc[0x334];
 962 +};
 963 +
 964  #define DRIVER_DESC "Freescale EHCI Host controller driver"
 965  #define DRV_NAME "ehci-fsl"
 966
 967  static struct hc_driver __read_mostly fsl_ehci_hc_driver;
 968
 969 +struct ehci_fsl {
 970 +       struct ehci_hcd ehci;
 971 +
 972 +#ifdef CONFIG_PM
 973 +struct ehci_regs saved_regs;
 974 +struct ccsr_usb_phy saved_phy_regs;
 975 +/* Saved USB PHY settings, need to restore after deep sleep. */
 976 +u32 usb_ctrl;
 977 +#endif
 978 +       /*
 979 +        * store current hcd state for otg;
 980 +        * have_hcd is true when host drv al already part of otg framework,
 981 +        * otherwise false;
 982 +        * hcd_add is true when otg framework wants to add host
 983 +        * drv as part of otg;flase when it wants to remove it
 984 +        */
 985 +unsigned have_hcd:1;
 986 +unsigned hcd_add:1;
 987 +};
 988 +
 989 +static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
 990 +{
 991 +struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 992 +
 993 +return container_of(ehci, struct ehci_fsl, ehci);
 994 +}
 995 +
 996 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
 997 +static void do_change_hcd(struct work_struct *work)
 998 +{
 999 +struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
1000 +                                    change_hcd_work);
1001 +struct usb_hcd *hcd = ehci_to_hcd(ehci);
1002 +struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1003 +void __iomem *non_ehci = hcd->regs;
1004 +int retval;
1005 +
1006 +       if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
1007 +       writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
1008 +       /* host, gadget and otg share same int line */
1009 +       retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
1010 +       if (retval == 0)
1011 +               ehci_fsl->have_hcd = 1;
1012 +       } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
1013 +               usb_remove_hcd(hcd);
1014 +               ehci_fsl->have_hcd = 0;
1015 +       }
1016 +}
1017 +#endif
1018 +
1019 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1020 +static void do_change_hcd(struct work_struct *work)
1021 +{
1022 +       struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
1023 +                       change_hcd_work);
1024 +       struct usb_hcd *hcd = ehci_to_hcd(ehci);
1025 +       struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1026 +       void __iomem *non_ehci = hcd->regs;
1027 +       int retval;
1028 +
1029 +       if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
1030 +               writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
1031 +               /* host, gadget and otg share same int line */
1032 +               retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
1033 +               if (retval == 0)
1034 +                       ehci_fsl->have_hcd = 1;
1035 +       } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
1036 +               usb_remove_hcd(hcd);
1037 +               ehci_fsl->have_hcd = 0;
1038 +       }
1039 +}
1040 +#endif
1041 +
1042  /* configure so an HC device and id are always provided */
1043  /* always called with process context; sleeping is OK */
1044
1045 @@ -131,6 +243,12 @@ static int fsl_ehci_drv_probe(struct pla
1046                 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
1047                                 CONTROL_REGISTER_W1C_MASK, 0x4);
1048
1049 +       /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
1050 +       if (pdata->controller_ver == FSL_USB_VER_2_5 &&
1051 +               pdata->phy_mode == FSL_USB2_PHY_ULPI)
1052 +               iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
1053 +
1054 +
1055         /*
1056          * Enable UTMI phy and program PTS field in UTMI mode before asserting
1057          * controller reset for USB Controller version 2.5
1058 @@ -143,16 +261,20 @@ static int fsl_ehci_drv_probe(struct pla
1059
1060         /* Don't need to set host mode here. It will be done by tdi_reset() */
1061
1062 -       retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
1063 +       retval = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_NO_SUSPEND);
1064         if (retval != 0)
1065                 goto err2;
1066         device_wakeup_enable(hcd->self.controller);
1067
1068 -#ifdef CONFIG_USB_OTG
1069 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1070         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
1071                 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1072 +               struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1073
1074                 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
1075 +
1076 +               INIT_WORK(&ehci->change_hcd_work, do_change_hcd);
1077 +
1078                 dev_dbg(&pdev->dev, "hcd=0x%p  ehci=0x%p, phy=0x%p\n",
1079                         hcd, ehci, hcd->usb_phy);
1080
1081 @@ -168,6 +290,11 @@ static int fsl_ehci_drv_probe(struct pla
1082                         retval = -ENODEV;
1083                         goto err2;
1084                 }
1085 +
1086 +               ehci_fsl->have_hcd = 1;
1087 +       } else {
1088 +               dev_err(&pdev->dev, "wrong operating mode\n");
1089 +               return -ENODEV;
1090         }
1091  #endif
1092         return retval;
1093 @@ -181,6 +308,17 @@ static int fsl_ehci_drv_probe(struct pla
1094         return retval;
1095  }
1096
1097 +static bool usb_phy_clk_valid(struct usb_hcd *hcd)
1098 +{
1099 +       void __iomem *non_ehci = hcd->regs;
1100 +       bool ret = true;
1101 +
1102 +       if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
1103 +               ret = false;
1104 +
1105 +       return ret;
1106 +}
1107 +
1108  static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
1109                                enum fsl_usb2_phy_modes phy_mode,
1110                                unsigned int port_offset)
1111 @@ -219,6 +357,21 @@ static int ehci_fsl_setup_phy(struct usb
1112                 /* fall through */
1113         case FSL_USB2_PHY_UTMI:
1114         case FSL_USB2_PHY_UTMI_DUAL:
1115 +               if (pdata->has_fsl_erratum_a006918) {
1116 +                       pr_warn("fsl-ehci: USB PHY clock invalid\n");
1117 +                       return -EINVAL;
1118 +               }
1119 +
1120 +               /* PHY_CLK_VALID bit is de-featured from all controller
1121 +                * versions below 2.4 and is to be checked only for
1122 +                * internal UTMI phy
1123 +                */
1124 +               if (pdata->controller_ver > FSL_USB_VER_2_4 &&
1125 +                       pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
1126 +                       pr_err("fsl-ehci: USB PHY clock invalid\n");
1127 +                       return -EINVAL;
1128 +               }
1129 +
1130                 if (pdata->have_sysif_regs && pdata->controller_ver) {
1131                         /* controller version 1.6 or above */
1132                         clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
1133 @@ -286,20 +439,18 @@ static int ehci_fsl_usb_setup(struct ehc
1134         if (pdata->has_fsl_erratum_a005275 == 1)
1135                 ehci->has_fsl_hs_errata = 1;
1136
1137 +       if (pdata->has_fsl_erratum_a005697 == 1)
1138 +               ehci->has_fsl_susp_errata = 1;
1139 +
1140         if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
1141                         (pdata->operating_mode == FSL_USB2_DR_OTG))
1142                 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
1143                         return -EINVAL;
1144
1145         if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
1146 -               unsigned int chip, rev, svr;
1147 -
1148 -               svr = mfspr(SPRN_SVR);
1149 -               chip = svr >> 16;
1150 -               rev = (svr >> 4) & 0xf;
1151
1152                 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
1153 -               if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
1154 +               if (pdata->has_fsl_erratum_14 == 1)
1155                         ehci->has_fsl_port_bug = 1;
1156
1157                 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
1158 @@ -379,16 +530,57 @@ static int ehci_fsl_setup(struct usb_hcd
1159         return retval;
1160  }
1161
1162 -struct ehci_fsl {
1163 -       struct ehci_hcd ehci;
1164
1165  #ifdef CONFIG_PM
1166 -       /* Saved USB PHY settings, need to restore after deep sleep. */
1167 -       u32 usb_ctrl;
1168 -#endif
1169 -};
1170 +void __iomem *phy_reg;
1171
1172 -#ifdef CONFIG_PM
1173 +#ifdef CONFIG_PPC
1174 +/* save usb registers */
1175 +static int ehci_fsl_save_context(struct usb_hcd *hcd)
1176 +{
1177 +       struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1178 +       struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1179 +       void __iomem *non_ehci = hcd->regs;
1180 +       struct device *dev = hcd->self.controller;
1181 +       struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1182 +
1183 +       if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1184 +       phy_reg = ioremap(FSL_USB_PHY_ADDR,
1185 +                       sizeof(struct ccsr_usb_phy));
1186 +       _memcpy_fromio((void *)&ehci_fsl->saved_phy_regs, phy_reg,
1187 +       sizeof(struct ccsr_usb_phy));
1188 +       }
1189 +
1190 +       _memcpy_fromio((void *)&ehci_fsl->saved_regs, ehci->regs,
1191 +                                       sizeof(struct ehci_regs));
1192 +       ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
1193 +
1194 +       return 0;
1195 +}
1196 +
1197 +/*Restore usb registers */
1198 +static int ehci_fsl_restore_context(struct usb_hcd *hcd)
1199 +{
1200 +       struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1201 +       struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1202 +       void __iomem *non_ehci = hcd->regs;
1203 +       struct device *dev = hcd->self.controller;
1204 +       struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1205 +
1206 +       if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1207 +               if (phy_reg)
1208 +                       _memcpy_toio(phy_reg,
1209 +                               (void *)&ehci_fsl->saved_phy_regs,
1210 +                               sizeof(struct ccsr_usb_phy));
1211 +       }
1212 +
1213 +       _memcpy_toio(ehci->regs, (void *)&ehci_fsl->saved_regs,
1214 +                               sizeof(struct ehci_regs));
1215 +       iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
1216 +
1217 +       return 0;
1218 +}
1219 +#endif
1220
1221  #ifdef CONFIG_PPC_MPC512x
1222  static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
1223 @@ -535,26 +727,45 @@ static inline int ehci_fsl_mpc512x_drv_r
1224  }
1225  #endif /* CONFIG_PPC_MPC512x */
1226
1227 -static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
1228 -{
1229 -       struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1230 -
1231 -       return container_of(ehci, struct ehci_fsl, ehci);
1232 -}
1233 -
1234  static int ehci_fsl_drv_suspend(struct device *dev)
1235  {
1236         struct usb_hcd *hcd = dev_get_drvdata(dev);
1237         struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1238         void __iomem *non_ehci = hcd->regs;
1239 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1240 +       struct usb_bus host = hcd->self;
1241 +#endif
1242 +
1243 +#ifdef CONFIG_PPC
1244 +suspend_state_t pm_state;
1245 +/* FIXME:Need to port fsl_pm.h before enable below code. */
1246 +/*pm_state = pm_suspend_state();*/
1247 +pm_state = PM_SUSPEND_MEM;
1248 +
1249 +if (pm_state == PM_SUSPEND_MEM)
1250 +       ehci_fsl_save_context(hcd);
1251 +#endif
1252
1253         if (of_device_is_compatible(dev->parent->of_node,
1254                                     "fsl,mpc5121-usb2-dr")) {
1255                 return ehci_fsl_mpc512x_drv_suspend(dev);
1256         }
1257
1258 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1259 +       if (host.is_otg) {
1260 +               struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1261 +
1262 +               /* remove hcd */
1263 +               ehci_fsl->hcd_add = 0;
1264 +               schedule_work(&ehci->change_hcd_work);
1265 +               host.is_otg = 0;
1266 +               return 0;
1267 +       }
1268 +#endif
1269 +
1270         ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
1271                         device_may_wakeup(dev));
1272 +
1273         if (!fsl_deep_sleep())
1274                 return 0;
1275
1276 @@ -568,12 +779,36 @@ static int ehci_fsl_drv_resume(struct de
1277         struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1278         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1279         void __iomem *non_ehci = hcd->regs;
1280 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1281 +       struct usb_bus host = hcd->self;
1282 +#endif
1283 +
1284 +#ifdef CONFIG_PPC
1285 +suspend_state_t pm_state;
1286 +/* FIXME:Need to port fsl_pm.h before enable below code.*/
1287 +/* pm_state = pm_suspend_state(); */
1288 +pm_state = PM_SUSPEND_MEM;
1289 +
1290 +if (pm_state == PM_SUSPEND_MEM)
1291 +       ehci_fsl_restore_context(hcd);
1292 +#endif
1293
1294         if (of_device_is_compatible(dev->parent->of_node,
1295                                     "fsl,mpc5121-usb2-dr")) {
1296                 return ehci_fsl_mpc512x_drv_resume(dev);
1297         }
1298
1299 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1300 +       if (host.is_otg) {
1301 +               /* add hcd */
1302 +               ehci_fsl->hcd_add = 1;
1303 +               schedule_work(&ehci->change_hcd_work);
1304 +               usb_hcd_resume_root_hub(hcd);
1305 +               host.is_otg = 0;
1306 +               return 0;
1307 +       }
1308 +#endif
1309 +
1310         ehci_prepare_ports_for_controller_resume(ehci);
1311         if (!fsl_deep_sleep())
1312                 return 0;
1313 --- a/drivers/usb/host/ehci-fsl.h
1314 +++ b/drivers/usb/host/ehci-fsl.h
1315 @@ -63,4 +63,7 @@
1316  #define UTMI_PHY_EN             (1<<9)
1317  #define ULPI_PHY_CLK_SEL        (1<<10)
1318  #define PHY_CLK_VALID          (1<<17)
1319 +
1320 +/* Retry count for checking UTMI PHY CLK validity */
1321 +#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
1322  #endif                         /* _EHCI_FSL_H */
1323 --- a/drivers/usb/host/ehci-hub.c
1324 +++ b/drivers/usb/host/ehci-hub.c
1325 @@ -278,6 +278,8 @@ static int ehci_bus_suspend (struct usb_
1326                 else if ((t1 & PORT_PE) && !(t1 & PORT_SUSPEND)) {
1327                         t2 |= PORT_SUSPEND;
1328                         set_bit(port, &ehci->bus_suspended);
1329 +                       if (ehci_has_fsl_susp_errata(ehci))
1330 +                               usleep_range(10000, 20000);
1331                 }
1332
1333                 /* enable remote wakeup on all ports, if told to do so */
1334 @@ -305,6 +307,8 @@ static int ehci_bus_suspend (struct usb_
1335                                                 USB_PORT_STAT_HIGH_SPEED)
1336                                 fs_idle_delay = true;
1337                         ehci_writel(ehci, t2, reg);
1338 +                       if (ehci_has_fsl_susp_errata(ehci))
1339 +                               usleep_range(10000, 20000);
1340                         changed = 1;
1341                 }
1342         }
1343 --- a/drivers/usb/host/ehci.h
1344 +++ b/drivers/usb/host/ehci.h
1345 @@ -180,6 +180,9 @@ struct ehci_hcd {                   /* one per controlle
1346         unsigned                periodic_count; /* periodic activity count */
1347         unsigned                uframe_periodic_max; /* max periodic time per uframe */
1348
1349 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1350 +       struct work_struct change_hcd_work;
1351 +#endif
1352
1353         /* list of itds & sitds completed while now_frame was still active */
1354         struct list_head        cached_itd_list;
1355 @@ -219,6 +222,7 @@ struct ehci_hcd {                   /* one per controlle
1356         unsigned                no_selective_suspend:1;
1357         unsigned                has_fsl_port_bug:1; /* FreeScale */
1358         unsigned                has_fsl_hs_errata:1;    /* Freescale HS quirk */
1359 +       unsigned                has_fsl_susp_errata:1; /*Freescale SUSP quirk*/
1360         unsigned                big_endian_mmio:1;
1361         unsigned                big_endian_desc:1;
1362         unsigned                big_endian_capbase:1;
1363 @@ -704,10 +708,15 @@ ehci_port_speed(struct ehci_hcd *ehci, u
1364  #if defined(CONFIG_PPC_85xx)
1365  /* Some Freescale processors have an erratum (USB A-005275) in which
1366   * incoming packets get corrupted in HS mode
1367 + * Some Freescale processors have an erratum (USB A-005697) in which
1368 + * we need to wait for 10ms for bus to fo into suspend mode after
1369 + * setting SUSP bit
1370   */
1371  #define ehci_has_fsl_hs_errata(e)      ((e)->has_fsl_hs_errata)
1372 +#define ehci_has_fsl_susp_errata(e)     ((e)->has_fsl_susp_errata)
1373  #else
1374  #define ehci_has_fsl_hs_errata(e)      (0)
1375 +#define ehci_has_fsl_susp_errata(e)     (0)
1376  #endif
1377
1378  /*
1379 --- a/drivers/usb/host/fsl-mph-dr-of.c
1380 +++ b/drivers/usb/host/fsl-mph-dr-of.c
1381 @@ -226,6 +226,18 @@ static int fsl_usb2_mph_dr_of_probe(stru
1382                 of_property_read_bool(np, "fsl,usb-erratum-a007792");
1383         pdata->has_fsl_erratum_a005275 =
1384                 of_property_read_bool(np, "fsl,usb-erratum-a005275");
1385 +       pdata->has_fsl_erratum_a005697 =
1386 +               of_property_read_bool(np, "fsl,usb_erratum-a005697");
1387 +       if (of_get_property(np, "fsl,erratum_a006918", NULL))
1388 +               pdata->has_fsl_erratum_a006918 = 1;
1389 +       else
1390 +               pdata->has_fsl_erratum_a006918 = 0;
1391 +
1392 +       if (of_get_property(np, "fsl,usb_erratum_14", NULL))
1393 +               pdata->has_fsl_erratum_14 = 1;
1394 +       else
1395 +               pdata->has_fsl_erratum_14 = 0;
1396 +
1397
1398         /*
1399          * Determine whether phy_clk_valid needs to be checked
1400 --- a/drivers/usb/host/xhci-plat.c
1401 +++ b/drivers/usb/host/xhci-plat.c
1402 @@ -223,6 +223,16 @@ static int xhci_plat_probe(struct platfo
1403         if (device_property_read_bool(&pdev->dev, "usb3-lpm-capable"))
1404                 xhci->quirks |= XHCI_LPM_SUPPORT;
1405
1406 +       if (device_property_read_bool(&pdev->dev, "quirk-reverse-in-out"))
1407 +               xhci->quirks |= XHCI_REVERSE_IN_OUT;
1408 +
1409 +       if (device_property_read_bool(&pdev->dev,
1410 +                               "quirk-stop-transfer-in-block"))
1411 +               xhci->quirks |= XHCI_STOP_TRANSFER_IN_BLOCK;
1412 +
1413 +       if (device_property_read_bool(&pdev->dev, "quirk-stop-ep-in-u1"))
1414 +               xhci->quirks |= XHCI_STOP_EP_IN_U1;
1415 +
1416         if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
1417                 xhci->quirks |= XHCI_BROKEN_PORT_PED;
1418
1419 --- a/drivers/usb/host/xhci-ring.c
1420 +++ b/drivers/usb/host/xhci-ring.c
1421 @@ -1859,14 +1859,17 @@ static int finish_td(struct xhci_hcd *xh
1422         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1423         struct xhci_virt_ep *ep, int *status, bool skip)
1424  {
1425 +       struct xhci_dequeue_state deq_state;
1426         struct xhci_virt_device *xdev;
1427         struct xhci_ring *ep_ring;
1428 +       unsigned int stream_id;
1429         unsigned int slot_id;
1430         int ep_index;
1431         struct urb *urb = NULL;
1432         struct xhci_ep_ctx *ep_ctx;
1433         int ret = 0;
1434         struct urb_priv *urb_priv;
1435 +       u32 remaining;
1436         u32 trb_comp_code;
1437
1438         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1439 @@ -1892,13 +1895,29 @@ static int finish_td(struct xhci_hcd *xh
1440         if (trb_comp_code == COMP_STALL ||
1441                 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1442                                                 trb_comp_code)) {
1443 -               /* Issue a reset endpoint command to clear the host side
1444 -                * halt, followed by a set dequeue command to move the
1445 -                * dequeue pointer past the TD.
1446 -                * The class driver clears the device side halt later.
1447 +               /*
1448 +                * A-007463: After transaction error, controller switches
1449 +                * control transfer data stage from IN to OUT direction.
1450                  */
1451 -               xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1452 +               remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1453 +               if (remaining && xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1454 +                                       trb_comp_code) &&
1455 +                                       (xhci->quirks & XHCI_REVERSE_IN_OUT)) {
1456 +                       memset(&deq_state, 0, sizeof(deq_state));
1457 +                       xhci_find_new_dequeue_state(xhci, slot_id,
1458 +                               ep_index, td->urb->stream_id, td, &deq_state);
1459 +                       xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
1460 +                                                       stream_id, &deq_state);
1461 +                       xhci_ring_cmd_db(xhci);
1462 +               } else {
1463 +                       /* Issue a reset endpoint command to clear the host side
1464 +                        * halt, followed by a set dequeue command to move the
1465 +                        * dequeue pointer past the TD.
1466 +                        * The class driver clears the device side halt later.
1467 +                        */
1468 +                       xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1469                                         ep_ring->stream_id, td, event_trb);
1470 +               }
1471         } else {
1472                 /* Update ring dequeue pointer */
1473                 while (ep_ring->dequeue != td->last_trb)
1474 --- a/drivers/usb/host/xhci.c
1475 +++ b/drivers/usb/host/xhci.c
1476 @@ -1619,14 +1619,38 @@ int xhci_urb_dequeue(struct usb_hcd *hcd
1477                         ret = -ENOMEM;
1478                         goto done;
1479                 }
1480 -               ep->ep_state |= EP_HALT_PENDING;
1481 -               ep->stop_cmds_pending++;
1482 -               ep->stop_cmd_timer.expires = jiffies +
1483 +               /*
1484 +                *A-009611: Issuing an End Transfer command on an IN endpoint.
1485 +                *when a transfer is in progress on USB blocks the transmission
1486 +                *Workaround: Software must wait for all existing TRBs to
1487 +                *complete before issuing End transfer command.
1488 +                */
1489 +               if ((ep_ring->enqueue == ep_ring->dequeue &&
1490 +                               (xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) ||
1491 +                               !(xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) {
1492 +                       ep->ep_state |= EP_HALT_PENDING;
1493 +                       ep->stop_cmds_pending++;
1494 +                       ep->stop_cmd_timer.expires = jiffies +
1495                         XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1496 -               add_timer(&ep->stop_cmd_timer);
1497 -               xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1498 -                                        ep_index, 0);
1499 -               xhci_ring_cmd_db(xhci);
1500 +                       add_timer(&ep->stop_cmd_timer);
1501 +                       xhci_queue_stop_endpoint(xhci, command,
1502 +                                       urb->dev->slot_id,
1503 +                                       ep_index, 0);
1504 +                       xhci_ring_cmd_db(xhci);
1505 +               }
1506 +
1507 +               /*
1508 +                *A-009668: Stop Endpoint Command does not complete.
1509 +                *Workaround: Instead of issuing a Stop Endpoint Command,
1510 +                *issue a Disable Slot Command with the corresponding slot ID.
1511 +                *Alternately, you can issue an Address Device Command with
1512 +                *BSR=1
1513 +                */
1514 +               if ((urb->dev->speed <= USB_SPEED_HIGH) &&
1515 +                                       (xhci->quirks & XHCI_STOP_EP_IN_U1)) {
1516 +                       xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
1517 +                                       urb->dev->slot_id);
1518 +               }
1519         }
1520  done:
1521         spin_unlock_irqrestore(&xhci->lock, flags);
1522 --- a/drivers/usb/host/xhci.h
1523 +++ b/drivers/usb/host/xhci.h
1524 @@ -1626,7 +1626,7 @@ struct xhci_hcd {
1525  #define XHCI_STATE_REMOVING    (1 << 2)
1526         /* Statistics */
1527         int                     error_bitmask;
1528 -       unsigned int            quirks;
1529 +       u64                     quirks;
1530  #define        XHCI_LINK_TRB_QUIRK     (1 << 0)
1531  #define XHCI_RESET_EP_QUIRK    (1 << 1)
1532  #define XHCI_NEC_HOST          (1 << 2)
1533 @@ -1662,6 +1662,9 @@ struct xhci_hcd {
1534  #define XHCI_SSIC_PORT_UNUSED  (1 << 22)
1535  #define XHCI_NO_64BIT_SUPPORT  (1 << 23)
1536  #define XHCI_MISSING_CAS       (1 << 24)
1537 +#define XHCI_REVERSE_IN_OUT    (1 << 29)
1538 +#define XHCI_STOP_TRANSFER_IN_BLOCK    (1 << 30)
1539 +#define XHCI_STOP_EP_IN_U1    (1 << 31)
1540  /* For controller with a broken Port Disable implementation */
1541  #define XHCI_BROKEN_PORT_PED   (1 << 25)
1542  #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26)
1543 --- a/drivers/usb/phy/phy-fsl-usb.c
1544 +++ b/drivers/usb/phy/phy-fsl-usb.c
1545 @@ -1,5 +1,5 @@
1546  /*
1547 - * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
1548 + * Copyright 2007,2008 Freescale Semiconductor, Inc.
1549   *
1550   * Author: Li Yang <LeoLi@freescale.com>
1551   *         Jerry Huang <Chang-Ming.Huang@freescale.com>
1552 @@ -463,6 +463,7 @@ void otg_reset_controller(void)
1553  int fsl_otg_start_host(struct otg_fsm *fsm, int on)
1554  {
1555         struct usb_otg *otg = fsm->otg;
1556 +       struct usb_bus *host = otg->host;
1557         struct device *dev;
1558         struct fsl_otg *otg_dev =
1559                 container_of(otg->usb_phy, struct fsl_otg, phy);
1560 @@ -486,6 +487,7 @@ int fsl_otg_start_host(struct otg_fsm *f
1561                         otg_reset_controller();
1562                         VDBG("host on......\n");
1563                         if (dev->driver->pm && dev->driver->pm->resume) {
1564 +                               host->is_otg = 1;
1565                                 retval = dev->driver->pm->resume(dev);
1566                                 if (fsm->id) {
1567                                         /* default-b */
1568 @@ -510,8 +512,11 @@ int fsl_otg_start_host(struct otg_fsm *f
1569                 else {
1570                         VDBG("host off......\n");
1571                         if (dev && dev->driver) {
1572 -                               if (dev->driver->pm && dev->driver->pm->suspend)
1573 +                               if (dev->driver->pm &&
1574 +                                               dev->driver->pm->suspend) {
1575 +                                       host->is_otg = 1;
1576                                         retval = dev->driver->pm->suspend(dev);
1577 +                               }
1578                                 if (fsm->id)
1579                                         /* default-b */
1580                                         fsl_otg_drv_vbus(fsm, 0);
1581 @@ -539,8 +544,17 @@ int fsl_otg_start_gadget(struct otg_fsm
1582         dev = otg->gadget->dev.parent;
1583
1584         if (on) {
1585 -               if (dev->driver->resume)
1586 +               /* Delay gadget resume to synchronize between host and gadget
1587 +                * drivers. Upon role-reversal host drv is shutdown by kernel
1588 +                * worker thread. By the time host drv shuts down, controller
1589 +                * gets programmed for gadget role. Shutting host drv after
1590 +                * this results in controller getting reset, and it stops
1591 +                * responding to otg events
1592 +                */
1593 +               if (dev->driver->resume) {
1594 +                       msleep(1000);
1595                         dev->driver->resume(dev);
1596 +               }
1597         } else {
1598                 if (dev->driver->suspend)
1599                         dev->driver->suspend(dev, otg_suspend_state);
1600 @@ -672,6 +686,10 @@ static void fsl_otg_event(struct work_st
1601                 fsl_otg_start_host(fsm, 0);
1602                 otg_drv_vbus(fsm, 0);
1603                 fsl_otg_start_gadget(fsm, 1);
1604 +       } else {
1605 +               fsl_otg_start_gadget(fsm, 0);
1606 +               otg_drv_vbus(fsm, 1);
1607 +               fsl_otg_start_host(fsm, 1);
1608         }
1609  }
1610
1611 @@ -724,6 +742,7 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1612  {
1613         struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
1614         struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
1615 +       struct fsl_otg *otg_dev = dev_id;
1616         u32 otg_int_src, otg_sc;
1617
1618         otg_sc = fsl_readl(&usb_dr_regs->otgsc);
1619 @@ -753,18 +772,8 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1620                                 otg->gadget->is_a_peripheral = !fsm->id;
1621                         VDBG("ID int (ID is %d)\n", fsm->id);
1622
1623 -                       if (fsm->id) {  /* switch to gadget */
1624 -                               schedule_delayed_work(
1625 -                                       &((struct fsl_otg *)dev_id)->otg_event,
1626 -                                       100);
1627 -                       } else {        /* switch to host */
1628 -                               cancel_delayed_work(&
1629 -                                                   ((struct fsl_otg *)dev_id)->
1630 -                                                   otg_event);
1631 -                               fsl_otg_start_gadget(fsm, 0);
1632 -                               otg_drv_vbus(fsm, 1);
1633 -                               fsl_otg_start_host(fsm, 1);
1634 -                       }
1635 +                       schedule_delayed_work(&otg_dev->otg_event, 100);
1636 +
1637                         return IRQ_HANDLED;
1638                 }
1639         }
1640 @@ -925,12 +934,32 @@ int usb_otg_start(struct platform_device
1641         temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
1642         switch (pdata->phy_mode) {
1643         case FSL_USB2_PHY_ULPI:
1644 +               if (pdata->controller_ver) {
1645 +                       /* controller version 1.6 or above */
1646 +                       setbits32(&p_otg->dr_mem_map->control,
1647 +                               USB_CTRL_ULPI_PHY_CLK_SEL);
1648 +                       /*
1649 +                        * Due to controller issue of PHY_CLK_VALID in ULPI
1650 +                        * mode, we set USB_CTRL_USB_EN before checking
1651 +                        * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
1652 +                        */
1653 +                       clrsetbits_be32(&p_otg->dr_mem_map->control,
1654 +                               USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
1655 +               }
1656                 temp |= PORTSC_PTS_ULPI;
1657                 break;
1658         case FSL_USB2_PHY_UTMI_WIDE:
1659                 temp |= PORTSC_PTW_16BIT;
1660                 /* fall through */
1661         case FSL_USB2_PHY_UTMI:
1662 +               if (pdata->controller_ver) {
1663 +                       /* controller version 1.6 or above */
1664 +                       setbits32(&p_otg->dr_mem_map->control,
1665 +                               USB_CTRL_UTMI_PHY_EN);
1666 +                       /* Delay for UTMI PHY CLK to become stable - 10ms */
1667 +                       mdelay(FSL_UTMI_PHY_DLY);
1668 +               }
1669 +               setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
1670                 temp |= PORTSC_PTS_UTMI;
1671                 /* fall through */
1672         default:
1673 --- a/drivers/usb/phy/phy-fsl-usb.h
1674 +++ b/drivers/usb/phy/phy-fsl-usb.h
1675 @@ -199,6 +199,14 @@
1676  /* control Register Bit Masks */
1677  #define  USB_CTRL_IOENB                        (0x1<<2)
1678  #define  USB_CTRL_ULPI_INT0EN          (0x1<<0)
1679 +#define        USB_CTRL_WU_INT_EN              (0x1<<1)
1680 +#define        USB_CTRL_LINE_STATE_FILTER__EN  (0x1<<3)
1681 +#define        USB_CTRL_KEEP_OTG_ON            (0x1<<4)
1682 +#define        USB_CTRL_OTG_PORT               (0x1<<5)
1683 +#define        USB_CTRL_PLL_RESET              (0x1<<8)
1684 +#define        USB_CTRL_UTMI_PHY_EN            (0x1<<9)
1685 +#define        USB_CTRL_ULPI_PHY_CLK_SEL       (0x1<<10)
1686 +#define        USB_CTRL_PHY_CLK_VALID          (0x1<<17)
1687
1688  /* BCSR5 */
1689  #define BCSR5_INT_USB                  (0x02)
1690 --- a/include/linux/usb.h
1691 +++ b/include/linux/usb.h
1692 @@ -360,6 +360,7 @@ struct usb_bus {
1693                                          * for control transfers?
1694                                          */
1695         u8 otg_port;                    /* 0, or number of OTG/HNP port */
1696 +       unsigned is_otg:1;              /* true when host is also otg */
1697         unsigned is_b_host:1;           /* true during some HNP roleswitches */
1698         unsigned b_hnp_enable:1;        /* OTG: did A-Host enable HNP? */
1699         unsigned no_stop_on_short:1;    /*
1700 --- a/include/linux/usb/of.h
1701 +++ b/include/linux/usb/of.h
1702 @@ -11,6 +11,8 @@
1703  #include <linux/usb/otg.h>
1704  #include <linux/usb/phy.h>
1705
1706 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np);
1707 +
1708  #if IS_ENABLED(CONFIG_OF)
1709  enum usb_dr_mode of_usb_get_dr_mode_by_phy(struct device_node *np, int arg0);
1710  bool of_usb_host_tpl_support(struct device_node *np);