target/linux/brcm63xx/patches-4.14/140-pinctrl-add-a-pincontrol-driver-for-BCM6368.patch

   1 From 90be3cb4f1a45b8be4a4ec264cd66c2f8e893fcb Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Fri, 24 Jun 2016 22:18:25 +0200
   4 Subject: [PATCH 11/16] pinctrl: add a pincontrol driver for BCM6368
   5
   6 Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32
   7 GPIOs onto alternative functions. Not all are documented.
   8
   9 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  10 ---
  11  drivers/pinctrl/bcm63xx/Kconfig           |  15 +
  12  drivers/pinctrl/bcm63xx/Makefile          |   1 +
  13  drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c | 573 ++++++++++++++++++++++++++++++
  14  3 files changed, 589 insertions(+)
  15  create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c
  16
  17 --- a/drivers/pinctrl/bcm63xx/Kconfig
  18 +++ b/drivers/pinctrl/bcm63xx/Kconfig
  19 @@ -30,3 +30,18 @@ config PINCTRL_BCM6362
  20         select PINCONF
  21         select PINCTRL_BCM63XX
  22         select GENERIC_PINCONF
  23 +
  24 +config PINCTRL_BCM6368
  25 +       bool "BCM6368 pincontrol driver" if COMPILE_TEST
  26 +       select PINMUX
  27 +       select PINCONF
  28 +       select PINCTRL_BCM63XX
  29 +       select GENERIC_PINCONF
  30 +       select MFD_SYSCON
  31 +
  32 +config PINCTRL_BCM63268
  33 +       bool "BCM63268 pincontrol driver" if COMPILE_TEST
  34 +       select PINMUX
  35 +       select PINCONF
  36 +       select PINCTRL_BCM63XX
  37 +       select GENERIC_PINCONF
  38 --- a/drivers/pinctrl/bcm63xx/Makefile
  39 +++ b/drivers/pinctrl/bcm63xx/Makefile
  40 @@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_BCM6328)   += pinctrl
  41  obj-$(CONFIG_PINCTRL_BCM6348)  += pinctrl-bcm6348.o
  42  obj-$(CONFIG_PINCTRL_BCM6358)  += pinctrl-bcm6358.o
  43  obj-$(CONFIG_PINCTRL_BCM6362)  += pinctrl-bcm6362.o
  44 +obj-$(CONFIG_PINCTRL_BCM6368)  += pinctrl-bcm6368.o
  45 --- /dev/null
  46 +++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c
  47 @@ -0,0 +1,573 @@
  48 +/*
  49 + * This file is subject to the terms and conditions of the GNU General Public
  50 + * License.  See the file "COPYING" in the main directory of this archive
  51 + * for more details.
  52 + *
  53 + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
  54 + */
  55 +
  56 +#include <linux/bitops.h>
  57 +#include <linux/kernel.h>
  58 +#include <linux/gpio.h>
  59 +#include <linux/mfd/syscon.h>
  60 +#include <linux/of.h>
  61 +#include <linux/of_address.h>
  62 +#include <linux/of_gpio.h>
  63 +#include <linux/pinctrl/pinconf.h>
  64 +#include <linux/pinctrl/pinconf-generic.h>
  65 +#include <linux/pinctrl/pinmux.h>
  66 +#include <linux/pinctrl/machine.h>
  67 +#include <linux/platform_device.h>
  68 +#include <linux/regmap.h>
  69 +#include <linux/slab.h>
  70 +#include <linux/spinlock.h>
  71 +
  72 +#include "../core.h"
  73 +#include "../pinctrl-utils.h"
  74 +
  75 +#include "pinctrl-bcm63xx.h"
  76 +
  77 +#define BCM6368_NGPIO  38
  78 +
  79 +#define BCM6368_BASEMODE_MASK  0x7
  80 +#define BCM6368_BASEMODE_GPIO  0x0
  81 +#define BCM6368_BASEMODE_UART1 0x1
  82 +
  83 +struct bcm6368_pingroup {
  84 +       const char *name;
  85 +       const unsigned * const pins;
  86 +       const unsigned num_pins;
  87 +};
  88 +
  89 +struct bcm6368_function {
  90 +       const char *name;
  91 +       const char * const *groups;
  92 +       const unsigned num_groups;
  93 +
  94 +       unsigned dir_out:16;
  95 +       unsigned basemode:3;
  96 +};
  97 +
  98 +struct bcm6368_pinctrl {
  99 +       struct pinctrl_dev *pctldev;
 100 +       struct pinctrl_desc desc;
 101 +
 102 +       void __iomem *mode;
 103 +       struct regmap_field *overlay;
 104 +
 105 +       /* register access lock */
 106 +       spinlock_t lock;
 107 +
 108 +       struct gpio_chip gpio[2];
 109 +};
 110 +
 111 +#define BCM6368_BASEMODE_PIN(a, b)             \
 112 +       {                                       \
 113 +               .number = a,                    \
 114 +               .name = b,                      \
 115 +               .drv_data = (void *)true        \
 116 +       }
 117 +
 118 +static const struct pinctrl_pin_desc bcm6368_pins[] = {
 119 +       PINCTRL_PIN(0, "gpio0"),
 120 +       PINCTRL_PIN(1, "gpio1"),
 121 +       PINCTRL_PIN(2, "gpio2"),
 122 +       PINCTRL_PIN(3, "gpio3"),
 123 +       PINCTRL_PIN(4, "gpio4"),
 124 +       PINCTRL_PIN(5, "gpio5"),
 125 +       PINCTRL_PIN(6, "gpio6"),
 126 +       PINCTRL_PIN(7, "gpio7"),
 127 +       PINCTRL_PIN(8, "gpio8"),
 128 +       PINCTRL_PIN(9, "gpio9"),
 129 +       PINCTRL_PIN(10, "gpio10"),
 130 +       PINCTRL_PIN(11, "gpio11"),
 131 +       PINCTRL_PIN(12, "gpio12"),
 132 +       PINCTRL_PIN(13, "gpio13"),
 133 +       PINCTRL_PIN(14, "gpio14"),
 134 +       PINCTRL_PIN(15, "gpio15"),
 135 +       PINCTRL_PIN(16, "gpio16"),
 136 +       PINCTRL_PIN(17, "gpio17"),
 137 +       PINCTRL_PIN(18, "gpio18"),
 138 +       PINCTRL_PIN(19, "gpio19"),
 139 +       PINCTRL_PIN(20, "gpio20"),
 140 +       PINCTRL_PIN(21, "gpio21"),
 141 +       PINCTRL_PIN(22, "gpio22"),
 142 +       PINCTRL_PIN(23, "gpio23"),
 143 +       PINCTRL_PIN(24, "gpio24"),
 144 +       PINCTRL_PIN(25, "gpio25"),
 145 +       PINCTRL_PIN(26, "gpio26"),
 146 +       PINCTRL_PIN(27, "gpio27"),
 147 +       PINCTRL_PIN(28, "gpio28"),
 148 +       PINCTRL_PIN(29, "gpio29"),
 149 +       BCM6368_BASEMODE_PIN(30, "gpio30"),
 150 +       BCM6368_BASEMODE_PIN(31, "gpio31"),
 151 +       BCM6368_BASEMODE_PIN(32, "gpio32"),
 152 +       BCM6368_BASEMODE_PIN(33, "gpio33"),
 153 +       PINCTRL_PIN(34, "gpio34"),
 154 +       PINCTRL_PIN(35, "gpio35"),
 155 +       PINCTRL_PIN(36, "gpio36"),
 156 +       PINCTRL_PIN(37, "gpio37"),
 157 +};
 158 +
 159 +static unsigned gpio0_pins[] = { 0 };
 160 +static unsigned gpio1_pins[] = { 1 };
 161 +static unsigned gpio2_pins[] = { 2 };
 162 +static unsigned gpio3_pins[] = { 3 };
 163 +static unsigned gpio4_pins[] = { 4 };
 164 +static unsigned gpio5_pins[] = { 5 };
 165 +static unsigned gpio6_pins[] = { 6 };
 166 +static unsigned gpio7_pins[] = { 7 };
 167 +static unsigned gpio8_pins[] = { 8 };
 168 +static unsigned gpio9_pins[] = { 9 };
 169 +static unsigned gpio10_pins[] = { 10 };
 170 +static unsigned gpio11_pins[] = { 11 };
 171 +static unsigned gpio12_pins[] = { 12 };
 172 +static unsigned gpio13_pins[] = { 13 };
 173 +static unsigned gpio14_pins[] = { 14 };
 174 +static unsigned gpio15_pins[] = { 15 };
 175 +static unsigned gpio16_pins[] = { 16 };
 176 +static unsigned gpio17_pins[] = { 17 };
 177 +static unsigned gpio18_pins[] = { 18 };
 178 +static unsigned gpio19_pins[] = { 19 };
 179 +static unsigned gpio20_pins[] = { 20 };
 180 +static unsigned gpio21_pins[] = { 21 };
 181 +static unsigned gpio22_pins[] = { 22 };
 182 +static unsigned gpio23_pins[] = { 23 };
 183 +static unsigned gpio24_pins[] = { 24 };
 184 +static unsigned gpio25_pins[] = { 25 };
 185 +static unsigned gpio26_pins[] = { 26 };
 186 +static unsigned gpio27_pins[] = { 27 };
 187 +static unsigned gpio28_pins[] = { 28 };
 188 +static unsigned gpio29_pins[] = { 29 };
 189 +static unsigned gpio30_pins[] = { 30 };
 190 +static unsigned gpio31_pins[] = { 31 };
 191 +static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 };
 192 +
 193 +#define BCM6368_GROUP(n)                               \
 194 +       {                                               \
 195 +               .name = #n,                             \
 196 +               .pins = n##_pins,                       \
 197 +               .num_pins = ARRAY_SIZE(n##_pins),       \
 198 +       }
 199 +
 200 +static struct bcm6368_pingroup bcm6368_groups[] = {
 201 +       BCM6368_GROUP(gpio0),
 202 +       BCM6368_GROUP(gpio1),
 203 +       BCM6368_GROUP(gpio2),
 204 +       BCM6368_GROUP(gpio3),
 205 +       BCM6368_GROUP(gpio4),
 206 +       BCM6368_GROUP(gpio5),
 207 +       BCM6368_GROUP(gpio6),
 208 +       BCM6368_GROUP(gpio7),
 209 +       BCM6368_GROUP(gpio8),
 210 +       BCM6368_GROUP(gpio9),
 211 +       BCM6368_GROUP(gpio10),
 212 +       BCM6368_GROUP(gpio11),
 213 +       BCM6368_GROUP(gpio12),
 214 +       BCM6368_GROUP(gpio13),
 215 +       BCM6368_GROUP(gpio14),
 216 +       BCM6368_GROUP(gpio15),
 217 +       BCM6368_GROUP(gpio16),
 218 +       BCM6368_GROUP(gpio17),
 219 +       BCM6368_GROUP(gpio18),
 220 +       BCM6368_GROUP(gpio19),
 221 +       BCM6368_GROUP(gpio20),
 222 +       BCM6368_GROUP(gpio21),
 223 +       BCM6368_GROUP(gpio22),
 224 +       BCM6368_GROUP(gpio23),
 225 +       BCM6368_GROUP(gpio24),
 226 +       BCM6368_GROUP(gpio25),
 227 +       BCM6368_GROUP(gpio26),
 228 +       BCM6368_GROUP(gpio27),
 229 +       BCM6368_GROUP(gpio28),
 230 +       BCM6368_GROUP(gpio29),
 231 +       BCM6368_GROUP(gpio30),
 232 +       BCM6368_GROUP(gpio31),
 233 +       BCM6368_GROUP(uart1_grp),
 234 +};
 235 +
 236 +static const char * const analog_afe_0_groups[] = {
 237 +       "gpio0",
 238 +};
 239 +
 240 +static const char * const analog_afe_1_groups[] = {
 241 +       "gpio1",
 242 +};
 243 +
 244 +static const char * const sys_irq_groups[] = {
 245 +       "gpio2",
 246 +};
 247 +
 248 +static const char * const serial_led_data_groups[] = {
 249 +       "gpio3",
 250 +};
 251 +
 252 +static const char * const serial_led_clk_groups[] = {
 253 +       "gpio4",
 254 +};
 255 +
 256 +static const char * const inet_led_groups[] = {
 257 +       "gpio5",
 258 +};
 259 +
 260 +static const char * const ephy0_led_groups[] = {
 261 +       "gpio6",
 262 +};
 263 +
 264 +static const char * const ephy1_led_groups[] = {
 265 +       "gpio7",
 266 +};
 267 +
 268 +static const char * const ephy2_led_groups[] = {
 269 +       "gpio8",
 270 +};
 271 +
 272 +static const char * const ephy3_led_groups[] = {
 273 +       "gpio9",
 274 +};
 275 +
 276 +static const char * const robosw_led_data_groups[] = {
 277 +       "gpio10",
 278 +};
 279 +
 280 +static const char * const robosw_led_clk_groups[] = {
 281 +       "gpio11",
 282 +};
 283 +
 284 +static const char * const robosw_led0_groups[] = {
 285 +       "gpio12",
 286 +};
 287 +
 288 +static const char * const robosw_led1_groups[] = {
 289 +       "gpio13",
 290 +};
 291 +
 292 +static const char * const usb_device_led_groups[] = {
 293 +       "gpio14",
 294 +};
 295 +
 296 +static const char * const pci_req1_groups[] = {
 297 +       "gpio16",
 298 +};
 299 +
 300 +static const char * const pci_gnt1_groups[] = {
 301 +       "gpio17",
 302 +};
 303 +
 304 +static const char * const pci_intb_groups[] = {
 305 +       "gpio18",
 306 +};
 307 +
 308 +static const char * const pci_req0_groups[] = {
 309 +       "gpio19",
 310 +};
 311 +
 312 +static const char * const pci_gnt0_groups[] = {
 313 +       "gpio20",
 314 +};
 315 +
 316 +static const char * const pcmcia_cd1_groups[] = {
 317 +       "gpio22",
 318 +};
 319 +
 320 +static const char * const pcmcia_cd2_groups[] = {
 321 +       "gpio23",
 322 +};
 323 +
 324 +static const char * const pcmcia_vs1_groups[] = {
 325 +       "gpio24",
 326 +};
 327 +
 328 +static const char * const pcmcia_vs2_groups[] = {
 329 +       "gpio25",
 330 +};
 331 +
 332 +static const char * const ebi_cs2_groups[] = {
 333 +       "gpio26",
 334 +};
 335 +
 336 +static const char * const ebi_cs3_groups[] = {
 337 +       "gpio27",
 338 +};
 339 +
 340 +static const char * const spi_cs2_groups[] = {
 341 +       "gpio28",
 342 +};
 343 +
 344 +static const char * const spi_cs3_groups[] = {
 345 +       "gpio29",
 346 +};
 347 +
 348 +static const char * const spi_cs4_groups[] = {
 349 +       "gpio30",
 350 +};
 351 +
 352 +static const char * const spi_cs5_groups[] = {
 353 +       "gpio31",
 354 +};
 355 +
 356 +static const char * const uart1_groups[] = {
 357 +       "uart1_grp",
 358 +};
 359 +
 360 +#define BCM6368_FUN(n, out)                            \
 361 +       {                                               \
 362 +               .name = #n,                             \
 363 +               .groups = n##_groups,                   \
 364 +               .num_groups = ARRAY_SIZE(n##_groups),   \
 365 +               .dir_out = out,                         \
 366 +       }
 367 +
 368 +#define BCM6368_BASEMODE_FUN(n, val, out)              \
 369 +       {                                               \
 370 +               .name = #n,                             \
 371 +               .groups = n##_groups,                   \
 372 +               .num_groups = ARRAY_SIZE(n##_groups),   \
 373 +               .basemode = BCM6368_BASEMODE_##val,     \
 374 +               .dir_out = out,                         \
 375 +       }
 376 +
 377 +static const struct bcm6368_function bcm6368_funcs[] = {
 378 +       BCM6368_FUN(analog_afe_0, 1),
 379 +       BCM6368_FUN(analog_afe_1, 1),
 380 +       BCM6368_FUN(sys_irq, 1),
 381 +       BCM6368_FUN(serial_led_data, 1),
 382 +       BCM6368_FUN(serial_led_clk, 1),
 383 +       BCM6368_FUN(inet_led, 1),
 384 +       BCM6368_FUN(ephy0_led, 1),
 385 +       BCM6368_FUN(ephy1_led, 1),
 386 +       BCM6368_FUN(ephy2_led, 1),
 387 +       BCM6368_FUN(ephy3_led, 1),
 388 +       BCM6368_FUN(robosw_led_data, 1),
 389 +       BCM6368_FUN(robosw_led_clk, 1),
 390 +       BCM6368_FUN(robosw_led0, 1),
 391 +       BCM6368_FUN(robosw_led1, 1),
 392 +       BCM6368_FUN(usb_device_led, 1),
 393 +       BCM6368_FUN(pci_req1, 0),
 394 +       BCM6368_FUN(pci_gnt1, 0),
 395 +       BCM6368_FUN(pci_intb, 0),
 396 +       BCM6368_FUN(pci_req0, 0),
 397 +       BCM6368_FUN(pci_gnt0, 0),
 398 +       BCM6368_FUN(pcmcia_cd1, 0),
 399 +       BCM6368_FUN(pcmcia_cd2, 0),
 400 +       BCM6368_FUN(pcmcia_vs1, 0),
 401 +       BCM6368_FUN(pcmcia_vs2, 0),
 402 +       BCM6368_FUN(ebi_cs2, 1),
 403 +       BCM6368_FUN(ebi_cs3, 1),
 404 +       BCM6368_FUN(spi_cs2, 1),
 405 +       BCM6368_FUN(spi_cs3, 1),
 406 +       BCM6368_FUN(spi_cs4, 1),
 407 +       BCM6368_FUN(spi_cs5, 1),
 408 +       BCM6368_BASEMODE_FUN(uart1, UART1, 0x6),
 409 +};
 410 +
 411 +static int bcm6368_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
 412 +{
 413 +       return ARRAY_SIZE(bcm6368_groups);
 414 +}
 415 +
 416 +static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 417 +                                                 unsigned group)
 418 +{
 419 +       return bcm6368_groups[group].name;
 420 +}
 421 +
 422 +static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 423 +                                         unsigned group, const unsigned **pins,
 424 +                                         unsigned *num_pins)
 425 +{
 426 +       *pins = bcm6368_groups[group].pins;
 427 +       *num_pins = bcm6368_groups[group].num_pins;
 428 +
 429 +       return 0;
 430 +}
 431 +
 432 +static int bcm6368_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
 433 +{
 434 +       return ARRAY_SIZE(bcm6368_funcs);
 435 +}
 436 +
 437 +static const char *bcm6368_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 438 +                                                unsigned selector)
 439 +{
 440 +       return bcm6368_funcs[selector].name;
 441 +}
 442 +
 443 +static int bcm6368_pinctrl_get_groups(struct pinctrl_dev *pctldev,
 444 +                                     unsigned selector,
 445 +                                     const char * const **groups,
 446 +                                     unsigned * const num_groups)
 447 +{
 448 +       *groups = bcm6368_funcs[selector].groups;
 449 +       *num_groups = bcm6368_funcs[selector].num_groups;
 450 +
 451 +       return 0;
 452 +}
 453 +
 454 +static void bcm6368_rmw_mux(struct bcm6368_pinctrl *pctl, void __iomem *reg,
 455 +                           u32 mask, u32 val)
 456 +{
 457 +       u32 tmp;
 458 +
 459 +       tmp = __raw_readl(reg);
 460 +       tmp &= ~mask;
 461 +       tmp |= (val & mask);
 462 +       __raw_writel(tmp, reg);
 463 +}
 464 +
 465 +static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 466 +                                  unsigned selector, unsigned group)
 467 +{
 468 +       struct bcm6368_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 469 +       const struct bcm6368_pingroup *grp = &bcm6368_groups[group];
 470 +       const struct bcm6368_function *fun = &bcm6368_funcs[selector];
 471 +       unsigned long flags;
 472 +       int i, pin;
 473 +
 474 +       spin_lock_irqsave(&pctl->lock, flags);
 475 +       if (fun->basemode) {
 476 +               u32 mask = 0;
 477 +
 478 +               for (i = 0; i < grp->num_pins; i++) {
 479 +                       pin = grp->pins[i];
 480 +                       if (pin < 32)
 481 +                               mask |= BIT(pin);
 482 +               }
 483 +
 484 +               bcm6368_rmw_mux(pctl, pctl->mode, mask, 0);
 485 +               regmap_field_write(pctl->overlay, fun->basemode);
 486 +       } else {
 487 +               pin = grp->pins[0];
 488 +
 489 +               if (bcm6368_pins[pin].drv_data)
 490 +                       regmap_field_write(pctl->overlay,
 491 +                                          BCM6368_BASEMODE_GPIO);
 492 +
 493 +               bcm6368_rmw_mux(pctl, pctl->mode, BIT(pin), BIT(pin));
 494 +       }
 495 +       spin_unlock_irqrestore(&pctl->lock, flags);
 496 +
 497 +       for (pin = 0; pin < grp->num_pins; pin++) {
 498 +               int hw_gpio = bcm6368_pins[pin].number;
 499 +               struct gpio_chip *gc = &pctl->gpio[hw_gpio / 32];
 500 +
 501 +               if (fun->dir_out & BIT(pin))
 502 +                       gc->direction_output(gc, hw_gpio % 32, 0);
 503 +               else
 504 +                       gc->direction_input(gc, hw_gpio % 32);
 505 +       }
 506 +
 507 +       return 0;
 508 +}
 509 +
 510 +static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev,
 511 +                                      struct pinctrl_gpio_range *range,
 512 +                                      unsigned offset)
 513 +{
 514 +       struct bcm6368_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 515 +       unsigned long flags;
 516 +
 517 +       if (offset >= 32 && !bcm6368_pins[offset].drv_data)
 518 +               return 0;
 519 +
 520 +       spin_lock_irqsave(&pctl->lock, flags);
 521 +       /* disable all functions using this pin */
 522 +       if (offset < 32)
 523 +               bcm6368_rmw_mux(pctl, pctl->mode, BIT(offset), 0);
 524 +
 525 +       if (bcm6368_pins[offset].drv_data)
 526 +               regmap_field_write(pctl->overlay, BCM6368_BASEMODE_GPIO);
 527 +
 528 +       spin_unlock_irqrestore(&pctl->lock, flags);
 529 +
 530 +       return 0;
 531 +}
 532 +
 533 +static struct pinctrl_ops bcm6368_pctl_ops = {
 534 +       .get_groups_count       = bcm6368_pinctrl_get_group_count,
 535 +       .get_group_name         = bcm6368_pinctrl_get_group_name,
 536 +       .get_group_pins         = bcm6368_pinctrl_get_group_pins,
 537 +#ifdef CONFIG_OF
 538 +       .dt_node_to_map         = pinconf_generic_dt_node_to_map_pin,
 539 +       .dt_free_map            = pinctrl_utils_free_map,
 540 +#endif
 541 +};
 542 +
 543 +static struct pinmux_ops bcm6368_pmx_ops = {
 544 +       .get_functions_count    = bcm6368_pinctrl_get_func_count,
 545 +       .get_function_name      = bcm6368_pinctrl_get_func_name,
 546 +       .get_function_groups    = bcm6368_pinctrl_get_groups,
 547 +       .set_mux                = bcm6368_pinctrl_set_mux,
 548 +       .gpio_request_enable    = bcm6368_gpio_request_enable,
 549 +       .strict                 = true,
 550 +};
 551 +
 552 +static int bcm6368_pinctrl_probe(struct platform_device *pdev)
 553 +{
 554 +       struct bcm6368_pinctrl *pctl;
 555 +       struct resource *res;
 556 +       void __iomem *mode;
 557 +       struct regmap *basemode;
 558 +       struct reg_field overlay = REG_FIELD(0, 0, 3);
 559 +
 560 +       if (pdev->dev.of_node)
 561 +               basemode = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 562 +                                                          "brcm,gpiobasemode");
 563 +       else
 564 +               basemode = syscon_regmap_lookup_by_pdevname("syscon.b00000b8");
 565 +
 566 +       if (IS_ERR(basemode))
 567 +               return PTR_ERR(basemode);
 568 +
 569 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
 570 +       mode = devm_ioremap_resource(&pdev->dev, res);
 571 +       if (IS_ERR(mode))
 572 +               return PTR_ERR(mode);
 573 +
 574 +       pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
 575 +       if (!pctl)
 576 +               return -ENOMEM;
 577 +
 578 +       pctl->overlay = devm_regmap_field_alloc(&pdev->dev, basemode, overlay);
 579 +       if (IS_ERR(pctl->overlay))
 580 +               return PTR_ERR(pctl->overlay);
 581 +
 582 +       spin_lock_init(&pctl->lock);
 583 +
 584 +       pctl->mode = mode;
 585 +
 586 +       /* disable all muxes by default */
 587 +       __raw_writel(0, pctl->mode);
 588 +
 589 +       pctl->desc.name = dev_name(&pdev->dev);
 590 +       pctl->desc.owner = THIS_MODULE;
 591 +       pctl->desc.pctlops = &bcm6368_pctl_ops;
 592 +       pctl->desc.pmxops = &bcm6368_pmx_ops;
 593 +
 594 +       pctl->desc.npins = ARRAY_SIZE(bcm6368_pins);
 595 +       pctl->desc.pins = bcm6368_pins;
 596 +
 597 +       platform_set_drvdata(pdev, pctl);
 598 +
 599 +       pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
 600 +                                                pctl->gpio, BCM6368_NGPIO);
 601 +       if (IS_ERR(pctl->pctldev))
 602 +               return PTR_ERR(pctl->pctldev);
 603 +
 604 +       return 0;
 605 +}
 606 +
 607 +static const struct of_device_id bcm6368_pinctrl_match[] = {
 608 +       { .compatible = "brcm,bcm6368-pinctrl", },
 609 +       { },
 610 +};
 611 +
 612 +static struct platform_driver bcm6368_pinctrl_driver = {
 613 +       .probe = bcm6368_pinctrl_probe,
 614 +       .driver = {
 615 +               .name = "bcm6368-pinctrl",
 616 +               .of_match_table = bcm6368_pinctrl_match,
 617 +       },
 618 +};
 619 +
 620 +builtin_platform_driver(bcm6368_pinctrl_driver);