target/linux/brcm63xx/patches-4.14/134-pinctrl-add-a-pincontrol-driver-for-BCM6348.patch

   1 From 45444cb631555e2dc16b95d779b10aa075c7482e Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Fri, 24 Jun 2016 22:14:13 +0200
   4 Subject: [PATCH 05/16] pinctrl: add a pincontrol driver for BCM6348
   5
   6 Add a pincotrol driver for BCM6348. BCM6348 allow muxing five groups of
   7 up to ten gpios into fourteen potential functions. It does not allow
   8 muxing individual pins. Some functions require more than one group to be
   9 muxed to the same function.
  10
  11 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  12 ---
  13  drivers/pinctrl/bcm63xx/Kconfig           |   7 +
  14  drivers/pinctrl/bcm63xx/Makefile          |   1 +
  15  drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c | 392 ++++++++++++++++++++++++++++++
  16  3 files changed, 400 insertions(+)
  17  create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c
  18
  19 --- a/drivers/pinctrl/bcm63xx/Kconfig
  20 +++ b/drivers/pinctrl/bcm63xx/Kconfig
  21 @@ -8,3 +8,10 @@ config PINCTRL_BCM6328
  22         select PINCONF
  23         select PINCTRL_BCM63XX
  24         select GENERIC_PINCONF
  25 +
  26 +config PINCTRL_BCM6348
  27 +       bool "BCM6348 pincontrol driver" if COMPILE_TEST
  28 +       select PINMUX
  29 +       select PINCONF
  30 +       select PINCTRL_BCM63XX
  31 +       select GENERIC_PINCONF
  32 --- a/drivers/pinctrl/bcm63xx/Makefile
  33 +++ b/drivers/pinctrl/bcm63xx/Makefile
  34 @@ -1,2 +1,3 @@
  35  obj-$(CONFIG_PINCTRL_BCM63XX)  += pinctrl-bcm63xx.o
  36  obj-$(CONFIG_PINCTRL_BCM6328)  += pinctrl-bcm6328.o
  37 +obj-$(CONFIG_PINCTRL_BCM6348)  += pinctrl-bcm6348.o
  38 --- /dev/null
  39 +++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c
  40 @@ -0,0 +1,392 @@
  41 +/*
  42 + * This file is subject to the terms and conditions of the GNU General Public
  43 + * License.  See the file "COPYING" in the main directory of this archive
  44 + * for more details.
  45 + *
  46 + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
  47 + */
  48 +
  49 +#include <linux/kernel.h>
  50 +#include <linux/spinlock.h>
  51 +#include <linux/bitops.h>
  52 +#include <linux/gpio.h>
  53 +#include <linux/of.h>
  54 +#include <linux/of_gpio.h>
  55 +#include <linux/slab.h>
  56 +#include <linux/platform_device.h>
  57 +
  58 +#include <linux/pinctrl/machine.h>
  59 +#include <linux/pinctrl/pinconf.h>
  60 +#include <linux/pinctrl/pinconf-generic.h>
  61 +#include <linux/pinctrl/pinmux.h>
  62 +
  63 +#include "../core.h"
  64 +#include "../pinctrl-utils.h"
  65 +
  66 +#include "pinctrl-bcm63xx.h"
  67 +
  68 +#define BCM6348_NGPIO          37
  69 +
  70 +#define MAX_GROUP              4
  71 +#define PINS_PER_GROUP         8
  72 +#define PIN_TO_GROUP(pin)      (MAX_GROUP - ((pin) / PINS_PER_GROUP))
  73 +#define GROUP_SHIFT(pin)       (PIN_TO_GROUP(pin) * 4)
  74 +#define GROUP_MASK(pin)                (0xf << GROUP_SHIFT(pin))
  75 +
  76 +struct bcm6348_pingroup {
  77 +       const char *name;
  78 +       const unsigned * const pins;
  79 +       const unsigned num_pins;
  80 +};
  81 +
  82 +struct bcm6348_function {
  83 +       const char *name;
  84 +       const char * const *groups;
  85 +       const unsigned num_groups;
  86 +       unsigned int value;
  87 +};
  88 +
  89 +struct bcm6348_pinctrl {
  90 +       struct pinctrl_dev *pctldev;
  91 +       struct pinctrl_desc desc;
  92 +
  93 +       void __iomem *mode;
  94 +
  95 +       /* register access lock */
  96 +       spinlock_t lock;
  97 +
  98 +       struct gpio_chip gpio[2];
  99 +};
 100 +
 101 +#define BCM6348_PIN(a, b, group)               \
 102 +       {                                       \
 103 +               .number = a,                    \
 104 +               .name = b,                      \
 105 +               .drv_data = (void *)(group),    \
 106 +       }
 107 +
 108 +static const struct pinctrl_pin_desc bcm6348_pins[] = {
 109 +       BCM6348_PIN(0, "gpio0", 4),
 110 +       BCM6348_PIN(1, "gpio1", 4),
 111 +       BCM6348_PIN(2, "gpio2", 4),
 112 +       BCM6348_PIN(3, "gpio3", 4),
 113 +       BCM6348_PIN(4, "gpio4", 4),
 114 +       BCM6348_PIN(5, "gpio5", 4),
 115 +       BCM6348_PIN(6, "gpio6", 4),
 116 +       BCM6348_PIN(7, "gpio7", 4),
 117 +       BCM6348_PIN(8, "gpio8", 3),
 118 +       BCM6348_PIN(9, "gpio9", 3),
 119 +       BCM6348_PIN(10, "gpio10", 3),
 120 +       BCM6348_PIN(11, "gpio11", 3),
 121 +       BCM6348_PIN(12, "gpio12", 3),
 122 +       BCM6348_PIN(13, "gpio13", 3),
 123 +       BCM6348_PIN(14, "gpio14", 3),
 124 +       BCM6348_PIN(15, "gpio15", 3),
 125 +       BCM6348_PIN(16, "gpio16", 2),
 126 +       BCM6348_PIN(17, "gpio17", 2),
 127 +       BCM6348_PIN(18, "gpio18", 2),
 128 +       BCM6348_PIN(19, "gpio19", 2),
 129 +       BCM6348_PIN(20, "gpio20", 2),
 130 +       BCM6348_PIN(21, "gpio21", 2),
 131 +       BCM6348_PIN(22, "gpio22", 1),
 132 +       BCM6348_PIN(23, "gpio23", 1),
 133 +       BCM6348_PIN(24, "gpio24", 1),
 134 +       BCM6348_PIN(25, "gpio25", 1),
 135 +       BCM6348_PIN(26, "gpio26", 1),
 136 +       BCM6348_PIN(27, "gpio27", 1),
 137 +       BCM6348_PIN(28, "gpio28", 1),
 138 +       BCM6348_PIN(29, "gpio29", 1),
 139 +       BCM6348_PIN(30, "gpio30", 1),
 140 +       BCM6348_PIN(31, "gpio31", 1),
 141 +       BCM6348_PIN(32, "gpio32", 0),
 142 +       BCM6348_PIN(33, "gpio33", 0),
 143 +       BCM6348_PIN(34, "gpio34", 0),
 144 +       BCM6348_PIN(35, "gpio35", 0),
 145 +       BCM6348_PIN(36, "gpio36", 0),
 146 +};
 147 +
 148 +enum bcm6348_muxes {
 149 +       BCM6348_MUX_GPIO = 0,
 150 +       BCM6348_MUX_EXT_EPHY,
 151 +       BCM6348_MUX_MII_SNOOP,
 152 +       BCM6348_MUX_LEGACY_LED,
 153 +       BCM6348_MUX_MII_PCCARD,
 154 +       BCM6348_MUX_PCI,
 155 +       BCM6348_MUX_SPI_MASTER_UART,
 156 +       BCM6348_MUX_EXT_MII,
 157 +       BCM6348_MUX_UTOPIA,
 158 +       BCM6348_MUX_DIAG,
 159 +};
 160 +
 161 +static unsigned group0_pins[] = {
 162 +       32, 33, 34, 35, 36,
 163 +};
 164 +
 165 +static unsigned group1_pins[] = {
 166 +       22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
 167 +};
 168 +
 169 +static unsigned group2_pins[] = {
 170 +       16, 17, 18, 19, 20, 21,
 171 +};
 172 +
 173 +static unsigned group3_pins[] = {
 174 +       8, 9, 10, 11, 12, 13, 14, 15,
 175 +};
 176 +
 177 +static unsigned group4_pins[] = {
 178 +       0, 1, 2, 3, 4, 5, 6, 7,
 179 +};
 180 +
 181 +#define BCM6348_GROUP(n)                               \
 182 +       {                                               \
 183 +               .name = #n,                             \
 184 +               .pins = n##_pins,                       \
 185 +               .num_pins = ARRAY_SIZE(n##_pins),       \
 186 +       } \
 187 +
 188 +static struct bcm6348_pingroup bcm6348_groups[] = {
 189 +       BCM6348_GROUP(group0),
 190 +       BCM6348_GROUP(group1),
 191 +       BCM6348_GROUP(group2),
 192 +       BCM6348_GROUP(group3),
 193 +       BCM6348_GROUP(group4),
 194 +};
 195 +
 196 +static const char * const ext_mii_groups[] = {
 197 +       "group0",
 198 +       "group3",
 199 +};
 200 +
 201 +static const char * const ext_ephy_groups[] = {
 202 +       "group1",
 203 +       "group4"
 204 +};
 205 +
 206 +static const char * const mii_snoop_groups[] = {
 207 +       "group1",
 208 +       "group4",
 209 +};
 210 +
 211 +static const char * const legacy_led_groups[] = {
 212 +       "group4",
 213 +};
 214 +
 215 +static const char * const mii_pccard_groups[] = {
 216 +       "group1",
 217 +};
 218 +
 219 +static const char * const pci_groups[] = {
 220 +       "group2",
 221 +};
 222 +
 223 +static const char * const spi_master_uart_groups[] = {
 224 +       "group1",
 225 +};
 226 +
 227 +static const char * const utopia_groups[] = {
 228 +       "group0",
 229 +       "group1",
 230 +       "group3",
 231 +};
 232 +
 233 +static const char * const diag_groups[] = {
 234 +       "group0",
 235 +       "group1",
 236 +       "group2",
 237 +       "group4",
 238 +};
 239 +
 240 +#define BCM6348_FUN(n, f)                              \
 241 +       {                                               \
 242 +               .name = #n,                             \
 243 +               .groups = n##_groups,                   \
 244 +               .num_groups = ARRAY_SIZE(n##_groups),   \
 245 +               .value = BCM6348_MUX_##f,               \
 246 +       }
 247 +
 248 +static const struct bcm6348_function bcm6348_funcs[] = {
 249 +       BCM6348_FUN(ext_mii, EXT_MII),
 250 +       BCM6348_FUN(ext_ephy, EXT_EPHY),
 251 +       BCM6348_FUN(mii_snoop, MII_SNOOP),
 252 +       BCM6348_FUN(legacy_led, LEGACY_LED),
 253 +       BCM6348_FUN(mii_pccard, MII_PCCARD),
 254 +       BCM6348_FUN(pci, PCI),
 255 +       BCM6348_FUN(spi_master_uart, SPI_MASTER_UART),
 256 +       BCM6348_FUN(utopia, UTOPIA),
 257 +       BCM6348_FUN(diag, DIAG),
 258 +};
 259 +
 260 +static int bcm6348_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
 261 +{
 262 +       return ARRAY_SIZE(bcm6348_groups);
 263 +}
 264 +
 265 +static const char *bcm6348_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 266 +                                                 unsigned group)
 267 +{
 268 +       return bcm6348_groups[group].name;
 269 +}
 270 +
 271 +static int bcm6348_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 272 +                                         unsigned group, const unsigned **pins,
 273 +                                         unsigned *num_pins)
 274 +{
 275 +       *pins = bcm6348_groups[group].pins;
 276 +       *num_pins = bcm6348_groups[group].num_pins;
 277 +
 278 +       return 0;
 279 +}
 280 +
 281 +static int bcm6348_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
 282 +{
 283 +       return ARRAY_SIZE(bcm6348_funcs);
 284 +}
 285 +
 286 +static const char *bcm6348_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 287 +                                                unsigned selector)
 288 +{
 289 +       return bcm6348_funcs[selector].name;
 290 +}
 291 +
 292 +static int bcm6348_pinctrl_get_groups(struct pinctrl_dev *pctldev,
 293 +                                     unsigned selector,
 294 +                                     const char * const **groups,
 295 +                                     unsigned * const num_groups)
 296 +{
 297 +       *groups = bcm6348_funcs[selector].groups;
 298 +       *num_groups = bcm6348_funcs[selector].num_groups;
 299 +
 300 +       return 0;
 301 +}
 302 +
 303 +static void bcm6348_rmw_mux(struct bcm6348_pinctrl *pctl, u32 mask, u32 val)
 304 +{
 305 +       unsigned long flags;
 306 +       u32 reg;
 307 +
 308 +       spin_lock_irqsave(&pctl->lock, flags);
 309 +
 310 +       reg = __raw_readl(pctl->mode);
 311 +       reg &= ~mask;
 312 +       reg |= val & mask;
 313 +       __raw_writel(reg, pctl->mode);
 314 +
 315 +       spin_unlock_irqrestore(&pctl->lock, flags);
 316 +}
 317 +
 318 +static int bcm6348_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 319 +                                  unsigned selector, unsigned group)
 320 +{
 321 +       struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 322 +       const struct bcm6348_pingroup *grp = &bcm6348_groups[group];
 323 +       const struct bcm6348_function *f = &bcm6348_funcs[selector];
 324 +       u32 group_num, mask, val;
 325 +
 326 +       /*
 327 +        * pins n..(n+7) share the same group, so we only need to look at
 328 +        * the first pin.
 329 +        */
 330 +       group_num = (unsigned long)bcm6348_pins[grp->pins[0]].drv_data;
 331 +       mask = GROUP_MASK(group_num);
 332 +       val = f->value << GROUP_SHIFT(group_num);
 333 +
 334 +       bcm6348_rmw_mux(pctl, mask, val);
 335 +
 336 +       return 0;
 337 +}
 338 +
 339 +static int bcm6348_gpio_request_enable(struct pinctrl_dev *pctldev,
 340 +                                      struct pinctrl_gpio_range *range,
 341 +                                      unsigned offset)
 342 +{
 343 +       struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 344 +       struct pin_desc *desc;
 345 +       u32 mask;
 346 +
 347 +       /* don't reconfigure if already muxed */
 348 +       desc = pin_desc_get(pctldev, offset);
 349 +       if (desc->mux_usecount)
 350 +               return 0;
 351 +
 352 +       mask = GROUP_MASK(offset);
 353 +
 354 +       /* disable all functions using this pin */
 355 +       bcm6348_rmw_mux(pctl, mask, 0);
 356 +
 357 +       return 0;
 358 +}
 359 +
 360 +static struct pinctrl_ops bcm6348_pctl_ops = {
 361 +       .get_groups_count       = bcm6348_pinctrl_get_group_count,
 362 +       .get_group_name         = bcm6348_pinctrl_get_group_name,
 363 +       .get_group_pins         = bcm6348_pinctrl_get_group_pins,
 364 +#ifdef CONFIG_OF
 365 +       .dt_node_to_map         = pinconf_generic_dt_node_to_map_pin,
 366 +       .dt_free_map            = pinctrl_utils_free_map,
 367 +#endif
 368 +};
 369 +
 370 +static struct pinmux_ops bcm6348_pmx_ops = {
 371 +       .get_functions_count    = bcm6348_pinctrl_get_func_count,
 372 +       .get_function_name      = bcm6348_pinctrl_get_func_name,
 373 +       .get_function_groups    = bcm6348_pinctrl_get_groups,
 374 +       .set_mux                = bcm6348_pinctrl_set_mux,
 375 +       .gpio_request_enable    = bcm6348_gpio_request_enable,
 376 +       .strict                 = true,
 377 +};
 378 +
 379 +static int bcm6348_pinctrl_probe(struct platform_device *pdev)
 380 +{
 381 +       struct bcm6348_pinctrl *pctl;
 382 +       struct resource *res;
 383 +       void __iomem *mode;
 384 +
 385 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
 386 +       mode = devm_ioremap_resource(&pdev->dev, res);
 387 +       if (IS_ERR(mode))
 388 +               return PTR_ERR(mode);
 389 +
 390 +       pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
 391 +       if (!pctl)
 392 +               return -ENOMEM;
 393 +
 394 +       spin_lock_init(&pctl->lock);
 395 +
 396 +       pctl->mode = mode;
 397 +
 398 +       /* disable all muxes by default */
 399 +       __raw_writel(0, pctl->mode);
 400 +
 401 +       pctl->desc.name = dev_name(&pdev->dev);
 402 +       pctl->desc.owner = THIS_MODULE;
 403 +       pctl->desc.pctlops = &bcm6348_pctl_ops;
 404 +       pctl->desc.pmxops = &bcm6348_pmx_ops;
 405 +
 406 +       pctl->desc.npins = ARRAY_SIZE(bcm6348_pins);
 407 +       pctl->desc.pins = bcm6348_pins;
 408 +
 409 +       platform_set_drvdata(pdev, pctl);
 410 +
 411 +       pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
 412 +                                                pctl->gpio, BCM6348_NGPIO);
 413 +       if (IS_ERR(pctl->pctldev))
 414 +               return PTR_ERR(pctl->pctldev);
 415 +
 416 +       return 0;
 417 +}
 418 +
 419 +static const struct of_device_id bcm6348_pinctrl_match[] = {
 420 +       { .compatible = "brcm,bcm6348-pinctrl", },
 421 +       { },
 422 +};
 423 +
 424 +static struct platform_driver bcm6348_pinctrl_driver = {
 425 +       .probe = bcm6348_pinctrl_probe,
 426 +       .driver = {
 427 +               .name = "bcm6348-pinctrl",
 428 +               .of_match_table = bcm6348_pinctrl_match,
 429 +       },
 430 +};
 431 +
 432 +builtin_platform_driver(bcm6348_pinctrl_driver);