target/linux/ath79/patches-4.19/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch

   1 From 339c191a95e978353c9ba3aafab0261e14de109b Mon Sep 17 00:00:00 2001
   2 From: Felix Fietkau <nbd@nbd.name>
   3 Date: Tue, 6 Mar 2018 13:22:43 +0100
   4 Subject: [PATCH 22/33] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
   5  out of soc init
   6
   7 Preparation for reusing functions for DT
   8
   9 Signed-off-by: Felix Fietkau <nbd@nbd.name>
  10 Signed-off-by: John Crispin <john@phrozen.org>
  11 ---
  12  arch/mips/ath79/clock.c | 38 +++++++++++++++++---------------------
  13  1 file changed, 17 insertions(+), 21 deletions(-)
  14
  15 --- a/arch/mips/ath79/clock.c
  16 +++ b/arch/mips/ath79/clock.c
  17 @@ -110,9 +110,6 @@ static void __init ar71xx_clocks_init(vo
  18         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
  19         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
  20         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
  21 -
  22 -       clk_add_alias("wdt", NULL, "ahb", NULL);
  23 -       clk_add_alias("uart", NULL, "ahb", NULL);
  24  }
  25
  26  static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
  27 @@ -140,9 +137,6 @@ static void __init ar724x_clocks_init(vo
  28         ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
  29
  30         ar724x_clk_init(ref_clk, ath79_pll_base);
  31 -
  32 -       clk_add_alias("wdt", NULL, "ahb", NULL);
  33 -       clk_add_alias("uart", NULL, "ahb", NULL);
  34  }
  35
  36  static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
  37 @@ -218,9 +212,6 @@ static void __init ar933x_clocks_init(vo
  38         ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
  39
  40         ar9330_clk_init(ref_clk, ath79_pll_base);
  41 -
  42 -       clk_add_alias("wdt", NULL, "ahb", NULL);
  43 -       clk_add_alias("uart", NULL, "ref", NULL);
  44  }
  45
  46  static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
  47 @@ -353,9 +344,6 @@ static void __init ar934x_clocks_init(vo
  48         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
  49         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
  50
  51 -       clk_add_alias("wdt", NULL, "ref", NULL);
  52 -       clk_add_alias("uart", NULL, "ref", NULL);
  53 -
  54         iounmap(dpll_base);
  55  }
  56
  57 @@ -439,9 +427,6 @@ static void __init qca953x_clocks_init(v
  58         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
  59         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
  60         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
  61 -
  62 -       clk_add_alias("wdt", NULL, "ref", NULL);
  63 -       clk_add_alias("uart", NULL, "ref", NULL);
  64  }
  65
  66  static void __init qca955x_clocks_init(void)
  67 @@ -524,9 +509,6 @@ static void __init qca955x_clocks_init(v
  68         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
  69         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
  70         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
  71 -
  72 -       clk_add_alias("wdt", NULL, "ref", NULL);
  73 -       clk_add_alias("uart", NULL, "ref", NULL);
  74  }
  75
  76  static void __init qca956x_clocks_init(void)
  77 @@ -628,13 +610,13 @@ static void __init qca956x_clocks_init(v
  78         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
  79         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
  80         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
  81 -
  82 -       clk_add_alias("wdt", NULL, "ref", NULL);
  83 -       clk_add_alias("uart", NULL, "ref", NULL);
  84  }
  85
  86  void __init ath79_clocks_init(void)
  87  {
  88 +       const char *wdt;
  89 +       const char *uart;
  90 +
  91         if (soc_is_ar71xx())
  92                 ar71xx_clocks_init();
  93         else if (soc_is_ar724x() || soc_is_ar913x())
  94 @@ -651,6 +633,20 @@ void __init ath79_clocks_init(void)
  95                 qca956x_clocks_init();
  96         else
  97                 BUG();
  98 +
  99 +       if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
 100 +               wdt = "ahb";
 101 +               uart = "ahb";
 102 +       } else if (soc_is_ar933x()) {
 103 +               wdt = "ahb";
 104 +               uart = "ref";
 105 +       } else {
 106 +               wdt = "ref";
 107 +               uart = "ref";
 108 +       }
 109 +
 110 +       clk_add_alias("wdt", NULL, wdt, NULL);
 111 +       clk_add_alias("uart", NULL, uart, NULL);
 112  }
 113
 114  unsigned long __init