2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
10 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \
11 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
12 #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \
13 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
15 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH \
16 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
17 #define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
19 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000
22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400
23 #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800
24 #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00
26 #define RW_MGR_MEM_NUMBER_OF_RANKS 1
27 #define NUM_SHADOW_REGS 1
29 #define RW_MGR_RANK_NONE 0xFF
30 #define RW_MGR_RANK_ALL 0x00
32 #define RW_MGR_ODT_MODE_OFF 0
33 #define RW_MGR_ODT_MODE_READ_WRITE 1
35 #define NUM_CALIB_REPEAT 1
37 #define NUM_READ_TESTS 7
38 #define NUM_READ_PB_TESTS 7
39 #define NUM_WRITE_TESTS 15
40 #define NUM_WRITE_PB_TESTS 31
42 #define PASS_ALL_BITS 1
43 #define PASS_ONE_BIT 0
45 /* calibration stages */
46 #define CAL_STAGE_NIL 0
47 #define CAL_STAGE_VFIFO 1
48 #define CAL_STAGE_WLEVEL 2
49 #define CAL_STAGE_LFIFO 3
50 #define CAL_STAGE_WRITES 4
51 #define CAL_STAGE_FULLTEST 5
52 #define CAL_STAGE_REFRESH 6
53 #define CAL_STAGE_CAL_SKIPPED 7
54 #define CAL_STAGE_CAL_ABORTED 8
55 #define CAL_STAGE_VFIFO_AFTER_WRITES 9
57 /* calibration substages */
58 #define CAL_SUBSTAGE_NIL 0
59 #define CAL_SUBSTAGE_GUARANTEED_READ 1
60 #define CAL_SUBSTAGE_DQS_EN_PHASE 2
61 #define CAL_SUBSTAGE_VFIFO_CENTER 3
62 #define CAL_SUBSTAGE_WORKING_DELAY 1
63 #define CAL_SUBSTAGE_LAST_WORKING_DELAY 2
64 #define CAL_SUBSTAGE_WLEVEL_COPY 3
65 #define CAL_SUBSTAGE_WRITES_CENTER 1
66 #define CAL_SUBSTAGE_READ_LATENCY 1
67 #define CAL_SUBSTAGE_REFRESH 1
69 /* length of VFIFO, from SW_MACROS */
70 #define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
72 #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000
73 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100
74 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200
75 #define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300
76 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400
77 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500
78 #define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700
79 #define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900
81 /* HHP-HPS-specific versions of some commands */
82 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600
83 #define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800
84 #define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00
85 #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00
86 #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00
88 #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0)
89 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000)
90 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000)
91 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)
92 #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)
94 #define PHY_MGR_CAL_RESET (0)
95 #define PHY_MGR_CAL_SUCCESS (1)
96 #define PHY_MGR_CAL_FAIL (2)
98 #define CALIB_SKIP_DELAY_LOOPS (1 << 0)
99 #define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
100 #define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
101 #define CALIB_SKIP_VFIFO (1 << 3)
102 #define CALIB_SKIP_LFIFO (1 << 4)
103 #define CALIB_SKIP_WLEVEL (1 << 5)
104 #define CALIB_SKIP_WRITES (1 << 6)
105 #define CALIB_SKIP_FULL_TEST (1 << 7)
106 #define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
107 CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
108 CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
109 #define CALIB_IN_RTL_SIM (1 << 8)
111 /* Scan chain manager command addresses */
112 #define READ_SCC_OCT_OUT2_DELAY 0
113 #define READ_SCC_DQ_OUT2_DELAY 0
114 #define READ_SCC_DQS_IO_OUT2_DELAY 0
115 #define READ_SCC_DM_IO_OUT2_DELAY 0
117 /* HHP-HPS-specific values */
118 #define SCC_MGR_HHP_EXTRAS_OFFSET 0
119 #define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
121 /* PHY Debug mode flag constants */
122 #define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
123 #define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
124 #define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
125 #define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
126 #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
127 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
129 /* Init and Reset delay constants - Only use if defined by sequencer_defines.h,
130 * otherwise, revert to defaults
131 * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 =
134 #ifdef TINIT_CNTR0_VAL
135 #define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
137 #define SEQ_TINIT_CNTR0_VAL 0
140 #ifdef TINIT_CNTR1_VAL
141 #define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
143 #define SEQ_TINIT_CNTR1_VAL 202
146 #ifdef TINIT_CNTR2_VAL
147 #define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
149 #define SEQ_TINIT_CNTR2_VAL 131
153 /* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 =
156 #ifdef TRESET_CNTR0_VAL
157 #define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
159 #define SEQ_TRESET_CNTR0_VAL 2
162 #ifdef TRESET_CNTR1_VAL
163 #define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
165 #define SEQ_TRESET_CNTR1_VAL 252
168 #ifdef TRESET_CNTR2_VAL
169 #define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
171 #define SEQ_TRESET_CNTR2_VAL 131
174 struct socfpga_sdr_rw_load_manager {
181 struct socfpga_sdr_rw_load_jump_manager {
188 struct socfpga_sdr_reg_file {
197 u32 trk_sample_count;
201 u32 trk_read_dqs_width;
205 /* parameter variable holder */
207 u32 read_correct_mask;
208 u32 read_correct_mask_vg;
209 u32 write_correct_mask;
210 u32 write_correct_mask_vg;
214 /* global variable holder */
216 uint32_t phy_debug_mode_flags;
218 /* current read latency */
220 uint32_t curr_read_lat;
224 uint32_t error_substage;
225 uint32_t error_stage;
226 uint32_t error_group;
228 /* figure-of-merit in, figure-of-merit out */
233 /*USER Number of RW Mgr NOP cycles between
234 write command and write data */
235 uint32_t rw_wl_nop_cycles;
238 struct socfpga_sdr_scc_mgr {
249 /* PHY manager configuration registers. */
250 struct socfpga_phy_mgr_cfg {
256 u32 vfifo_rd_en_ovrd;
261 /* PHY manager command addresses. */
262 struct socfpga_phy_mgr_cmd {
264 u32 inc_vfifo_hard_phy;
270 struct socfpga_data_mgr {
276 #endif /* _SEQUENCER_H_ */