1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
9 #include <asm/arch/clock.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/arch/soc.h>
12 #include <asm/arch-fsl-layerscape/fsl_icid.h>
13 #include <fdt_support.h>
19 #include <fsl_esdhc.h>
26 #include <asm/arch/ppa.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 int board_early_init_f(void)
32 fsl_lsch2_early_init_f();
37 #ifndef CONFIG_SPL_BUILD
41 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
42 #ifndef CONFIG_SD_BOOT
43 u8 cfg_rcw_src1, cfg_rcw_src2;
48 printf("Board: LS1043ARDB, boot from ");
53 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
54 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
55 cpld_rev_bit(&cfg_rcw_src1);
56 cfg_rcw_src = cfg_rcw_src1;
57 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
59 if (cfg_rcw_src == 0x25)
60 printf("vBank %d\n", CPLD_READ(vbank));
61 else if (cfg_rcw_src == 0x106)
64 printf("Invalid setting of SW4\n");
67 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
68 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
70 puts("SERDES Reference Clocks:\n");
71 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
72 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
79 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
81 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
86 init_final_memctl_regs();
89 #ifdef CONFIG_SECURE_BOOT
90 /* In case of Secure Boot, the IBR configures the SMMU
91 * to allow only Secure transactions.
92 * SMMU must be reset in bypass mode.
93 * Set the ClientPD bit and Clear the USFCFG Bit
96 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
97 out_le32(SMMU_SCR0, val);
98 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
99 out_le32(SMMU_NSCR0, val);
102 #ifdef CONFIG_FSL_CAAM
106 #ifdef CONFIG_FSL_LS_PPA
113 /* invert AQR105 IRQ pins polarity */
114 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
119 int config_board_mux(void)
121 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
124 if (hwconfig("qe-hdlc")) {
125 out_be32(&scfg->rcwpmuxcr0,
126 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
127 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
128 in_be32(&scfg->rcwpmuxcr0));
130 #ifdef CONFIG_HAS_FSL_XHCI_USB
131 out_be32(&scfg->rcwpmuxcr0, 0x3333);
132 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
133 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
134 SCFG_USBPWRFAULT_USB3_SHIFT) |
135 (SCFG_USBPWRFAULT_DEDICATED <<
136 SCFG_USBPWRFAULT_USB2_SHIFT) |
137 (SCFG_USBPWRFAULT_SHARED <<
138 SCFG_USBPWRFAULT_USB1_SHIFT);
139 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
145 #if defined(CONFIG_MISC_INIT_R)
146 int misc_init_r(void)
153 void fdt_del_qe(void *blob)
157 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
159 fdt_del_node(blob, nodeoff);
163 int ft_board_setup(void *blob, bd_t *bd)
165 u64 base[CONFIG_NR_DRAM_BANKS];
166 u64 size[CONFIG_NR_DRAM_BANKS];
168 /* fixup DT for the two DDR banks */
169 base[0] = gd->bd->bi_dram[0].start;
170 size[0] = gd->bd->bi_dram[0].size;
171 base[1] = gd->bd->bi_dram[1].start;
172 size[1] = gd->bd->bi_dram[1].size;
174 fdt_fixup_memory_banks(blob, base, size, 2);
175 ft_cpu_setup(blob, bd);
177 #ifdef CONFIG_SYS_DPAA_FMAN
178 fdt_fixup_fman_ethernet(blob);
181 fdt_fixup_icid(blob);
184 * qe-hdlc and usb multi-use the pins,
185 * when set hwconfig to qe-hdlc, delete usb node.
187 if (hwconfig("qe-hdlc"))
188 #ifdef CONFIG_HAS_FSL_XHCI_USB
189 fdt_del_node_and_alias(blob, "usb1");
192 * qe just support qe-uart and qe-hdlc,
193 * if qe-uart and qe-hdlc are not set in hwconfig,
196 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
202 u8 flash_read8(void *addr)
204 return __raw_readb(addr + 1);
207 void flash_write16(u16 val, void *addr)
209 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
211 __raw_writew(shftval, addr);
214 u16 flash_read16(void *addr)
216 u16 val = __raw_readw(addr);
218 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);