1 menu "x86 architecture"
8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
20 experimental and is missing a lot of features.
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
29 memory can be accessed through normal means, although
30 arch_phys_memset() can be used for basic access to other memory.
36 select SPL_SEPARATE_BSS
38 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
39 experimental and many features are missing. U-Boot SPL starts up,
40 runs through the 16-bit and 32-bit init, then switches to 64-bit
41 mode and jumps to U-Boot proper.
53 prompt "Mainboard vendor"
54 default VENDOR_EMULATION
56 config VENDOR_ADVANTECH
59 config VENDOR_CONGATEC
62 config VENDOR_COREBOOT
71 config VENDOR_EMULATION
82 # subarchitectures-specific options below
84 bool "Intel MID platform support"
88 Select to build a U-Boot capable of supporting Intel MID
89 (Mobile Internet Device) platform systems which do not have
90 the PCI legacy interfaces.
92 If you are building for a PC class system say N here.
94 Intel MID platforms are based on an Intel processor and
95 chipset which consume less power than most of the x86
98 # board-specific options below
99 source "board/advantech/Kconfig"
100 source "board/congatec/Kconfig"
101 source "board/coreboot/Kconfig"
102 source "board/dfi/Kconfig"
103 source "board/efi/Kconfig"
104 source "board/emulation/Kconfig"
105 source "board/google/Kconfig"
106 source "board/intel/Kconfig"
108 # platform-specific options below
109 source "arch/x86/cpu/baytrail/Kconfig"
110 source "arch/x86/cpu/braswell/Kconfig"
111 source "arch/x86/cpu/broadwell/Kconfig"
112 source "arch/x86/cpu/coreboot/Kconfig"
113 source "arch/x86/cpu/ivybridge/Kconfig"
114 source "arch/x86/cpu/efi/Kconfig"
115 source "arch/x86/cpu/qemu/Kconfig"
116 source "arch/x86/cpu/quark/Kconfig"
117 source "arch/x86/cpu/queensbay/Kconfig"
118 source "arch/x86/cpu/slimbootloader/Kconfig"
119 source "arch/x86/cpu/tangier/Kconfig"
121 # architecture-specific options below
126 config SYS_MALLOC_F_LEN
135 depends on X86_RESET_VECTOR
144 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
153 config X86_RESET_VECTOR
158 # The following options control where the 16-bit and 32-bit init lies
159 # If SPL is enabled then it normally holds this init code, and U-Boot proper
160 # is normally a 64-bit build.
162 # The 16-bit init refers to the reset vector and the small amount of code to
163 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
164 # or missing altogether if U-Boot is started from EFI or coreboot.
166 # The 32-bit init refers to processor init, running binary blobs including
167 # FSP, setting up interrupts and anything else that needs to be done in
168 # 32-bit code. It is normally in the same place as 16-bit init if that is
169 # enabled (i.e. they are both in SPL, or both in U-Boot proper).
170 config X86_16BIT_INIT
172 depends on X86_RESET_VECTOR
173 default y if X86_RESET_VECTOR && !SPL
175 This is enabled when 16-bit init is in U-Boot proper
177 config SPL_X86_16BIT_INIT
179 depends on X86_RESET_VECTOR
180 default y if X86_RESET_VECTOR && SPL && !TPL
182 This is enabled when 16-bit init is in SPL
184 config TPL_X86_16BIT_INIT
186 depends on X86_RESET_VECTOR
187 default y if X86_RESET_VECTOR && TPL
189 This is enabled when 16-bit init is in TPL
191 config X86_32BIT_INIT
193 depends on X86_RESET_VECTOR
194 default y if X86_RESET_VECTOR && !SPL
196 This is enabled when 32-bit init is in U-Boot proper
198 config SPL_X86_32BIT_INIT
200 depends on X86_RESET_VECTOR
201 default y if X86_RESET_VECTOR && SPL
203 This is enabled when 32-bit init is in SPL
205 config RESET_SEG_START
207 depends on X86_RESET_VECTOR
212 depends on X86_RESET_VECTOR
215 config SYS_X86_START16
217 depends on X86_RESET_VECTOR
220 config X86_LOAD_FROM_32_BIT
221 bool "Boot from a 32-bit program"
223 Define this to boot U-Boot from a 32-bit program which sets
224 the GDT differently. This can be used to boot directly from
225 any stage of coreboot, for example, bypassing the normal
226 payload-loading feature.
228 config BOARD_ROMSIZE_KB_512
230 config BOARD_ROMSIZE_KB_1024
232 config BOARD_ROMSIZE_KB_2048
234 config BOARD_ROMSIZE_KB_4096
236 config BOARD_ROMSIZE_KB_8192
238 config BOARD_ROMSIZE_KB_16384
242 prompt "ROM chip size"
243 depends on X86_RESET_VECTOR
244 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
245 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
246 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
247 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
248 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
249 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
251 Select the size of the ROM chip you intend to flash U-Boot on.
253 The build system will take care of creating a u-boot.rom file
254 of the matching size.
256 config UBOOT_ROMSIZE_KB_512
259 Choose this option if you have a 512 KB ROM chip.
261 config UBOOT_ROMSIZE_KB_1024
262 bool "1024 KB (1 MB)"
264 Choose this option if you have a 1024 KB (1 MB) ROM chip.
266 config UBOOT_ROMSIZE_KB_2048
267 bool "2048 KB (2 MB)"
269 Choose this option if you have a 2048 KB (2 MB) ROM chip.
271 config UBOOT_ROMSIZE_KB_4096
272 bool "4096 KB (4 MB)"
274 Choose this option if you have a 4096 KB (4 MB) ROM chip.
276 config UBOOT_ROMSIZE_KB_8192
277 bool "8192 KB (8 MB)"
279 Choose this option if you have a 8192 KB (8 MB) ROM chip.
281 config UBOOT_ROMSIZE_KB_16384
282 bool "16384 KB (16 MB)"
284 Choose this option if you have a 16384 KB (16 MB) ROM chip.
288 # Map the config names to an integer (KB).
289 config UBOOT_ROMSIZE_KB
291 default 512 if UBOOT_ROMSIZE_KB_512
292 default 1024 if UBOOT_ROMSIZE_KB_1024
293 default 2048 if UBOOT_ROMSIZE_KB_2048
294 default 4096 if UBOOT_ROMSIZE_KB_4096
295 default 8192 if UBOOT_ROMSIZE_KB_8192
296 default 16384 if UBOOT_ROMSIZE_KB_16384
298 # Map the config names to a hex value (bytes).
301 default 0x80000 if UBOOT_ROMSIZE_KB_512
302 default 0x100000 if UBOOT_ROMSIZE_KB_1024
303 default 0x200000 if UBOOT_ROMSIZE_KB_2048
304 default 0x400000 if UBOOT_ROMSIZE_KB_4096
305 default 0x800000 if UBOOT_ROMSIZE_KB_8192
306 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
307 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
310 bool "Platform requires Intel Management Engine"
312 Newer higher-end devices have an Intel Management Engine (ME)
313 which is a very large binary blob (typically 1.5MB) which is
314 required for the platform to work. This enforces a particular
315 SPI flash format. You will need to supply the me.bin file in
316 your board directory.
319 bool "Perform a simple RAM test after SDRAM initialisation"
321 If there is something wrong with SDRAM then the platform will
322 often crash within U-Boot or the kernel. This option enables a
323 very simple RAM test that quickly checks whether the SDRAM seems
324 to work correctly. It is not exhaustive but can save time by
325 detecting obvious failures.
327 config FLASH_DESCRIPTOR_FILE
328 string "Flash descriptor binary filename"
329 depends on HAVE_INTEL_ME
330 default "descriptor.bin"
332 The filename of the file to use as flash descriptor in the
336 string "Intel Management Engine binary filename"
337 depends on HAVE_INTEL_ME
340 The filename of the file to use as Intel Management Engine in the
344 bool "Use HOB (Hand-Off Block)"
346 Select this option to access HOB (Hand-Off Block) data structures
347 and parse HOBs. This HOB infra structure can be reused with
348 different solutions across different platforms.
351 bool "Add an Firmware Support Package binary"
355 Select this option to add an Firmware Support Package binary to
356 the resulting U-Boot image. It is a binary blob which U-Boot uses
357 to set up SDRAM and other chipset specific initialization.
359 Note: Without this binary U-Boot will not be able to set up its
360 SDRAM so will not boot.
363 bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up"
364 default y if !HAVE_FSP
366 Select this option if your board uses CAR init code, typically in a
367 car.S file, to get some initial memory for code execution. This is
368 common with Intel CPUs which don't use FSP.
375 Selects the FSP version to use. Intel has published several versions
376 of the FSP External Architecture Specification and this allows
377 selection of the version number used by a particular SoC.
380 bool "FSP version 1.x"
382 This covers versions 1.0 and 1.1a. See here for details:
383 https://github.com/IntelFsp/fsp/wiki
386 bool "FSP version 2.x"
388 This covers versions 2.0 and 2.1. See here for details:
389 https://github.com/IntelFsp/fsp/wiki
394 string "Firmware Support Package binary filename"
395 depends on FSP_VERSION1
398 The filename of the file to use as Firmware Support Package binary
399 in the board directory.
402 hex "Firmware Support Package binary location"
403 depends on FSP_VERSION1
406 FSP is not Position Independent Code (PIC) and the whole FSP has to
407 be rebased if it is placed at a location which is different from the
408 perferred base address specified during the FSP build. Use Intel's
409 Binary Configuration Tool (BCT) to do the rebase.
411 The default base address of 0xfffc0000 indicates that the binary must
412 be located at offset 0xc0000 from the beginning of a 1MB flash device.
414 config FSP_TEMP_RAM_ADDR
416 depends on FSP_VERSION1
419 Stack top address which is used in fsp_init() after DRAM is ready and
422 config FSP_SYS_MALLOC_F_LEN
424 depends on FSP_VERSION1
427 Additional size of malloc() pool before relocation.
431 depends on FSP_VERSION1
434 Most FSPs use UPD data region for some FSP customization. But there
435 are still some FSPs that might not even have UPD. For such FSPs,
436 override this to n in their platform Kconfig files.
438 config FSP_BROKEN_HOB
440 depends on FSP_VERSION1
442 Indicate some buggy FSPs that does not report memory used by FSP
443 itself as reserved in the resource descriptor HOB. Select this to
444 tell U-Boot to do some additional work to ensure U-Boot relocation
445 do not overwrite the important boot service data which is used by
446 FSP, otherwise the subsequent call to fsp_notify() will fail.
448 config ENABLE_MRC_CACHE
449 bool "Enable MRC cache"
450 depends on !EFI && !SYS_COREBOOT
452 Enable this feature to cause MRC data to be cached in NV storage
453 to be used for speeding up boot time on future reboots and/or
456 For platforms that use Intel FSP for the memory initialization,
457 please check FSP output HOB via U-Boot command 'fsp hob' to see
458 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
459 If such GUID does not exist, MRC cache is not available on such
460 platform (eg: Intel Queensbay), which means selecting this option
461 here does not make any difference.
464 bool "Add a System Agent binary"
467 Select this option to add a System Agent binary to
468 the resulting U-Boot image. MRC stands for Memory Reference Code.
469 It is a binary blob which U-Boot uses to set up SDRAM.
471 Note: Without this binary U-Boot will not be able to set up its
472 SDRAM so will not boot.
479 Enable caching for the memory reference code binary. This uses an
480 MTRR (memory type range register) to turn on caching for the section
481 of SPI flash that contains the memory reference code. This makes
482 SDRAM init run faster.
484 config CACHE_MRC_SIZE_KB
489 Sets the size of the cached area for the memory reference code.
490 This ends at the end of SPI flash (address 0xffffffff) and is
491 measured in KB. Typically this is set to 512, providing for 0.5MB
494 config DCACHE_RAM_BASE
498 Sets the base of the data cache area in memory space. This is the
499 start address of the cache-as-RAM (CAR) area and the address varies
500 depending on the CPU. Once CAR is set up, read/write memory becomes
501 available at this address and can be used temporarily until SDRAM
504 config DCACHE_RAM_SIZE
509 Sets the total size of the data cache area in memory space. This
510 sets the size of the cache-as-RAM (CAR) area. Note that much of the
511 CAR space is required by the MRC. The CAR space available to U-Boot
512 is normally at the start and typically extends to 1/4 or 1/2 of the
515 config DCACHE_RAM_MRC_VAR_SIZE
519 This is the amount of CAR (Cache as RAM) reserved for use by the
520 memory reference code. This depends on the implementation of the
521 memory reference code and must be set correctly or the board will
525 bool "Add a Reference Code binary"
527 Select this option to add a Reference Code binary to the resulting
528 U-Boot image. This is an Intel binary blob that handles system
529 initialisation, in this case the PCH and System Agent.
531 Note: Without this binary (on platforms that need it such as
532 broadwell) U-Boot will be missing some critical setup steps.
533 Various peripherals may fail to work.
536 bool "Enable Symmetric Multiprocessing"
539 Enable use of more than one CPU in U-Boot and the Operating System
540 when loaded. Each CPU will be started up and information can be
541 obtained using the 'cpu' command. If this option is disabled, then
542 only one CPU will be enabled regardless of the number of CPUs
546 int "Maximum number of CPUs permitted"
550 When using multi-CPU chips it is possible for U-Boot to start up
551 more than one CPU. The stack memory used by all of these CPUs is
552 pre-allocated so at present U-Boot wants to know the maximum
553 number of CPUs that may be present. Set this to at least as high
554 as the number of CPUs in your system (it uses about 4KB of RAM for
562 Each additional CPU started by U-Boot requires its own stack. This
563 option sets the stack size used by each CPU and directly affects
564 the memory used by this initialisation process. Typically 4KB is
567 config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
570 This option indicates that the turbo mode setting is not package
571 scoped. i.e. turbo_enable() needs to be called on not just the
572 bootstrap processor (BSP).
575 bool "Add a VGA BIOS image"
577 Select this option if you have a VGA BIOS image that you would
578 like to add to your ROM.
581 string "VGA BIOS image filename"
582 depends on HAVE_VGA_BIOS
585 The filename of the VGA BIOS image in the board directory.
588 hex "VGA BIOS image location"
589 depends on HAVE_VGA_BIOS
592 The location of VGA BIOS image in the SPI flash. For example, base
593 address of 0xfff90000 indicates that the image will be put at offset
594 0x90000 from the beginning of a 1MB flash device.
597 bool "Add a Video BIOS Table (VBT) image"
598 depends on FSP_VERSION1
600 Select this option if you have a Video BIOS Table (VBT) image that
601 you would like to add to your ROM. This is normally required if you
602 are using an Intel FSP firmware that is complaint with spec 1.1 or
603 later to initialize the integrated graphics device (IGD).
605 Video BIOS Table, or VBT, provides platform and board specific
606 configuration information to the driver that is not discoverable
607 or available through other means. By other means the most used
608 method here is to read EDID table from the attached monitor, over
609 Display Data Channel (DDC) using two pin I2C serial interface. VBT
610 configuration is related to display hardware and is available via
611 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
614 string "Video BIOS Table (VBT) image filename"
618 The filename of the file to use as Video BIOS Table (VBT) image
619 in the board directory.
622 hex "Video BIOS Table (VBT) image location"
626 The location of Video BIOS Table (VBT) image in the SPI flash. For
627 example, base address of 0xfff90000 indicates that the image will
628 be put at offset 0x90000 from the beginning of a 1MB flash device.
631 bool "Enable FSP framebuffer driver support"
632 depends on HAVE_VBT && DM_VIDEO
634 Turn on this option to enable a framebuffer driver when U-Boot is
635 using Video BIOS Table (VBT) image for FSP firmware to initialize
636 the integrated graphics device.
638 config ROM_TABLE_ADDR
642 All x86 tables happen to like the address range from 0x0f0000
643 to 0x100000. We use 0xf0000 as the starting address to store
644 those tables, including PIRQ routing table, Multi-Processor
645 table and ACPI table.
647 config ROM_TABLE_SIZE
652 depends on !EFI && !SYS_COREBOOT
654 config GENERATE_PIRQ_TABLE
655 bool "Generate a PIRQ table"
658 Generate a PIRQ routing table for this board. The PIRQ routing table
659 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
660 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
661 It specifies the interrupt router information as well how all the PCI
662 devices' interrupt pins are wired to PIRQs.
664 config GENERATE_SFI_TABLE
665 bool "Generate a SFI (Simple Firmware Interface) table"
667 The Simple Firmware Interface (SFI) provides a lightweight method
668 for platform firmware to pass information to the operating system
669 via static tables in memory. Kernel SFI support is required to
670 boot on SFI-only platforms. If you have ACPI tables then these are
673 U-Boot writes this table in write_sfi_table() just before booting
676 For more information, see http://simplefirmware.org
678 config GENERATE_MP_TABLE
679 bool "Generate an MP (Multi-Processor) table"
682 Generate an MP (Multi-Processor) table for this board. The MP table
683 provides a way for the operating system to support for symmetric
684 multiprocessing as well as symmetric I/O interrupt handling with
685 the local APIC and I/O APIC.
687 config GENERATE_ACPI_TABLE
688 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
692 The Advanced Configuration and Power Interface (ACPI) specification
693 provides an open standard for device configuration and management
694 by the operating system. It defines platform-independent interfaces
695 for configuration and power management monitoring.
699 config HAVE_ACPI_RESUME
700 bool "Enable ACPI S3 resume"
701 select ENABLE_MRC_CACHE
703 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
704 state where all system context is lost except system memory. U-Boot
705 is responsible for restoring the machine state as it was before sleep.
706 It needs restore the memory controller, without overwriting memory
707 which is not marked as reserved. For the peripherals which lose their
708 registers, U-Boot needs to write the original value. When everything
709 is done, U-Boot needs to find out the wakeup vector provided by OSes
712 config S3_VGA_ROM_RUN
713 bool "Re-run VGA option ROMs on S3 resume"
714 depends on HAVE_ACPI_RESUME
716 Execute VGA option ROMs in U-Boot when resuming from S3. Normally
717 this is needed when graphics console is being used in the kernel.
719 Turning it off can reduce some resume time, but be aware that your
720 graphics console won't work without VGA options ROMs. Set it to N
721 if your kernel is only on a serial console.
725 depends on HAVE_ACPI_RESUME
728 Estimated U-Boot's runtime stack size that needs to be reserved
729 during an ACPI S3 resume.
731 config MAX_PIRQ_LINKS
735 This variable specifies the number of PIRQ interrupt links which are
736 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
737 Some newer chipsets offer more than four links, commonly up to PIRQH.
739 config IRQ_SLOT_COUNT
743 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
744 which in turns forms a table of exact 4KiB. The default value 128
745 should be enough for most boards. If this does not fit your board,
746 change it according to your needs.
748 config PCIE_ECAM_BASE
752 This is the memory-mapped address of PCI configuration space, which
753 is only available through the Enhanced Configuration Access
754 Mechanism (ECAM) with PCI Express. It can be set up almost
755 anywhere. Before it is set up, it is possible to access PCI
756 configuration space through I/O access, but memory access is more
757 convenient. Using this, PCI can be scanned and configured. This
758 should be set to a region that does not conflict with memory
759 assigned to PCI devices - i.e. the memory and prefetch regions, as
760 passed to pci_set_region().
762 config PCIE_ECAM_SIZE
766 This is the size of memory-mapped address of PCI configuration space,
767 which is only available through the Enhanced Configuration Access
768 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
769 so a default 0x10000000 size covers all of the 256 buses which is the
770 maximum number of PCI buses as defined by the PCI specification.
773 bool "Enable Intel 8259 compatible interrupt controller"
776 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
777 slave) interrupt controllers. Include this to have U-Boot set up
778 the interrupt correctly.
781 bool "Enable Intel Advanced Programmable Interrupt Controller"
784 The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
785 for catching interrupts and distributing them to one or more CPU
786 cores. In most cases there are some LAPICs (local) for each core and
787 one I/O APIC. This conjunction is found on most modern x86 systems.
792 Intel ICH6 compatible chipset pinctrl driver. It needs to work
793 together with the ICH6 compatible gpio driver.
799 Intel 8254 timer contains three counters which have fixed uses.
800 Include this to have U-Boot set up the timer correctly.
803 bool "Support booting SeaBIOS"
805 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
806 It can run in an emulator or natively on X86 hardware with the use
807 of coreboot/U-Boot. By turning on this option, U-Boot prepares
808 all the configuration tables that are necessary to boot SeaBIOS.
810 Check http://www.seabios.org/SeaBIOS for details.
812 config HIGH_TABLE_SIZE
813 hex "Size of configuration tables which reside in high memory"
817 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
818 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
819 puts a copy of configuration tables in high memory region which
820 is reserved on the stack before relocation. The region size is
821 determined by this option.
823 Increse it if the default size does not fit the board's needs.
824 This is most likely due to a large ACPI DSDT table is used.