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riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL
authorRick Chen <rick@andestech.com>
Thu, 14 Nov 2019 05:52:25 +0000 (13:52 +0800)
committerAndes <uboot@andestech.com>
Tue, 10 Dec 2019 00:23:10 +0000 (08:23 +0800)
commit8ba595b6bda56eac15d721554ea0ab8fc6a48f73
treeaf8b3931b445a7fac6e79195923aa302ab7829a5tree | snapshot
parent43a0832ba09068d1ab0628afbe62e498450ece63commit | diff
riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
arch/riscv/cpu/ax25/cache.c diff | blob | history
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