1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU208
5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
19 model = "ZynqMP ZCU208 RevA";
20 compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp";
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
38 xlnx,eeprom = &eeprom;
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
47 compatible = "gpio-keys";
51 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
52 linux,code = <KEY_DOWN>;
59 compatible = "gpio-leds";
62 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "heartbeat";
68 compatible = "iio-hwmon";
69 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
71 ina226-vccint-io-bram-ps {
72 compatible = "iio-hwmon";
73 io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
76 compatible = "iio-hwmon";
77 io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
80 compatible = "iio-hwmon";
81 io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
84 compatible = "iio-hwmon";
85 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
88 compatible = "iio-hwmon";
89 io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
92 compatible = "iio-hwmon";
93 io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
96 compatible = "iio-hwmon";
97 io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
100 compatible = "iio-hwmon";
101 io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
104 compatible = "iio-hwmon";
105 io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
108 compatible = "iio-hwmon";
109 io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
112 compatible = "iio-hwmon";
113 io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
116 compatible = "iio-hwmon";
117 io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
120 compatible = "iio-hwmon";
121 io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
163 phy-handle = <&phy0>;
164 phy-mode = "rgmii-id";
165 phy0: ethernet-phy@c {
167 ti,rx-internal-delay = <0x8>;
168 ti,tx-internal-delay = <0xa>;
169 ti,fifo-depth = <0x1>;
170 ti,dp83867-rxctrl-strap-quirk;
176 gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
177 "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
178 "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
179 "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
180 "", "", "BUTTON", "LED", "", /* 20 - 24 */
181 "", "PMU_INPUT", "", "", "", /* 25 - 29 */
182 "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
183 "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
184 "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
185 "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
186 "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
187 "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
188 "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
189 "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
190 "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
191 "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
192 "", "", /* 78 - 79 */
193 "", "", "", "", "", /* 80 - 84 */
194 "", "", "", "", "", /* 85 -89 */
195 "", "", "", "", "", /* 90 - 94 */
196 "", "", "", "", "", /* 95 - 99 */
197 "", "", "", "", "", /* 100 - 104 */
198 "", "", "", "", "", /* 105 - 109 */
199 "", "", "", "", "", /* 110 - 114 */
200 "", "", "", "", "", /* 115 - 119 */
201 "", "", "", "", "", /* 120 - 124 */
202 "", "", "", "", "", /* 125 - 129 */
203 "", "", "", "", "", /* 130 - 134 */
204 "", "", "", "", "", /* 135 - 139 */
205 "", "", "", "", "", /* 140 - 144 */
206 "", "", "", "", "", /* 145 - 149 */
207 "", "", "", "", "", /* 150 - 154 */
208 "", "", "", "", "", /* 155 - 159 */
209 "", "", "", "", "", /* 160 - 164 */
210 "", "", "", "", "", /* 165 - 169 */
211 "", "", "", ""; /* 170 - 174 */
216 clock-frequency = <400000>;
218 tca6416_u15: gpio@20 { /* u15 */
219 compatible = "ti,tca6416";
221 gpio-controller; /* interrupt not connected */
223 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
224 "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
225 "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
226 "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
229 i2c-mux@75 { /* u17 */
230 compatible = "nxp,pca9544";
231 #address-cells = <1>;
235 #address-cells = <1>;
239 /* PMBUS_ALERT done via pca9544 */
240 vccint: ina226@40 { /* u65 */
241 compatible = "ti,ina226";
242 #io-channel-cells = <1>;
243 label = "ina226-vccint";
245 shunt-resistor = <5000>;
247 vccint_io_bram_ps: ina226@41 { /* u57 */
248 compatible = "ti,ina226";
249 #io-channel-cells = <1>;
250 label = "ina226-vccint-io-bram-ps";
252 shunt-resistor = <5000>;
254 vcc1v8: ina226@42 { /* u60 */
255 compatible = "ti,ina226";
256 #io-channel-cells = <1>;
257 label = "ina226-vcc1v8";
259 shunt-resistor = <2000>;
261 vcc1v2: ina226@43 { /* u58 */
262 compatible = "ti,ina226";
263 #io-channel-cells = <1>;
264 label = "ina226-vcc1v2";
266 shunt-resistor = <5000>;
268 vadj_fmc: ina226@45 { /* u62 */
269 compatible = "ti,ina226";
270 #io-channel-cells = <1>;
271 label = "ina226-vadj-fmc";
273 shunt-resistor = <5000>;
275 mgtavcc: ina226@46 { /* u67 */
276 compatible = "ti,ina226";
277 #io-channel-cells = <1>;
278 label = "ina226-mgtavcc";
280 shunt-resistor = <2000>;
282 mgt1v2: ina226@47 { /* u63 */
283 compatible = "ti,ina226";
284 #io-channel-cells = <1>;
285 label = "ina226-mgt1v2";
287 shunt-resistor = <5000>;
289 mgt1v8: ina226@48 { /* u64 */
290 compatible = "ti,ina226";
291 #io-channel-cells = <1>;
292 label = "ina226-mgt1v8";
294 shunt-resistor = <5000>;
296 vccint_ams: ina226@49 { /* u61 */
297 compatible = "ti,ina226";
298 #io-channel-cells = <1>;
299 label = "ina226-vccint-ams";
301 shunt-resistor = <5000>;
303 dac_avtt: ina226@4a { /* u59 */
304 compatible = "ti,ina226";
305 #io-channel-cells = <1>;
306 label = "ina226-dac-avtt";
308 shunt-resistor = <5000>;
310 dac_avccaux: ina226@4b { /* u124 */
311 compatible = "ti,ina226";
312 #io-channel-cells = <1>;
313 label = "ina226-dac-avccaux";
315 shunt-resistor = <5000>;
317 adc_avcc: ina226@4c { /* u75 */
318 compatible = "ti,ina226";
319 #io-channel-cells = <1>;
320 label = "ina226-adc-avcc";
322 shunt-resistor = <5000>;
324 adc_avccaux: ina226@4d { /* u71 */
325 compatible = "ti,ina226";
326 #io-channel-cells = <1>;
327 label = "ina226-adc-avccaux";
329 shunt-resistor = <5000>;
331 dac_avcc: ina226@4e { /* u77 */
332 compatible = "ti,ina226";
333 #io-channel-cells = <1>;
334 label = "ina226-dac-avcc";
336 shunt-resistor = <5000>;
340 #address-cells = <1>;
346 #address-cells = <1>;
349 /* u104 - ir35215 0x10/0x40 */
350 /* u127 - ir38164 0x1b/0x4b */
351 /* u112 - ir38164 0x13/0x43 */
352 /* u123 - ir38164 0x1c/0x4c */
354 irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
355 compatible = "infineon,irps5401";
356 reg = <0x44>; /* i2c addr 0x14 */
358 irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
359 compatible = "infineon,irps5401";
360 reg = <0x45>; /* i2c addr 0x15 */
366 #address-cells = <1>;
377 clock-frequency = <400000>;
380 compatible = "nxp,pca9548"; /* u20 */
381 #address-cells = <1>;
384 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
386 #address-cells = <1>;
390 * IIC_EEPROM 1kB memory which uses 256B blocks
391 * where every block has different address.
392 * 0 - 256B address 0x54
393 * 256B - 512B address 0x55
394 * 512B - 768B address 0x56
395 * 768B - 1024B address 0x57
397 eeprom: eeprom@54 { /* u21 */
398 compatible = "atmel,24c128";
403 #address-cells = <1>;
406 si5341: clock-generator@36 { /* SI5341 - u43 */
407 compatible = "si5341";
412 i2c_si570_user_c0: i2c@2 {
413 #address-cells = <1>;
416 si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
418 compatible = "silabs,si570";
420 temperature-stability = <50>;
421 factory-fout = <300000000>;
422 clock-frequency = <300000000>;
423 clock-output-names = "si570_user_c0";
426 i2c_si570_mgt: i2c@3 {
427 #address-cells = <1>;
430 si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
432 compatible = "silabs,si570";
434 temperature-stability = <50>;
435 factory-fout = <156250000>;
436 clock-frequency = <148500000>;
437 clock-output-names = "si570_mgt";
441 #address-cells = <1>;
444 /* U409B - 8a34001 */
447 #address-cells = <1>;
453 #address-cells = <1>;
456 /* RFMCP connector */
462 compatible = "nxp,pca9548"; /* u22 */
463 #address-cells = <1>;
466 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
468 #address-cells = <1>;
473 i2c_si570_user_c1: i2c@1 {
474 #address-cells = <1>;
477 si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
479 compatible = "silabs,si570";
481 temperature-stability = <50>;
482 factory-fout = <300000000>;
483 clock-frequency = <300000000>;
484 clock-output-names = "si570_user_c1";
488 #address-cells = <1>;
494 #address-cells = <1>;
500 #address-cells = <1>;
506 #address-cells = <1>;
512 #address-cells = <1>;
518 #address-cells = <1>;
531 compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
532 #address-cells = <1>;
535 spi-tx-bus-width = <1>;
536 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
537 spi-max-frequency = <108000000>; /* Based on DC1 spec */
547 /* SATA OOB timing settings */
548 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
549 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
550 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
551 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
552 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
553 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
554 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
555 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
556 phy-names = "sata-phy";
557 phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
560 /* SD1 with level shifter */
565 * This property should be removed for supporting UHS mode
579 /* ULPI SMSC USB3320 */
587 snps,usb3_lpm_capable;
588 phy-names = "usb3-phy";
589 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;