arch/arm/dts/hi3798cv200.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * DTS File for HiSilicon Hi3798cv200 SoC.
   4  *
   5  * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
   6  */
   7
   8 #include <dt-bindings/clock/histb-clock.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/reset/ti-syscon.h>
  11
  12 / {
  13         compatible = "hisilicon,hi3798cv200";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         psci {
  19                 compatible = "arm,psci-0.2";
  20                 method = "smc";
  21         };
  22
  23         cpus {
  24                 #address-cells = <2>;
  25                 #size-cells = <0>;
  26
  27                 cpu@0 {
  28                         compatible = "arm,cortex-a53";
  29                         device_type = "cpu";
  30                         reg = <0x0 0x0>;
  31                         enable-method = "psci";
  32                 };
  33
  34                 cpu@1 {
  35                         compatible = "arm,cortex-a53";
  36                         device_type = "cpu";
  37                         reg = <0x0 0x1>;
  38                         enable-method = "psci";
  39                 };
  40
  41                 cpu@2 {
  42                         compatible = "arm,cortex-a53";
  43                         device_type = "cpu";
  44                         reg = <0x0 0x2>;
  45                         enable-method = "psci";
  46                 };
  47
  48                 cpu@3 {
  49                         compatible = "arm,cortex-a53";
  50                         device_type = "cpu";
  51                         reg = <0x0 0x3>;
  52                         enable-method = "psci";
  53                 };
  54         };
  55
  56         gic: interrupt-controller@f1001000 {
  57                 compatible = "arm,gic-400";
  58                 reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
  59                       <0x0 0xf1002000 0x0 0x100>;   /* GICC */
  60                 #address-cells = <0>;
  61                 #interrupt-cells = <3>;
  62                 interrupt-controller;
  63         };
  64
  65         timer {
  66                 compatible = "arm,armv8-timer";
  67                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
  68                               IRQ_TYPE_LEVEL_LOW)>,
  69                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
  70                               IRQ_TYPE_LEVEL_LOW)>,
  71                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
  72                               IRQ_TYPE_LEVEL_LOW)>,
  73                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
  74                               IRQ_TYPE_LEVEL_LOW)>;
  75         };
  76
  77         soc: soc@f0000000 {
  78                 compatible = "simple-bus";
  79                 #address-cells = <1>;
  80                 #size-cells = <1>;
  81                 ranges = <0x0 0x0 0xf0000000 0x10000000>;
  82
  83                 crg: clock-reset-controller@8a22000 {
  84                         compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
  85                         reg = <0x8a22000 0x1000>;
  86                         #clock-cells = <1>;
  87                         #reset-cells = <2>;
  88
  89                         gmacphyrst: reset-controller {
  90                                 compatible = "ti,syscon-reset";
  91                                 #reset-cells = <1>;
  92                                 ti,reset-bits =
  93                                         <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
  94                                          DEASSERT_SET|STATUS_NONE)>,
  95                                         <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
  96                                          DEASSERT_SET|STATUS_NONE)>;
  97                         };
  98                 };
  99
 100                 sysctrl: system-controller@8000000 {
 101                         compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
 102                         reg = <0x8000000 0x1000>;
 103                         #clock-cells = <1>;
 104                         #reset-cells = <2>;
 105                 };
 106
 107                 uart0: serial@8b00000 {
 108                         compatible = "arm,pl011", "arm,primecell";
 109                         reg = <0x8b00000 0x1000>;
 110                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 111                         clocks = <&sysctrl HISTB_UART0_CLK>;
 112                         clock-names = "apb_pclk";
 113                         status = "disabled";
 114                 };
 115
 116                 uart2: serial@8b02000 {
 117                         compatible = "arm,pl011", "arm,primecell";
 118                         reg = <0x8b02000 0x1000>;
 119                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 120                         clocks = <&crg HISTB_UART2_CLK>;
 121                         clock-names = "apb_pclk";
 122                         status = "disabled";
 123                 };
 124
 125                 i2c0: i2c@8b10000 {
 126                         compatible = "hisilicon,hix5hd2-i2c";
 127                         reg = <0x8b10000 0x1000>;
 128                         #address-cells = <1>;
 129                         #size-cells = <0>;
 130                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 131                         clock-frequency = <400000>;
 132                         clocks = <&crg HISTB_I2C0_CLK>;
 133                         status = "disabled";
 134                 };
 135
 136                 i2c1: i2c@8b11000 {
 137                         compatible = "hisilicon,hix5hd2-i2c";
 138                         reg = <0x8b11000 0x1000>;
 139                         #address-cells = <1>;
 140                         #size-cells = <0>;
 141                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 142                         clock-frequency = <400000>;
 143                         clocks = <&crg HISTB_I2C1_CLK>;
 144                         status = "disabled";
 145                 };
 146
 147                 i2c2: i2c@8b12000 {
 148                         compatible = "hisilicon,hix5hd2-i2c";
 149                         reg = <0x8b12000 0x1000>;
 150                         #address-cells = <1>;
 151                         #size-cells = <0>;
 152                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 153                         clock-frequency = <400000>;
 154                         clocks = <&crg HISTB_I2C2_CLK>;
 155                         status = "disabled";
 156                 };
 157
 158                 i2c3: i2c@8b13000 {
 159                         compatible = "hisilicon,hix5hd2-i2c";
 160                         reg = <0x8b13000 0x1000>;
 161                         #address-cells = <1>;
 162                         #size-cells = <0>;
 163                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 164                         clock-frequency = <400000>;
 165                         clocks = <&crg HISTB_I2C3_CLK>;
 166                         status = "disabled";
 167                 };
 168
 169                 i2c4: i2c@8b14000 {
 170                         compatible = "hisilicon,hix5hd2-i2c";
 171                         reg = <0x8b14000 0x1000>;
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 175                         clock-frequency = <400000>;
 176                         clocks = <&crg HISTB_I2C4_CLK>;
 177                         status = "disabled";
 178                 };
 179
 180                 spi0: spi@8b1a000 {
 181                         compatible = "arm,pl022", "arm,primecell";
 182                         reg = <0x8b1a000 0x1000>;
 183                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 184                         num-cs = <1>;
 185                         cs-gpios = <&gpio7 1 0>;
 186                         clocks = <&crg HISTB_SPI0_CLK>;
 187                         clock-names = "apb_pclk";
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         status = "disabled";
 191                 };
 192
 193                 emmc: mmc@9830000 {
 194                         compatible = "snps,dw-mshc";
 195                         reg = <0x9830000 0x10000>;
 196                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 197                         clocks = <&crg HISTB_MMC_CIU_CLK>,
 198                                  <&crg HISTB_MMC_BIU_CLK>;
 199                         clock-names = "ciu", "biu";
 200                 };
 201
 202                 gpio0: gpio@8b20000 {
 203                         compatible = "arm,pl061", "arm,primecell";
 204                         reg = <0x8b20000 0x1000>;
 205                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 206                         gpio-controller;
 207                         #gpio-cells = <2>;
 208                         interrupt-controller;
 209                         #interrupt-cells = <2>;
 210                         clocks = <&crg HISTB_APB_CLK>;
 211                         clock-names = "apb_pclk";
 212                         status = "disabled";
 213                 };
 214
 215                 gpio1: gpio@8b21000 {
 216                         compatible = "arm,pl061", "arm,primecell";
 217                         reg = <0x8b21000 0x1000>;
 218                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 219                         gpio-controller;
 220                         #gpio-cells = <2>;
 221                         interrupt-controller;
 222                         #interrupt-cells = <2>;
 223                         clocks = <&crg HISTB_APB_CLK>;
 224                         clock-names = "apb_pclk";
 225                         status = "disabled";
 226                 };
 227
 228                 gpio2: gpio@8b22000 {
 229                         compatible = "arm,pl061", "arm,primecell";
 230                         reg = <0x8b22000 0x1000>;
 231                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 232                         gpio-controller;
 233                         #gpio-cells = <2>;
 234                         interrupt-controller;
 235                         #interrupt-cells = <2>;
 236                         clocks = <&crg HISTB_APB_CLK>;
 237                         clock-names = "apb_pclk";
 238                         status = "disabled";
 239                 };
 240
 241                 gpio3: gpio@8b23000 {
 242                         compatible = "arm,pl061", "arm,primecell";
 243                         reg = <0x8b23000 0x1000>;
 244                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 245                         gpio-controller;
 246                         #gpio-cells = <2>;
 247                         interrupt-controller;
 248                         #interrupt-cells = <2>;
 249                         clocks = <&crg HISTB_APB_CLK>;
 250                         clock-names = "apb_pclk";
 251                         status = "disabled";
 252                 };
 253
 254                 gpio4: gpio@8b24000 {
 255                         compatible = "arm,pl061", "arm,primecell";
 256                         reg = <0x8b24000 0x1000>;
 257                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 258                         gpio-controller;
 259                         #gpio-cells = <2>;
 260                         interrupt-controller;
 261                         #interrupt-cells = <2>;
 262                         clocks = <&crg HISTB_APB_CLK>;
 263                         clock-names = "apb_pclk";
 264                         status = "disabled";
 265                 };
 266
 267                 gpio5: gpio@8004000 {
 268                         compatible = "arm,pl061", "arm,primecell";
 269                         reg = <0x8004000 0x1000>;
 270                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 271                         gpio-controller;
 272                         #gpio-cells = <2>;
 273                         interrupt-controller;
 274                         #interrupt-cells = <2>;
 275                         clocks = <&crg HISTB_APB_CLK>;
 276                         clock-names = "apb_pclk";
 277                         status = "disabled";
 278                 };
 279
 280                 gpio6: gpio@8b26000 {
 281                         compatible = "arm,pl061", "arm,primecell";
 282                         reg = <0x8b26000 0x1000>;
 283                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 284                         gpio-controller;
 285                         #gpio-cells = <2>;
 286                         interrupt-controller;
 287                         #interrupt-cells = <2>;
 288                         clocks = <&crg HISTB_APB_CLK>;
 289                         clock-names = "apb_pclk";
 290                         status = "disabled";
 291                 };
 292
 293                 gpio7: gpio@8b27000 {
 294                         compatible = "arm,pl061", "arm,primecell";
 295                         reg = <0x8b27000 0x1000>;
 296                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 297                         gpio-controller;
 298                         #gpio-cells = <2>;
 299                         interrupt-controller;
 300                         #interrupt-cells = <2>;
 301                         clocks = <&crg HISTB_APB_CLK>;
 302                         clock-names = "apb_pclk";
 303                         status = "disabled";
 304                 };
 305
 306                 gpio8: gpio@8b28000 {
 307                         compatible = "arm,pl061", "arm,primecell";
 308                         reg = <0x8b28000 0x1000>;
 309                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 310                         gpio-controller;
 311                         #gpio-cells = <2>;
 312                         interrupt-controller;
 313                         #interrupt-cells = <2>;
 314                         clocks = <&crg HISTB_APB_CLK>;
 315                         clock-names = "apb_pclk";
 316                         status = "disabled";
 317                 };
 318
 319                 gpio9: gpio@8b29000 {
 320                         compatible = "arm,pl061", "arm,primecell";
 321                         reg = <0x8b29000 0x1000>;
 322                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 323                         gpio-controller;
 324                         #gpio-cells = <2>;
 325                         interrupt-controller;
 326                         #interrupt-cells = <2>;
 327                         clocks = <&crg HISTB_APB_CLK>;
 328                         clock-names = "apb_pclk";
 329                         status = "disabled";
 330                 };
 331
 332                 gpio10: gpio@8b2a000 {
 333                         compatible = "arm,pl061", "arm,primecell";
 334                         reg = <0x8b2a000 0x1000>;
 335                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 336                         gpio-controller;
 337                         #gpio-cells = <2>;
 338                         interrupt-controller;
 339                         #interrupt-cells = <2>;
 340                         clocks = <&crg HISTB_APB_CLK>;
 341                         clock-names = "apb_pclk";
 342                         status = "disabled";
 343                 };
 344
 345                 gpio11: gpio@8b2b000 {
 346                         compatible = "arm,pl061", "arm,primecell";
 347                         reg = <0x8b2b000 0x1000>;
 348                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 349                         gpio-controller;
 350                         #gpio-cells = <2>;
 351                         interrupt-controller;
 352                         #interrupt-cells = <2>;
 353                         clocks = <&crg HISTB_APB_CLK>;
 354                         clock-names = "apb_pclk";
 355                         status = "disabled";
 356                 };
 357
 358                 gpio12: gpio@8b2c000 {
 359                         compatible = "arm,pl061", "arm,primecell";
 360                         reg = <0x8b2c000 0x1000>;
 361                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 362                         gpio-controller;
 363                         #gpio-cells = <2>;
 364                         interrupt-controller;
 365                         #interrupt-cells = <2>;
 366                         clocks = <&crg HISTB_APB_CLK>;
 367                         clock-names = "apb_pclk";
 368                         status = "disabled";
 369                 };
 370
 371                 gmac0: ethernet@9840000 {
 372                         compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
 373                         reg = <0x9840000 0x1000>,
 374                               <0x984300c 0x4>;
 375                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 376                         clocks = <&crg HISTB_ETH0_MAC_CLK>,
 377                                  <&crg HISTB_ETH0_MACIF_CLK>;
 378                         clock-names = "mac_core", "mac_ifc";
 379                         resets = <&crg 0xcc 8>,
 380                                  <&crg 0xcc 10>,
 381                                  <&gmacphyrst 0>;
 382                         reset-names = "mac_core", "mac_ifc", "phy";
 383                         status = "disabled";
 384                 };
 385
 386                 gmac1: ethernet@9841000 {
 387                         compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
 388                         reg = <0x9841000 0x1000>,
 389                               <0x9843010 0x4>;
 390                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 391                         clocks = <&crg HISTB_ETH1_MAC_CLK>,
 392                                  <&crg HISTB_ETH1_MACIF_CLK>;
 393                         clock-names = "mac_core", "mac_ifc";
 394                         resets = <&crg 0xcc 9>,
 395                                  <&crg 0xcc 11>,
 396                                  <&gmacphyrst 1>;
 397                         reset-names = "mac_core", "mac_ifc", "phy";
 398                         status = "disabled";
 399                 };
 400
 401                 ir: ir@8001000 {
 402                         compatible = "hisilicon,hix5hd2-ir";
 403                         reg = <0x8001000 0x1000>;
 404                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 405                         clocks = <&sysctrl HISTB_IR_CLK>;
 406                         status = "disabled";
 407                 };
 408         };
 409 };