arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <fsl_ddr_sdram.h>
   9 #include <asm/io.h>
  10 #include <linux/errno.h>
  11 #include <asm/system.h>
  12 #include <fm_eth.h>
  13 #include <asm/armv8/mmu.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/fsl_serdes.h>
  16 #include <asm/arch/soc.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/speed.h>
  19 #include <fsl_immap.h>
  20 #include <asm/arch/mp.h>
  21 #include <efi_loader.h>
  22 #include <fsl-mc/fsl_mc.h>
  23 #ifdef CONFIG_FSL_ESDHC
  24 #include <fsl_esdhc.h>
  25 #endif
  26 #include <asm/armv8/sec_firmware.h>
  27 #ifdef CONFIG_SYS_FSL_DDR
  28 #include <fsl_ddr.h>
  29 #endif
  30 #include <asm/arch/clock.h>
  31 #include <hwconfig.h>
  32 #include <fsl_qbman.h>
  33
  34 #ifdef CONFIG_TFABOOT
  35 #include <environment.h>
  36 #ifdef CONFIG_CHAIN_OF_TRUST
  37 #include <fsl_validate.h>
  38 #endif
  39 #endif
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 static struct cpu_type cpu_type_list[] = {
  44         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  45         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  46         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  47         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  48         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  49         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  50         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  51         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  52         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  53         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  54         CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
  55         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  56         CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
  57         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  58         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  59         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  60         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  61         CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
  62         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  63         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  64         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  65         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  66         CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
  67         CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
  68         CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
  69 };
  70
  71 #define EARLY_PGTABLE_SIZE 0x5000
  72 static struct mm_region early_map[] = {
  73 #ifdef CONFIG_FSL_LSCH3
  74         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  75           CONFIG_SYS_FSL_CCSR_SIZE,
  76           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  77           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  78         },
  79         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  80           SYS_FSL_OCRAM_SPACE_SIZE,
  81           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  82         },
  83         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
  84           CONFIG_SYS_FSL_QSPI_SIZE1,
  85           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
  86 #ifdef CONFIG_FSL_IFC
  87         /* For IFC Region #1, only the first 4MB is cache-enabled */
  88         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  89           CONFIG_SYS_FSL_IFC_SIZE1_1,
  90           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  91         },
  92         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  93           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  94           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
  95           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
  96         },
  97         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
  98           CONFIG_SYS_FSL_IFC_SIZE1,
  99           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 100         },
 101 #endif
 102         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 103           CONFIG_SYS_FSL_DRAM_SIZE1,
 104 #if defined(CONFIG_TFABOOT) || \
 105         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 106           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 107 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 108           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 109 #endif
 110           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 111         },
 112 #ifdef CONFIG_FSL_IFC
 113         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 114         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 115           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 116           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 117         },
 118 #endif
 119         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 120           CONFIG_SYS_FSL_DCSR_SIZE,
 121           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 122           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 123         },
 124         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 125           CONFIG_SYS_FSL_DRAM_SIZE2,
 126           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 127           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 128         },
 129 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 130         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 131           CONFIG_SYS_FSL_DRAM_SIZE3,
 132           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 133           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 134         },
 135 #endif
 136 #elif defined(CONFIG_FSL_LSCH2)
 137         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 138           CONFIG_SYS_FSL_CCSR_SIZE,
 139           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 140           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 141         },
 142         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 143           SYS_FSL_OCRAM_SPACE_SIZE,
 144           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 145         },
 146         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 147           CONFIG_SYS_FSL_DCSR_SIZE,
 148           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 149           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 150         },
 151         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 152           CONFIG_SYS_FSL_QSPI_SIZE,
 153           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 154         },
 155 #ifdef CONFIG_FSL_IFC
 156         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 157           CONFIG_SYS_FSL_IFC_SIZE,
 158           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 159         },
 160 #endif
 161         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 162           CONFIG_SYS_FSL_DRAM_SIZE1,
 163 #if defined(CONFIG_TFABOOT) || \
 164         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 165           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 166 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 167           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 168 #endif
 169           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 170         },
 171         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 172           CONFIG_SYS_FSL_DRAM_SIZE2,
 173           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 174           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 175         },
 176 #endif
 177         {},     /* list terminator */
 178 };
 179
 180 static struct mm_region final_map[] = {
 181 #ifdef CONFIG_FSL_LSCH3
 182         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 183           CONFIG_SYS_FSL_CCSR_SIZE,
 184           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 185           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 186         },
 187         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 188           SYS_FSL_OCRAM_SPACE_SIZE,
 189           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 190         },
 191         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 192           CONFIG_SYS_FSL_DRAM_SIZE1,
 193           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 194           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 195         },
 196         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 197           CONFIG_SYS_FSL_QSPI_SIZE1,
 198           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 199           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 200         },
 201         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 202           CONFIG_SYS_FSL_QSPI_SIZE2,
 203           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 204           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 205         },
 206 #ifdef CONFIG_FSL_IFC
 207         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 208           CONFIG_SYS_FSL_IFC_SIZE2,
 209           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 210           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 211         },
 212 #endif
 213         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 214           CONFIG_SYS_FSL_DCSR_SIZE,
 215           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 216           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 217         },
 218         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 219           CONFIG_SYS_FSL_MC_SIZE,
 220           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 221           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 222         },
 223         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 224           CONFIG_SYS_FSL_NI_SIZE,
 225           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 226           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 227         },
 228         /* For QBMAN portal, only the first 64MB is cache-enabled */
 229         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 230           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 231           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 232           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 233         },
 234         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 235           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 236           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 237           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 238           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 239         },
 240         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 241           CONFIG_SYS_PCIE1_PHYS_SIZE,
 242           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 243           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 244         },
 245         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 246           CONFIG_SYS_PCIE2_PHYS_SIZE,
 247           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 248           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 249         },
 250 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 251         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 252           CONFIG_SYS_PCIE3_PHYS_SIZE,
 253           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 254           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 255         },
 256 #endif
 257 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 258         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 259           CONFIG_SYS_PCIE4_PHYS_SIZE,
 260           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 261           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 262         },
 263 #endif
 264 #ifdef SYS_PCIE5_PHYS_ADDR
 265         { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
 266           SYS_PCIE5_PHYS_SIZE,
 267           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 268           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 269         },
 270 #endif
 271 #ifdef SYS_PCIE6_PHYS_ADDR
 272         { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
 273           SYS_PCIE6_PHYS_SIZE,
 274           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 275           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 276         },
 277 #endif
 278         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 279           CONFIG_SYS_FSL_WRIOP1_SIZE,
 280           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 281           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 282         },
 283         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 284           CONFIG_SYS_FSL_AIOP1_SIZE,
 285           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 286           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 287         },
 288         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 289           CONFIG_SYS_FSL_PEBUF_SIZE,
 290           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 291           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 292         },
 293         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 294           CONFIG_SYS_FSL_DRAM_SIZE2,
 295           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 296           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 297         },
 298 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 299         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 300           CONFIG_SYS_FSL_DRAM_SIZE3,
 301           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 302           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 303         },
 304 #endif
 305 #elif defined(CONFIG_FSL_LSCH2)
 306         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 307           CONFIG_SYS_FSL_BOOTROM_SIZE,
 308           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 309           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 310         },
 311         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 312           CONFIG_SYS_FSL_CCSR_SIZE,
 313           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 314           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 315         },
 316         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 317           SYS_FSL_OCRAM_SPACE_SIZE,
 318           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 319         },
 320         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 321           CONFIG_SYS_FSL_DCSR_SIZE,
 322           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 323           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 324         },
 325         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 326           CONFIG_SYS_FSL_QSPI_SIZE,
 327           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 328           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 329         },
 330 #ifdef CONFIG_FSL_IFC
 331         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 332           CONFIG_SYS_FSL_IFC_SIZE,
 333           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 334         },
 335 #endif
 336         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 337           CONFIG_SYS_FSL_DRAM_SIZE1,
 338           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 339           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 340         },
 341         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 342           CONFIG_SYS_FSL_QBMAN_SIZE,
 343           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 344           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 345         },
 346         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 347           CONFIG_SYS_FSL_DRAM_SIZE2,
 348           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 349           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 350         },
 351         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 352           CONFIG_SYS_PCIE1_PHYS_SIZE,
 353           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 354           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 355         },
 356         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 357           CONFIG_SYS_PCIE2_PHYS_SIZE,
 358           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 359           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 360         },
 361 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 362         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 363           CONFIG_SYS_PCIE3_PHYS_SIZE,
 364           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 365           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 366         },
 367 #endif
 368         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 369           CONFIG_SYS_FSL_DRAM_SIZE3,
 370           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 371           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 372         },
 373 #endif
 374 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 375         {},     /* space holder for secure mem */
 376 #endif
 377         {},
 378 };
 379
 380 struct mm_region *mem_map = early_map;
 381
 382 void cpu_name(char *name)
 383 {
 384         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 385         unsigned int i, svr, ver;
 386
 387         svr = gur_in32(&gur->svr);
 388         ver = SVR_SOC_VER(svr);
 389
 390         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 391                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 392                         strcpy(name, cpu_type_list[i].name);
 393 #ifdef CONFIG_ARCH_LX2160A
 394                         if (IS_C_PROCESSOR(svr))
 395                                 strcat(name, "C");
 396 #endif
 397
 398                         if (IS_E_PROCESSOR(svr))
 399                                 strcat(name, "E");
 400
 401                         sprintf(name + strlen(name), " Rev%d.%d",
 402                                 SVR_MAJ(svr), SVR_MIN(svr));
 403                         break;
 404                 }
 405
 406         if (i == ARRAY_SIZE(cpu_type_list))
 407                 strcpy(name, "unknown");
 408 }
 409
 410 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 411 /*
 412  * To start MMU before DDR is available, we create MMU table in SRAM.
 413  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 414  * levels of translation tables here to cover 40-bit address space.
 415  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 416  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 417  * Note, the debug print in cache_v8.c is not usable for debugging
 418  * these early MMU tables because UART is not yet available.
 419  */
 420 static inline void early_mmu_setup(void)
 421 {
 422         unsigned int el = current_el();
 423
 424         /* global data is already setup, no allocation yet */
 425         if (el == 3)
 426                 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 427         else
 428                 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 429         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 430         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 431
 432         /* Create early page tables */
 433         setup_pgtables();
 434
 435         /* point TTBR to the new table */
 436         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 437                           get_tcr(el, NULL, NULL) &
 438                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 439                           MEMORY_ATTRIBUTES);
 440
 441         set_sctlr(get_sctlr() | CR_M);
 442 }
 443
 444 static void fix_pcie_mmu_map(void)
 445 {
 446 #ifdef CONFIG_ARCH_LS2080A
 447         unsigned int i;
 448         u32 svr, ver;
 449         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 450
 451         svr = gur_in32(&gur->svr);
 452         ver = SVR_SOC_VER(svr);
 453
 454         /* Fix PCIE base and size for LS2088A */
 455         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 456             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 457             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 458                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 459                         switch (final_map[i].phys) {
 460                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 461                                 final_map[i].phys = 0x2000000000ULL;
 462                                 final_map[i].virt = 0x2000000000ULL;
 463                                 final_map[i].size = 0x800000000ULL;
 464                                 break;
 465                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 466                                 final_map[i].phys = 0x2800000000ULL;
 467                                 final_map[i].virt = 0x2800000000ULL;
 468                                 final_map[i].size = 0x800000000ULL;
 469                                 break;
 470 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 471                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 472                                 final_map[i].phys = 0x3000000000ULL;
 473                                 final_map[i].virt = 0x3000000000ULL;
 474                                 final_map[i].size = 0x800000000ULL;
 475                                 break;
 476 #endif
 477 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 478                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 479                                 final_map[i].phys = 0x3800000000ULL;
 480                                 final_map[i].virt = 0x3800000000ULL;
 481                                 final_map[i].size = 0x800000000ULL;
 482                                 break;
 483 #endif
 484                         default:
 485                                 break;
 486                         }
 487                 }
 488         }
 489 #endif
 490 }
 491
 492 /*
 493  * The final tables look similar to early tables, but different in detail.
 494  * These tables are in DRAM. Sub tables are added to enable cache for
 495  * QBMan and OCRAM.
 496  *
 497  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 498  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 499  */
 500 static inline void final_mmu_setup(void)
 501 {
 502         u64 tlb_addr_save = gd->arch.tlb_addr;
 503         unsigned int el = current_el();
 504         int index;
 505
 506         /* fix the final_map before filling in the block entries */
 507         fix_pcie_mmu_map();
 508
 509         mem_map = final_map;
 510
 511         /* Update mapping for DDR to actual size */
 512         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 513                 /*
 514                  * Find the entry for DDR mapping and update the address and
 515                  * size. Zero-sized mapping will be skipped when creating MMU
 516                  * table.
 517                  */
 518                 switch (final_map[index].virt) {
 519                 case CONFIG_SYS_FSL_DRAM_BASE1:
 520                         final_map[index].virt = gd->bd->bi_dram[0].start;
 521                         final_map[index].phys = gd->bd->bi_dram[0].start;
 522                         final_map[index].size = gd->bd->bi_dram[0].size;
 523                         break;
 524 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 525                 case CONFIG_SYS_FSL_DRAM_BASE2:
 526 #if (CONFIG_NR_DRAM_BANKS >= 2)
 527                         final_map[index].virt = gd->bd->bi_dram[1].start;
 528                         final_map[index].phys = gd->bd->bi_dram[1].start;
 529                         final_map[index].size = gd->bd->bi_dram[1].size;
 530 #else
 531                         final_map[index].size = 0;
 532 #endif
 533                 break;
 534 #endif
 535 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 536                 case CONFIG_SYS_FSL_DRAM_BASE3:
 537 #if (CONFIG_NR_DRAM_BANKS >= 3)
 538                         final_map[index].virt = gd->bd->bi_dram[2].start;
 539                         final_map[index].phys = gd->bd->bi_dram[2].start;
 540                         final_map[index].size = gd->bd->bi_dram[2].size;
 541 #else
 542                         final_map[index].size = 0;
 543 #endif
 544                 break;
 545 #endif
 546                 default:
 547                         break;
 548                 }
 549         }
 550
 551 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 552         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 553                 if (el == 3) {
 554                         /*
 555                          * Only use gd->arch.secure_ram if the address is
 556                          * recalculated. Align to 4KB for MMU table.
 557                          */
 558                         /* put page tables in secure ram */
 559                         index = ARRAY_SIZE(final_map) - 2;
 560                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 561                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 562                         final_map[index].phys = final_map[index].virt;
 563                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 564                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 565                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 566                         tlb_addr_save = gd->arch.tlb_addr;
 567                 } else {
 568                         /* Use allocated (board_f.c) memory for TLB */
 569                         tlb_addr_save = gd->arch.tlb_allocated;
 570                         gd->arch.tlb_addr = tlb_addr_save;
 571                 }
 572         }
 573 #endif
 574
 575         /* Reset the fill ptr */
 576         gd->arch.tlb_fillptr = tlb_addr_save;
 577
 578         /* Create normal system page tables */
 579         setup_pgtables();
 580
 581         /* Create emergency page tables */
 582         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 583         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 584         setup_pgtables();
 585         gd->arch.tlb_addr = tlb_addr_save;
 586
 587         /* Disable cache and MMU */
 588         dcache_disable();       /* TLBs are invalidated */
 589         invalidate_icache_all();
 590
 591         /* point TTBR to the new table */
 592         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 593                           MEMORY_ATTRIBUTES);
 594
 595         set_sctlr(get_sctlr() | CR_M);
 596 }
 597
 598 u64 get_page_table_size(void)
 599 {
 600         return 0x10000;
 601 }
 602
 603 int arch_cpu_init(void)
 604 {
 605         /*
 606          * This function is called before U-Boot relocates itself to speed up
 607          * on system running. It is not necessary to run if performance is not
 608          * critical. Skip if MMU is already enabled by SPL or other means.
 609          */
 610         if (get_sctlr() & CR_M)
 611                 return 0;
 612
 613         icache_enable();
 614         __asm_invalidate_dcache_all();
 615         __asm_invalidate_tlb_all();
 616         early_mmu_setup();
 617         set_sctlr(get_sctlr() | CR_C);
 618         return 0;
 619 }
 620
 621 void mmu_setup(void)
 622 {
 623         final_mmu_setup();
 624 }
 625
 626 /*
 627  * This function is called from common/board_r.c.
 628  * It recreates MMU table in main memory.
 629  */
 630 void enable_caches(void)
 631 {
 632         mmu_setup();
 633         __asm_invalidate_tlb_all();
 634         icache_enable();
 635         dcache_enable();
 636 }
 637 #endif  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 638
 639 #ifdef CONFIG_TFABOOT
 640 enum boot_src __get_boot_src(u32 porsr1)
 641 {
 642         enum boot_src src = BOOT_SOURCE_RESERVED;
 643         u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
 644 #if !defined(CONFIG_NXP_LSCH3_2)
 645         u32 val;
 646 #endif
 647         debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
 648
 649 #if defined(CONFIG_FSL_LSCH3)
 650 #if defined(CONFIG_NXP_LSCH3_2)
 651         switch (rcw_src) {
 652         case RCW_SRC_SDHC1_VAL:
 653                 src = BOOT_SOURCE_SD_MMC;
 654         break;
 655         case RCW_SRC_SDHC2_VAL:
 656                 src = BOOT_SOURCE_SD_MMC2;
 657         break;
 658         case RCW_SRC_I2C1_VAL:
 659                 src = BOOT_SOURCE_I2C1_EXTENDED;
 660         break;
 661         case RCW_SRC_FLEXSPI_NAND2K_VAL:
 662                 src = BOOT_SOURCE_XSPI_NAND;
 663         break;
 664         case RCW_SRC_FLEXSPI_NAND4K_VAL:
 665                 src = BOOT_SOURCE_XSPI_NAND;
 666         break;
 667         case RCW_SRC_RESERVED_1_VAL:
 668                 src = BOOT_SOURCE_RESERVED;
 669         break;
 670         case RCW_SRC_FLEXSPI_NOR_24B:
 671                 src = BOOT_SOURCE_XSPI_NOR;
 672         break;
 673         default:
 674                 src = BOOT_SOURCE_RESERVED;
 675         }
 676 #else
 677         val = rcw_src & RCW_SRC_TYPE_MASK;
 678         if (val == RCW_SRC_NOR_VAL) {
 679                 val = rcw_src & NOR_TYPE_MASK;
 680
 681                 switch (val) {
 682                 case NOR_16B_VAL:
 683                 case NOR_32B_VAL:
 684                         src = BOOT_SOURCE_IFC_NOR;
 685                 break;
 686                 default:
 687                         src = BOOT_SOURCE_RESERVED;
 688                 }
 689         } else {
 690                 /* RCW SRC Serial Flash */
 691                 val = rcw_src & RCW_SRC_SERIAL_MASK;
 692                 switch (val) {
 693                 case RCW_SRC_QSPI_VAL:
 694                 /* RCW SRC Serial NOR (QSPI) */
 695                         src = BOOT_SOURCE_QSPI_NOR;
 696                         break;
 697                 case RCW_SRC_SD_CARD_VAL:
 698                 /* RCW SRC SD Card */
 699                         src = BOOT_SOURCE_SD_MMC;
 700                         break;
 701                 case RCW_SRC_EMMC_VAL:
 702                 /* RCW SRC EMMC */
 703                         src = BOOT_SOURCE_SD_MMC;
 704                         break;
 705                 case RCW_SRC_I2C1_VAL:
 706                 /* RCW SRC I2C1 Extended */
 707                         src = BOOT_SOURCE_I2C1_EXTENDED;
 708                         break;
 709                 default:
 710                         src = BOOT_SOURCE_RESERVED;
 711                 }
 712         }
 713 #endif
 714 #elif defined(CONFIG_FSL_LSCH2)
 715         /* RCW SRC NAND */
 716         val = rcw_src & RCW_SRC_NAND_MASK;
 717         if (val == RCW_SRC_NAND_VAL) {
 718                 val = rcw_src & NAND_RESERVED_MASK;
 719                 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
 720                         src = BOOT_SOURCE_IFC_NAND;
 721
 722         } else {
 723                 /* RCW SRC NOR */
 724                 val = rcw_src & RCW_SRC_NOR_MASK;
 725                 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
 726                         src = BOOT_SOURCE_IFC_NOR;
 727                 } else {
 728                         switch (rcw_src) {
 729                         case QSPI_VAL1:
 730                         case QSPI_VAL2:
 731                                 src = BOOT_SOURCE_QSPI_NOR;
 732                                 break;
 733                         case SD_VAL:
 734                                 src = BOOT_SOURCE_SD_MMC;
 735                                 break;
 736                         default:
 737                                 src = BOOT_SOURCE_RESERVED;
 738                         }
 739                 }
 740         }
 741 #endif
 742
 743         if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
 744                 src = BOOT_SOURCE_QSPI_NOR;
 745
 746         debug("%s: src 0x%x\n", __func__, src);
 747         return src;
 748 }
 749
 750 enum boot_src get_boot_src(void)
 751 {
 752         struct pt_regs regs;
 753         u32 porsr1 = 0;
 754
 755 #if defined(CONFIG_FSL_LSCH3)
 756         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 757 #elif defined(CONFIG_FSL_LSCH2)
 758         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 759 #endif
 760
 761         if (current_el() == 2) {
 762                 regs.regs[0] = SIP_SVC_RCW;
 763
 764                 smc_call(&regs);
 765                 if (!regs.regs[0])
 766                         porsr1 = regs.regs[1];
 767         }
 768
 769         if (current_el() == 3 || !porsr1) {
 770 #ifdef CONFIG_FSL_LSCH3
 771                 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 772 #elif defined(CONFIG_FSL_LSCH2)
 773                 porsr1 = in_be32(&gur->porsr1);
 774 #endif
 775         }
 776
 777         debug("%s: porsr1 0x%x\n", __func__, porsr1);
 778
 779         return __get_boot_src(porsr1);
 780 }
 781
 782 #ifdef CONFIG_ENV_IS_IN_MMC
 783 int mmc_get_env_dev(void)
 784 {
 785         enum boot_src src = get_boot_src();
 786         int dev = CONFIG_SYS_MMC_ENV_DEV;
 787
 788         switch (src) {
 789         case BOOT_SOURCE_SD_MMC:
 790                 dev = 0;
 791                 break;
 792         case BOOT_SOURCE_SD_MMC2:
 793                 dev = 1;
 794                 break;
 795         default:
 796                 break;
 797         }
 798
 799         return dev;
 800 }
 801 #endif
 802
 803 enum env_location env_get_location(enum env_operation op, int prio)
 804 {
 805         enum boot_src src = get_boot_src();
 806         enum env_location env_loc = ENVL_NOWHERE;
 807
 808         if (prio)
 809                 return ENVL_UNKNOWN;
 810
 811 #ifdef CONFIG_CHAIN_OF_TRUST
 812         /* Check Boot Mode
 813          * If Boot Mode is Secure, return ENVL_NOWHERE
 814          */
 815         if (fsl_check_boot_mode_secure() == 1)
 816                 goto done;
 817 #endif
 818
 819         switch (src) {
 820         case BOOT_SOURCE_IFC_NOR:
 821                 env_loc = ENVL_FLASH;
 822                 break;
 823         case BOOT_SOURCE_QSPI_NOR:
 824                 /* FALLTHROUGH */
 825         case BOOT_SOURCE_XSPI_NOR:
 826                 env_loc = ENVL_SPI_FLASH;
 827                 break;
 828         case BOOT_SOURCE_IFC_NAND:
 829                 /* FALLTHROUGH */
 830         case BOOT_SOURCE_QSPI_NAND:
 831                 /* FALLTHROUGH */
 832         case BOOT_SOURCE_XSPI_NAND:
 833                 env_loc = ENVL_NAND;
 834                 break;
 835         case BOOT_SOURCE_SD_MMC:
 836                 /* FALLTHROUGH */
 837         case BOOT_SOURCE_SD_MMC2:
 838                 env_loc =  ENVL_MMC;
 839                 break;
 840         case BOOT_SOURCE_I2C1_EXTENDED:
 841                 /* FALLTHROUGH */
 842         default:
 843                 break;
 844         }
 845
 846 #ifdef CONFIG_CHAIN_OF_TRUST
 847 done:
 848 #endif
 849         return env_loc;
 850 }
 851 #endif  /* CONFIG_TFABOOT */
 852
 853 u32 initiator_type(u32 cluster, int init_id)
 854 {
 855         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 856         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 857         u32 type = 0;
 858
 859         type = gur_in32(&gur->tp_ityp[idx]);
 860         if (type & TP_ITYP_AV)
 861                 return type;
 862
 863         return 0;
 864 }
 865
 866 u32 cpu_pos_mask(void)
 867 {
 868         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 869         int i = 0;
 870         u32 cluster, type, mask = 0;
 871
 872         do {
 873                 int j;
 874
 875                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 876                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 877                         type = initiator_type(cluster, j);
 878                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 879                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 880                 }
 881                 i++;
 882         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 883
 884         return mask;
 885 }
 886
 887 u32 cpu_mask(void)
 888 {
 889         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 890         int i = 0, count = 0;
 891         u32 cluster, type, mask = 0;
 892
 893         do {
 894                 int j;
 895
 896                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 897                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 898                         type = initiator_type(cluster, j);
 899                         if (type) {
 900                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 901                                         mask |= 1 << count;
 902                                 count++;
 903                         }
 904                 }
 905                 i++;
 906         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 907
 908         return mask;
 909 }
 910
 911 /*
 912  * Return the number of cores on this SOC.
 913  */
 914 int cpu_numcores(void)
 915 {
 916         return hweight32(cpu_mask());
 917 }
 918
 919 int fsl_qoriq_core_to_cluster(unsigned int core)
 920 {
 921         struct ccsr_gur __iomem *gur =
 922                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 923         int i = 0, count = 0;
 924         u32 cluster;
 925
 926         do {
 927                 int j;
 928
 929                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 930                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 931                         if (initiator_type(cluster, j)) {
 932                                 if (count == core)
 933                                         return i;
 934                                 count++;
 935                         }
 936                 }
 937                 i++;
 938         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 939
 940         return -1;      /* cannot identify the cluster */
 941 }
 942
 943 u32 fsl_qoriq_core_to_type(unsigned int core)
 944 {
 945         struct ccsr_gur __iomem *gur =
 946                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 947         int i = 0, count = 0;
 948         u32 cluster, type;
 949
 950         do {
 951                 int j;
 952
 953                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 954                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 955                         type = initiator_type(cluster, j);
 956                         if (type) {
 957                                 if (count == core)
 958                                         return type;
 959                                 count++;
 960                         }
 961                 }
 962                 i++;
 963         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 964
 965         return -1;      /* cannot identify the cluster */
 966 }
 967
 968 #ifndef CONFIG_FSL_LSCH3
 969 uint get_svr(void)
 970 {
 971         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 972
 973         return gur_in32(&gur->svr);
 974 }
 975 #endif
 976
 977 #ifdef CONFIG_DISPLAY_CPUINFO
 978 int print_cpuinfo(void)
 979 {
 980         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 981         struct sys_info sysinfo;
 982         char buf[32];
 983         unsigned int i, core;
 984         u32 type, rcw, svr = gur_in32(&gur->svr);
 985
 986         puts("SoC: ");
 987
 988         cpu_name(buf);
 989         printf(" %s (0x%x)\n", buf, svr);
 990         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 991         get_sys_info(&sysinfo);
 992         puts("Clock Configuration:");
 993         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 994                 if (!(i % 3))
 995                         puts("\n       ");
 996                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
 997                 printf("CPU%d(%s):%-4s MHz  ", core,
 998                        type == TY_ITYP_VER_A7 ? "A7 " :
 999                        (type == TY_ITYP_VER_A53 ? "A53" :
1000                        (type == TY_ITYP_VER_A57 ? "A57" :
1001                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
1002                        strmhz(buf, sysinfo.freq_processor[core]));
1003         }
1004         /* Display platform clock as Bus frequency. */
1005         printf("\n       Bus:      %-4s MHz  ",
1006                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1007         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1008 #ifdef CONFIG_SYS_DPAA_FMAN
1009         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1010 #endif
1011 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1012         if (soc_has_dp_ddr()) {
1013                 printf("     DP-DDR:   %-4s MT/s",
1014                        strmhz(buf, sysinfo.freq_ddrbus2));
1015         }
1016 #endif
1017         puts("\n");
1018
1019         /*
1020          * Display the RCW, so that no one gets confused as to what RCW
1021          * we're actually using for this boot.
1022          */
1023         puts("Reset Configuration Word (RCW):");
1024         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1025                 rcw = gur_in32(&gur->rcwsr[i]);
1026                 if ((i % 4) == 0)
1027                         printf("\n       %08x:", i * 4);
1028                 printf(" %08x", rcw);
1029         }
1030         puts("\n");
1031
1032         return 0;
1033 }
1034 #endif
1035
1036 #ifdef CONFIG_FSL_ESDHC
1037 int cpu_mmc_init(bd_t *bis)
1038 {
1039         return fsl_esdhc_mmc_init(bis);
1040 }
1041 #endif
1042
1043 int cpu_eth_init(bd_t *bis)
1044 {
1045         int error = 0;
1046
1047 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1048         error = fsl_mc_ldpaa_init(bis);
1049 #endif
1050 #ifdef CONFIG_FMAN_ENET
1051         fm_standard_init(bis);
1052 #endif
1053         return error;
1054 }
1055
1056 static inline int check_psci(void)
1057 {
1058         unsigned int psci_ver;
1059
1060         psci_ver = sec_firmware_support_psci_version();
1061         if (psci_ver == PSCI_INVALID_VER)
1062                 return 1;
1063
1064         return 0;
1065 }
1066
1067 static void config_core_prefetch(void)
1068 {
1069         char *buf = NULL;
1070         char buffer[HWCONFIG_BUFFER_SIZE];
1071         const char *prefetch_arg = NULL;
1072         size_t arglen;
1073         unsigned int mask;
1074         struct pt_regs regs;
1075
1076         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1077                 buf = buffer;
1078
1079         prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1080                                          &arglen, buf);
1081
1082         if (prefetch_arg) {
1083                 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1084                 if (mask & 0x1) {
1085                         printf("Core0 prefetch can't be disabled\n");
1086                         return;
1087                 }
1088
1089 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1090                 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1091                 regs.regs[1] = mask;
1092                 smc_call(&regs);
1093
1094                 if (regs.regs[0])
1095                         printf("Prefetch disable config failed for mask ");
1096                 else
1097                         printf("Prefetch disable config passed for mask ");
1098                 printf("0x%x\n", mask);
1099         }
1100 }
1101
1102 int arch_early_init_r(void)
1103 {
1104 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1105         u32 svr_dev_id;
1106         /*
1107          * erratum A009635 is valid only for LS2080A SoC and
1108          * its personalitiesi
1109          */
1110         svr_dev_id = get_svr();
1111         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1112                 erratum_a009635();
1113 #endif
1114 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1115         erratum_a009942_check_cpo();
1116 #endif
1117         if (check_psci()) {
1118                 debug("PSCI: PSCI does not exist.\n");
1119
1120                 /* if PSCI does not exist, boot secondary cores here */
1121                 if (fsl_layerscape_wake_seconday_cores())
1122                         printf("Did not wake secondary cores\n");
1123         }
1124
1125         config_core_prefetch();
1126
1127 #ifdef CONFIG_SYS_HAS_SERDES
1128         fsl_serdes_init();
1129 #endif
1130 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1131         /* some dpmacs in armv8a based freescale layerscape SOCs can be
1132          * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1133          * EC*_PMUX(rgmii) bits in RCW.
1134          * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1135          * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1136          * Now if a dpmac is enabled by serdes bits then it takes precedence
1137          * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
1138          * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
1139          * then the dpmac is SGMII and not RGMII.
1140          *
1141          * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
1142          * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
1143          * or not? if it is (fsl_serdes_init has already enabled the dpmac),
1144          * then don't enable it.
1145          */
1146         fsl_rgmii_init();
1147 #endif
1148 #ifdef CONFIG_FMAN_ENET
1149         fman_enet_init();
1150 #endif
1151 #ifdef CONFIG_SYS_DPAA_QBMAN
1152         setup_qbman_portals();
1153 #endif
1154         return 0;
1155 }
1156
1157 int timer_init(void)
1158 {
1159         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1160 #ifdef CONFIG_FSL_LSCH3
1161         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1162 #endif
1163 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
1164         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1165         u32 svr_dev_id;
1166 #endif
1167 #ifdef COUNTER_FREQUENCY_REAL
1168         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1169
1170         /* Update with accurate clock frequency */
1171         if (current_el() == 3)
1172                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1173 #endif
1174
1175 #ifdef CONFIG_FSL_LSCH3
1176         /* Enable timebase for all clusters.
1177          * It is safe to do so even some clusters are not enabled.
1178          */
1179         out_le32(cltbenr, 0xf);
1180 #endif
1181
1182 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
1183         /*
1184          * In certain Layerscape SoCs, the clock for each core's
1185          * has an enable bit in the PMU Physical Core Time Base Enable
1186          * Register (PCTBENR), which allows the watchdog to operate.
1187          */
1188         setbits_le32(pctbenr, 0xff);
1189         /*
1190          * For LS2080A SoC and its personalities, timer controller
1191          * offset is different
1192          */
1193         svr_dev_id = get_svr();
1194         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1195                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1196
1197 #endif
1198
1199         /* Enable clock for timer
1200          * This is a global setting.
1201          */
1202         out_le32(cntcr, 0x1);
1203
1204         return 0;
1205 }
1206
1207 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1208
1209 void __efi_runtime reset_cpu(ulong addr)
1210 {
1211         u32 val;
1212
1213 #ifdef CONFIG_ARCH_LX2160A
1214         val = in_le32(rstcr);
1215         val |= 0x01;
1216         out_le32(rstcr, val);
1217 #else
1218         /* Raise RESET_REQ_B */
1219         val = scfg_in32(rstcr);
1220         val |= 0x02;
1221         scfg_out32(rstcr, val);
1222 #endif
1223 }
1224
1225 #ifdef CONFIG_EFI_LOADER
1226
1227 void __efi_runtime EFIAPI efi_reset_system(
1228                        enum efi_reset_type reset_type,
1229                        efi_status_t reset_status,
1230                        unsigned long data_size, void *reset_data)
1231 {
1232         switch (reset_type) {
1233         case EFI_RESET_COLD:
1234         case EFI_RESET_WARM:
1235         case EFI_RESET_PLATFORM_SPECIFIC:
1236                 reset_cpu(0);
1237                 break;
1238         case EFI_RESET_SHUTDOWN:
1239                 /* Nothing we can do */
1240                 break;
1241         }
1242
1243         while (1) { }
1244 }
1245
1246 efi_status_t efi_reset_system_init(void)
1247 {
1248         return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1249 }
1250
1251 #endif
1252
1253 /*
1254  * Calculate reserved memory with given memory bank
1255  * Return aligned memory size on success
1256  * Return (ram_size + needed size) for failure
1257  */
1258 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1259 {
1260         phys_size_t ram_top = ram_size;
1261
1262 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1263         ram_top = mc_get_dram_block_size();
1264         if (ram_top > ram_size)
1265                 return ram_size + ram_top;
1266
1267         ram_top = ram_size - ram_top;
1268         /* The start address of MC reserved memory needs to be aligned. */
1269         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1270 #endif
1271
1272         return ram_size - ram_top;
1273 }
1274
1275 phys_size_t get_effective_memsize(void)
1276 {
1277         phys_size_t ea_size, rem = 0;
1278
1279         /*
1280          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1281          * first region is 2GB space at 0x8000_0000. Secure memory needs to
1282          * allocated from first region. If the memory extends to  the second
1283          * region (or the third region if applicable), Management Complex (MC)
1284          * memory should be put into the highest region, i.e. the end of DDR
1285          * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1286          * U-Boot doesn't relocate itself into higher address. Should DDR be
1287          * configured to skip the first region, this function needs to be
1288          * adjusted.
1289          */
1290         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1291                 ea_size = CONFIG_MAX_MEM_MAPPED;
1292                 rem = gd->ram_size - ea_size;
1293         } else {
1294                 ea_size = gd->ram_size;
1295         }
1296
1297 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1298         /* Check if we have enough space for secure memory */
1299         if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1300                 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1301         else
1302                 printf("Error: No enough space for secure memory.\n");
1303 #endif
1304         /* Check if we have enough memory for MC */
1305         if (rem < board_reserve_ram_top(rem)) {
1306                 /* Not enough memory in high region to reserve */
1307                 if (ea_size > board_reserve_ram_top(ea_size))
1308                         ea_size -= board_reserve_ram_top(ea_size);
1309                 else
1310                         printf("Error: No enough space for reserved memory.\n");
1311         }
1312
1313         return ea_size;
1314 }
1315
1316 #ifdef CONFIG_TFABOOT
1317 phys_size_t tfa_get_dram_size(void)
1318 {
1319         struct pt_regs regs;
1320         phys_size_t dram_size = 0;
1321
1322         regs.regs[0] = SMC_DRAM_BANK_INFO;
1323         regs.regs[1] = -1;
1324
1325         smc_call(&regs);
1326         if (regs.regs[0])
1327                 return 0;
1328
1329         dram_size = regs.regs[1];
1330         return dram_size;
1331 }
1332
1333 static int tfa_dram_init_banksize(void)
1334 {
1335         int i = 0, ret = 0;
1336         struct pt_regs regs;
1337         phys_size_t dram_size = tfa_get_dram_size();
1338
1339         debug("dram_size %llx\n", dram_size);
1340
1341         if (!dram_size)
1342                 return -EINVAL;
1343
1344         do {
1345                 regs.regs[0] = SMC_DRAM_BANK_INFO;
1346                 regs.regs[1] = i;
1347
1348                 smc_call(&regs);
1349                 if (regs.regs[0]) {
1350                         ret = -EINVAL;
1351                         break;
1352                 }
1353
1354                 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1355                       regs.regs[2]);
1356                 gd->bd->bi_dram[i].start = regs.regs[1];
1357                 gd->bd->bi_dram[i].size = regs.regs[2];
1358
1359                 dram_size -= gd->bd->bi_dram[i].size;
1360
1361                 i++;
1362         } while (dram_size);
1363
1364         if (i > 0)
1365                 ret = 0;
1366
1367 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1368         /* Assign memory for MC */
1369 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1370         if (gd->bd->bi_dram[2].size >=
1371             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1372                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1373                             gd->bd->bi_dram[2].size -
1374                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1375         } else
1376 #endif
1377         {
1378                 if (gd->bd->bi_dram[1].size >=
1379                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1380                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1381                                 gd->bd->bi_dram[1].size -
1382                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1383                 } else if (gd->bd->bi_dram[0].size >
1384                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1385                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1386                                 gd->bd->bi_dram[0].size -
1387                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1388                 }
1389         }
1390 #endif  /* CONFIG_FSL_MC_ENET */
1391
1392         return ret;
1393 }
1394 #endif
1395
1396 int dram_init_banksize(void)
1397 {
1398 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1399         phys_size_t dp_ddr_size;
1400 #endif
1401
1402 #ifdef CONFIG_TFABOOT
1403         if (!tfa_dram_init_banksize())
1404                 return 0;
1405 #endif
1406         /*
1407          * gd->ram_size has the total size of DDR memory, less reserved secure
1408          * memory. The DDR extends from low region to high region(s) presuming
1409          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1410          * the location of secure memory. gd->arch.resv_ram tracks the location
1411          * of reserved memory for Management Complex (MC). Because gd->ram_size
1412          * is reduced by this function if secure memory is reserved, checking
1413          * gd->arch.secure_ram should be done to avoid running it repeatedly.
1414          */
1415
1416 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1417         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1418                 debug("No need to run again, skip %s\n", __func__);
1419
1420                 return 0;
1421         }
1422 #endif
1423
1424         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1425         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1426                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1427                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1428                 gd->bd->bi_dram[1].size = gd->ram_size -
1429                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
1430 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1431                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1432                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1433                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1434                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
1435                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1436                 }
1437 #endif
1438         } else {
1439                 gd->bd->bi_dram[0].size = gd->ram_size;
1440         }
1441 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1442         if (gd->bd->bi_dram[0].size >
1443                                 CONFIG_SYS_MEM_RESERVE_SECURE) {
1444                 gd->bd->bi_dram[0].size -=
1445                                 CONFIG_SYS_MEM_RESERVE_SECURE;
1446                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1447                                       gd->bd->bi_dram[0].size;
1448                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1449                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1450         }
1451 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
1452
1453 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1454         /* Assign memory for MC */
1455 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1456         if (gd->bd->bi_dram[2].size >=
1457             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1458                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1459                             gd->bd->bi_dram[2].size -
1460                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1461         } else
1462 #endif
1463         {
1464                 if (gd->bd->bi_dram[1].size >=
1465                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1466                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1467                                 gd->bd->bi_dram[1].size -
1468                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1469                 } else if (gd->bd->bi_dram[0].size >
1470                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1471                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1472                                 gd->bd->bi_dram[0].size -
1473                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1474                 }
1475         }
1476 #endif  /* CONFIG_FSL_MC_ENET */
1477
1478 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1479 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1480 #error "This SoC shouldn't have DP DDR"
1481 #endif
1482         if (soc_has_dp_ddr()) {
1483                 /* initialize DP-DDR here */
1484                 puts("DP-DDR:  ");
1485                 /*
1486                  * DDR controller use 0 as the base address for binding.
1487                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1488                  */
1489                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1490                                           CONFIG_DP_DDR_CTRL,
1491                                           CONFIG_DP_DDR_NUM_CTRLS,
1492                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1493                                           NULL, NULL, NULL);
1494                 if (dp_ddr_size) {
1495                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1496                         gd->bd->bi_dram[2].size = dp_ddr_size;
1497                 } else {
1498                         puts("Not detected");
1499                 }
1500         }
1501 #endif
1502
1503 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1504         debug("%s is called. gd->ram_size is reduced to %lu\n",
1505               __func__, (ulong)gd->ram_size);
1506 #endif
1507
1508         return 0;
1509 }
1510
1511 #if CONFIG_IS_ENABLED(EFI_LOADER)
1512 void efi_add_known_memory(void)
1513 {
1514         int i;
1515         phys_addr_t ram_start, start;
1516         phys_size_t ram_size;
1517         u64 pages;
1518
1519         /* Add RAM */
1520         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1521 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1522 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1523 #error "This SoC shouldn't have DP DDR"
1524 #endif
1525                 if (i == 2)
1526                         continue;       /* skip DP-DDR */
1527 #endif
1528                 ram_start = gd->bd->bi_dram[i].start;
1529                 ram_size = gd->bd->bi_dram[i].size;
1530 #ifdef CONFIG_RESV_RAM
1531                 if (gd->arch.resv_ram >= ram_start &&
1532                     gd->arch.resv_ram < ram_start + ram_size)
1533                         ram_size = gd->arch.resv_ram - ram_start;
1534 #endif
1535                 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1536                 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1537
1538                 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1539                                    false);
1540         }
1541 }
1542 #endif
1543
1544 /*
1545  * Before DDR size is known, early MMU table have DDR mapped as device memory
1546  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1547  * needs to be set for these mappings.
1548  * If a special case configures DDR with holes in the mapping, the holes need
1549  * to be marked as invalid. This is not implemented in this function.
1550  */
1551 void update_early_mmu_table(void)
1552 {
1553         if (!gd->arch.tlb_addr)
1554                 return;
1555
1556         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1557                 mmu_change_region_attr(
1558                                         CONFIG_SYS_SDRAM_BASE,
1559                                         gd->ram_size,
1560                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1561                                         PTE_BLOCK_OUTER_SHARE           |
1562                                         PTE_BLOCK_NS                    |
1563                                         PTE_TYPE_VALID);
1564         } else {
1565                 mmu_change_region_attr(
1566                                         CONFIG_SYS_SDRAM_BASE,
1567                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1568                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1569                                         PTE_BLOCK_OUTER_SHARE           |
1570                                         PTE_BLOCK_NS                    |
1571                                         PTE_TYPE_VALID);
1572 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1573 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1574 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1575 #endif
1576                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1577                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
1578                         mmu_change_region_attr(
1579                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1580                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1581                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1582                                         PTE_BLOCK_OUTER_SHARE           |
1583                                         PTE_BLOCK_NS                    |
1584                                         PTE_TYPE_VALID);
1585                         mmu_change_region_attr(
1586                                         CONFIG_SYS_DDR_BLOCK3_BASE,
1587                                         gd->ram_size -
1588                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
1589                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1590                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1591                                         PTE_BLOCK_OUTER_SHARE           |
1592                                         PTE_BLOCK_NS                    |
1593                                         PTE_TYPE_VALID);
1594                 } else
1595 #endif
1596                 {
1597                         mmu_change_region_attr(
1598                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1599                                         gd->ram_size -
1600                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1601                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1602                                         PTE_BLOCK_OUTER_SHARE           |
1603                                         PTE_BLOCK_NS                    |
1604                                         PTE_TYPE_VALID);
1605                 }
1606         }
1607 }
1608
1609 __weak int dram_init(void)
1610 {
1611         fsl_initdram();
1612 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1613         defined(CONFIG_SPL_BUILD)
1614         /* This will break-before-make MMU for DDR */
1615         update_early_mmu_table();
1616 #endif
1617
1618         return 0;
1619 }