1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
7 #include "skeleton.dtsi"
8 #include "dt-bindings/clock/snps,hsdk-cgu.h"
9 #include "dt-bindings/reset/snps,hsdk-reset.h"
25 compatible = "fixed-clock";
26 clock-frequency = <500000000>;
32 clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
33 <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
34 <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
35 <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
36 <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
37 <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
38 <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
39 <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
40 <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
41 <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
42 <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
43 <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
44 <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
45 clock-names = "cpu-pll", "sys-pll",
47 "cpu-clk", "hdmi-pll",
48 "tun-clk", "hdmi-clk",
51 "sdio-clk", "hdmi-sys-clk",
52 "gfx-core-clk", "gfx-dma-clk",
53 "gfx-cfg-clk", "dmac-core-clk",
54 "dmac-cfg-clk", "sdio-ref-clk",
56 "uart-clk", "ebi-clk",
60 cgu_clk: cgu-clk@f0000000 {
61 compatible = "snps,hsdk-cgu-clock";
62 reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
66 cgu_rst: reset-controller@f00008a0 {
67 compatible = "snps,hsdk-reset";
69 reg = <0xf00008a0 0x4>, <0xf0000ff0 0x4>;
72 uart0: serial0@f0005000 {
73 compatible = "snps,dw-apb-uart";
74 reg = <0xf0005000 0x1000>;
80 #interrupt-cells = <1>;
81 compatible = "snps,arc-dwmac-3.70a";
82 reg = <0xf0008000 0x2000>;
87 compatible = "generic-ehci";
88 reg = <0xf0040000 0x100>;
92 compatible = "generic-ohci";
93 reg = <0xf0060000 0x100>;
96 mmcclk_ciu: mmcclk-ciu {
97 compatible = "fixed-clock";
99 * DW sdio controller has external ciu clock divider
100 * controlled via register in SDIO IP. Due to its
101 * unexpected default value (it should divide by 1
102 * but it divides by 8) SDIO IP uses wrong clock and
103 * works unstable (see STAR 9001204800)
104 * We switched to the minimum possible value of the
105 * divisor (div-by-2) in HSDK platform code.
106 * So default mmcclk ciu clock is 50000000 Hz.
108 clock-frequency = <50000000>;
113 compatible = "snps,dw-mshc";
114 reg = <0xf000a000 0x400>;
117 clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
118 clock-names = "biu", "ciu";
119 max-frequency = <25000000>;
123 compatible = "snps,dw-apb-ssi";
124 reg = <0xf0020000 0x1000>;
125 #address-cells = <1>;
127 spi-max-frequency = <4000000>;
128 clocks = <&cgu_clk CLK_SYS_SPI_REF>;
129 clock-names = "spi_clk";
130 cs-gpio = <&cs_gpio 0>;
132 compatible = "jedec,spi-nor";
134 spi-max-frequency = <4000000>;
138 cs_gpio: gpio@f00014b0 {
139 compatible = "snps,creg-gpio";
140 reg = <0xf00014b0 0x4>;
143 gpio-bank-name = "hsdk-spi-cs";
145 gpio-first-shift = <0>;
146 gpio-bit-per-line = <2>;
147 gpio-activate-val = <2>;
148 gpio-deactivate-val = <3>;
149 gpio-default-val = <1>;