Add support for PHY0/4 swap

diff --git a/u-boot/board/ar7240/common/athr_s27_phy.c b/u-boot/board/ar7240/common/athr_s27_phy.c
index ccdbebfca243d7e61cd7a0e42aba0ef0ea024a8f..6b0e196fc6bc1e192ead88b0222bf733901ceb01 100644 (file)
--- a/u-boot/board/ar7240/common/athr_s27_phy.c
+++ b/u-boot/board/ar7240/common/athr_s27_phy.c
@@ -112,7 +112,11 @@ static athrPhyInfo_t athrPhyInfo[] = {
 
     {TRUE,   /* port 1 -- LAN port 1 */
      FALSE,
+#if defined(CONFIG_QCA_ETH_PHY_SWAP)
+     ENET_UNIT_WAN,
+#else
      ENET_UNIT_LAN,
+#endif
      0,
      ATHR_PHY0_ADDR,
      ATHR_LAN_PORT_VLAN
@@ -145,7 +149,11 @@ static athrPhyInfo_t athrPhyInfo[] = {
 
     {TRUE,  /* port 5 -- WAN Port 5 */
      FALSE,
+#if defined(CONFIG_QCA_ETH_PHY_SWAP)
+     ENET_UNIT_LAN,
+#else
      ENET_UNIT_WAN,
+#endif
      0,
      ATHR_PHY4_ADDR,
      ATHR_LAN_PORT_VLAN    /* Send to all ports */
@@ -238,6 +246,12 @@ void athrs27_force_10M(int phyAddr,int duplex)
 
 int athrs27_reg_init(void)
 {
+#if defined(CONFIG_QCA_ETH_PHY_SWAP)
+       int phyWanAddr = ATHR_PHY0_ADDR;
+#else
+       int phyWanAddr = ATHR_PHY4_ADDR;
+#endif
+
 #ifdef S27_PHY_DEBUG
     uint32_t rd_val;
 #endif
@@ -247,11 +261,11 @@ int athrs27_reg_init(void)
     athrs27_reg_rmw(0x8,(1<<28));  /* Set WAN port is connected to GE0 */
 
 #if defined(S27_FORCE_100M)
-    athrs27_force_100M(ATHR_PHY4_ADDR,1);
+    athrs27_force_100M(phyWanAddr,1);
 #elif  defined(S27_FORCE_10M)
-    athrs27_force_10M(ATHR_PHY4_ADDR,1);
+    athrs27_force_10M(phyWanAddr,1);
 #else
-    s27_wr_phy(ATHR_PHY4_ADDR,ATHR_PHY_CONTROL,0x9000);
+    s27_wr_phy(phyWanAddr,ATHR_PHY_CONTROL,0x9000);
 
 #endif
 #ifdef S27_PHY_DEBUG

diff --git a/u-boot/board/ar7240/common/qca-eth-953x.c b/u-boot/board/ar7240/common/qca-eth-953x.c
index a3c9e3fa89ae051d7617786543a6ec56e3248cfa..bef38e20d41aa1a00318e866e01f51c2bdce7d52 100644 (file)
--- a/u-boot/board/ar7240/common/qca-eth-953x.c
+++ b/u-boot/board/ar7240/common/qca-eth-953x.c
@@ -176,6 +176,9 @@ void ath_gmac_mii_setup(ath_gmac_mac_t *mac)
        //ath_reg_wr(SWITCH_CLOCK_SPARE_ADDRESS, 0x520);
        if ((mac->mac_unit == 1)) {
                ath_reg_wr(ATH_ETH_CFG, ETH_CFG_ETH_RXDV_DELAY_SET(3) |
+#if defined(CONFIG_QCA_ETH_PHY_SWAP)
+                                       ATH_ETH_CFG_SW_PHY_SWAP |
+#endif
                                        ETH_CFG_ETH_RXD_DELAY_SET(3)|
                                        ETH_CFG_RGMII_GE0_SET(1));
 
@@ -192,6 +195,9 @@ void ath_gmac_mii_setup(ath_gmac_mac_t *mac)
 
        if (is_vir_phy()) {
                ath_reg_wr(ATH_ETH_CFG, ETH_CFG_ETH_RXDV_DELAY_SET(3) |
+#if defined(CONFIG_QCA_ETH_PHY_SWAP)
+                                       ATH_ETH_CFG_SW_PHY_SWAP |
+#endif
                                        ETH_CFG_ETH_RXD_DELAY_SET(3)|
                                        ETH_CFG_RGMII_GE0_SET(1));
                ath_reg_wr(ETH_XMII_ADDRESS, ETH_XMII_TX_INVERT_SET(1) |
@@ -207,6 +213,9 @@ void ath_gmac_mii_setup(ath_gmac_mac_t *mac)
        if (is_s27()) {
                mgmt_cfg_val = 2;
                ath_reg_wr(ETH_CFG_ADDRESS, ETH_CFG_MII_GE0_SET(1)|
+#if defined(CONFIG_QCA_ETH_PHY_SWAP)
+                                       ATH_ETH_CFG_SW_PHY_SWAP |
+#endif
                                         ETH_CFG_MII_GE0_SLAVE_SET(1));
                udelay(1000);
                ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));