Restore workaround for AR9331 hang on soft reset

Restore workaround for AR9331 hang on soft reset

This workaround was already included in ff7a030 and then removed in
d9ba54f. As it turned out, it's critical and required.

Tests showed that on some devices with AR9331, CPU PLL doesn't lock
after a soft reset with AHB clock divider lower than 4. In original code
from Qualcomm Atheros SDK, AHB clock divider is set to 4 before CPU PLL
is powered up. Then, when PLL update is done, divider is set to target
value.

Tests were made on multiple devices, with DDR1, DDR2 and different
AR9331 chip revisions: -AL1A, -AL2A and -AL3A. Unfortunately, the
problem exists in every configuration type, isn't related with chip
revision and is reproductible.

Without this workaround, some devices hangs at waiting for CPU PLL
update process to finish and can be recovered from this state only
with a hard reset.