From 2795573a8c9c62db7b4bcf4bddf54d73b6ae61d3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 12 Dec 2014 21:05:23 +0800 Subject: [PATCH] x86: ich6-gpio: Move setup_pch_gpios() to board support codes Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/include/asm/arch-coreboot/gpio.h | 3 ++ arch/x86/include/asm/arch-ivybridge/gpio.h | 3 ++ arch/x86/include/asm/gpio.h | 1 + board/coreboot/coreboot/coreboot.c | 6 +++ board/google/chromebook_link/link.c | 40 ++++++++++++++++ drivers/gpio/intel_ich6_gpio.c | 53 +--------------------- 6 files changed, 55 insertions(+), 51 deletions(-) diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h index 4951a8c957..31edef9623 100644 --- a/arch/x86/include/asm/arch-coreboot/gpio.h +++ b/arch/x86/include/asm/arch-coreboot/gpio.h @@ -7,4 +7,7 @@ #ifndef _X86_ARCH_GPIO_H_ #define _X86_ARCH_GPIO_H_ +/* Where in config space is the register that points to the GPIO registers? */ +#define PCI_CFG_GPIOBASE 0x48 + #endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h index 4951a8c957..31edef9623 100644 --- a/arch/x86/include/asm/arch-ivybridge/gpio.h +++ b/arch/x86/include/asm/arch-ivybridge/gpio.h @@ -7,4 +7,7 @@ #ifndef _X86_ARCH_GPIO_H_ #define _X86_ARCH_GPIO_H_ +/* Where in config space is the register that points to the GPIO registers? */ +#define PCI_CFG_GPIOBASE 0x48 + #endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index 5540d422b4..1787e5210c 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -147,6 +147,7 @@ struct pch_gpio_map { } set3; }; +void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio); void ich_gpio_set_gpio_map(const struct pch_gpio_map *map); #endif /* _X86_GPIO_H_ */ diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index 0240c34581..b260f9a163 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -6,6 +6,7 @@ #include #include +#include int arch_early_init_r(void) { @@ -14,3 +15,8 @@ int arch_early_init_r(void) return 0; } + +void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 1822237dd8..4d95c1c927 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -7,6 +7,9 @@ #include #include #include +#include +#include +#include int arch_early_init_r(void) { @@ -121,3 +124,40 @@ int board_early_init_f(void) return 0; } + +void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio) +{ + /* GPIO Set 1 */ + if (gpio->set1.level) + outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); + if (gpio->set1.mode) + outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); + if (gpio->set1.direction) + outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); + if (gpio->set1.reset) + outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); + if (gpio->set1.invert) + outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); + if (gpio->set1.blink) + outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); + + /* GPIO Set 2 */ + if (gpio->set2.level) + outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); + if (gpio->set2.mode) + outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); + if (gpio->set2.direction) + outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); + if (gpio->set2.reset) + outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); + + /* GPIO Set 3 */ + if (gpio->set3.level) + outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); + if (gpio->set3.mode) + outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); + if (gpio->set3.direction) + outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); + if (gpio->set3.reset) + outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); +} diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 92c23aed4c..3433216cb6 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -34,16 +34,9 @@ #include #include #include -#ifdef CONFIG_X86_RESET_VECTOR -#include -#define SUPPORT_GPIO_SETUP -#endif #define GPIO_PER_BANK 32 -/* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x48 - struct ich6_bank_priv { /* These are I/O addresses */ uint32_t use_sel; @@ -51,52 +44,11 @@ struct ich6_bank_priv { uint32_t lvl; }; -#ifdef SUPPORT_GPIO_SETUP -static void setup_pch_gpios(const struct pch_gpio_map *gpio) -{ - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - - /* GPIO Set 1 */ - if (gpio->set1.level) - outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL); - if (gpio->set1.mode) - outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL); - if (gpio->set1.direction) - outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL); - if (gpio->set1.reset) - outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1); - if (gpio->set1.invert) - outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV); - if (gpio->set1.blink) - outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK); - - /* GPIO Set 2 */ - if (gpio->set2.level) - outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2); - if (gpio->set2.mode) - outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); - if (gpio->set2.direction) - outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2); - if (gpio->set2.reset) - outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2); - - /* GPIO Set 3 */ - if (gpio->set3.level) - outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3); - if (gpio->set3.mode) - outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); - if (gpio->set3.direction) - outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3); - if (gpio->set3.reset) - outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3); -} - /* TODO: Move this to device tree, or platform data */ void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) { gd->arch.gpio_map = map; } -#endif /* SUPPORT_GPIO_SETUP */ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) { @@ -198,12 +150,11 @@ static int ich6_gpio_probe(struct udevice *dev) struct gpio_dev_priv *uc_priv = dev->uclass_priv; struct ich6_bank_priv *bank = dev_get_priv(dev); -#ifdef SUPPORT_GPIO_SETUP if (gd->arch.gpio_map) { - setup_pch_gpios(gd->arch.gpio_map); + setup_pch_gpios(plat->base_addr, gd->arch.gpio_map); gd->arch.gpio_map = NULL; } -#endif + uc_priv->gpio_count = GPIO_PER_BANK; uc_priv->bank_name = plat->bank_name; bank->use_sel = plat->base_addr; -- 2.25.1