From: Horatiu Vultur Date: Wed, 24 Apr 2019 09:27:59 +0000 (+0200) Subject: net: mscc: ocelot: Update DTS for Ocelot pcb120. X-Git-Tag: v2019.07-rc2~21^2~4 X-Git-Url: https://git.librecmc.org/?p=oweals%2Fu-boot.git;a=commitdiff_plain;h=8c211af8f8c0617c40ccf4f0df557e4fbf6073ea net: mscc: ocelot: Update DTS for Ocelot pcb120. Update device tree for ocelot to add support for ocelot pcb120. Signed-off-by: Horatiu Vultur --- diff --git a/MAINTAINERS b/MAINTAINERS index 09f31cd483..6035623fc4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -577,6 +577,7 @@ F: configs/mscc* F: drivers/gpio/mscc_sgpio.c F: drivers/spi/mscc_bb_spi.c F: include/configs/vcoreiii.h +F: include/dt-bindings/mscc/ F: drivers/pinctrl/mscc/ F: drivers/net/mscc_eswitch/ diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi index 4f3fe356c4..9a187b6e58 100644 --- a/arch/mips/dts/mscc,ocelot.dtsi +++ b/arch/mips/dts/mscc,ocelot.dtsi @@ -112,32 +112,33 @@ status = "disabled"; }; - switch@1010000 { + switch: switch@1010000 { pinctrl-0 = <&miim1_pins>; pinctrl-names = "default"; compatible = "mscc,vsc7514-switch"; - reg = <0x1010000 0x10000>, /* VTSS_TO_SYS */ - <0x1030000 0x10000>, /* VTSS_TO_REW */ - <0x1080000 0x100>, /* VTSS_TO_DEVCPU_QS */ - <0x10d0000 0x10000>, /* VTSS_TO_HSIO */ - <0x11e0000 0x100>, /* VTSS_TO_DEV_0 */ - <0x11f0000 0x100>, /* VTSS_TO_DEV_1 */ - <0x1200000 0x100>, /* VTSS_TO_DEV_2 */ - <0x1210000 0x100>, /* VTSS_TO_DEV_3 */ - <0x1220000 0x100>, /* VTSS_TO_DEV_4 */ - <0x1230000 0x100>, /* VTSS_TO_DEV_5 */ - <0x1240000 0x100>, /* VTSS_TO_DEV_6 */ - <0x1250000 0x100>, /* VTSS_TO_DEV_7 */ - <0x1260000 0x100>, /* VTSS_TO_DEV_8 */ - <0x1270000 0x100>, /* NA */ - <0x1280000 0x100>, /* NA */ - <0x1800000 0x80000>, /* VTSS_TO_QSYS */ - <0x1880000 0x10000>; /* VTSS_TO_ANA */ - reg-names = "sys", "rew", "qs", "hsio", "port0", - "port1", "port2", "port3", "port4", "port5", - "port6", "port7", "port8", "port9", - "port10", "qsys", "ana"; + + reg = <0x11e0000 0x100>, // VTSS_TO_DEV_0 + <0x11f0000 0x100>, // VTSS_TO_DEV_1 + <0x1200000 0x100>, // VTSS_TO_DEV_2 + <0x1210000 0x100>, // VTSS_TO_DEV_3 + <0x1220000 0x100>, // VTSS_TO_DEV_4 + <0x1230000 0x100>, // VTSS_TO_DEV_5 + <0x1240000 0x100>, // VTSS_TO_DEV_6 + <0x1250000 0x100>, // VTSS_TO_DEV_7 + <0x1260000 0x100>, // VTSS_TO_DEV_8 + <0x1270000 0x100>, // VTSS_TO_DEV_9 + <0x1280000 0x100>, // VTSS_TO_DEV_10 + <0x1010000 0x10000>, // VTSS_TO_SYS + <0x1030000 0x10000>, // VTSS_TO_REW + <0x1080000 0x100>, // VTSS_TO_DEVCPU_QS + <0x10d0000 0x10000>, // VTSS_TO_HSIO + <0x1800000 0x80000>,// VTSS_TO_QSYS + <0x1880000 0x10000>;// VTSS_TO_ANA + reg-names = "port0", "port1", "port2", "port3", "port4", + "port5", "port6", "port7", "port8", "port9", + "port10", + "sys", "rew", "qs", "hsio", "qsys", "ana"; interrupts = <21 22>; interrupt-names = "xtr", "inj"; status = "okay"; @@ -145,40 +146,6 @@ ethernet-ports { #address-cells = <1>; #size-cells = <0>; - - port0: port@0 { - reg = <0>; - }; - port1: port@1 { - reg = <1>; - }; - port2: port@2 { - reg = <2>; - }; - port3: port@3 { - reg = <3>; - }; - port4: port@4 { - reg = <4>; - }; - port5: port@5 { - reg = <5>; - }; - port6: port@6 { - reg = <6>; - }; - port7: port@7 { - reg = <7>; - }; - port8: port@8 { - reg = <8>; - }; - port9: port@9 { - reg = <9>; - }; - port10: port@10 { - reg = <10>; - }; }; }; @@ -186,21 +153,27 @@ #address-cells = <1>; #size-cells = <0>; compatible = "mscc,ocelot-miim"; - reg = <0x107009c 0x24>, <0x10700f0 0x8>; + reg = <0x107009c 0x24>; interrupts = <14>; status = "disabled"; + }; - phy0: ethernet-phy@0 { - reg = <0>; - }; - phy1: ethernet-phy@1 { - reg = <1>; - }; - phy2: ethernet-phy@2 { - reg = <2>; - }; - phy3: ethernet-phy@3 { - reg = <3>; + mdio1: mdio@10700f0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,ocelot-miim"; + reg = <0x10700c0 0x24>; + interrupts = <14>; + status = "disabled"; + }; + + hsio: syscon@10d0000 { + compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd"; + reg = <0x10d0000 0x10000>; + + serdes_hsio: serdes_hsio { + compatible = "mscc,vsc7514-serdes"; + #phy-cells = <3>; }; }; diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts index 658719e684..e608029a3f 100644 --- a/arch/mips/dts/ocelot_pcb120.dts +++ b/arch/mips/dts/ocelot_pcb120.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "mscc,ocelot_pcb.dtsi" +#include / { model = "Ocelot PCB120 Reference Board"; @@ -86,3 +87,77 @@ mscc,sgpio-ports = <0x000FFFFF>; }; +&mdio0 { + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <3>; + }; + phy5: ethernet-phy@5 { + reg = <2>; + }; + phy6: ethernet-phy@6 { + reg = <1>; + }; + phy7: ethernet-phy@7 { + reg = <0>; + }; +}; + +&mdio1 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <3>; + }; + phy1: ethernet-phy@1 { + reg = <2>; + }; + phy2: ethernet-phy@2 { + reg = <1>; + }; + phy3: ethernet-phy@3 { + reg = <0>; + }; +}; + +&switch { + ethernet-ports { + port0: port@0 { + reg = <5>; + phy-handle = <&phy0>; + phys = <&serdes_hsio 5 SERDES1G(2) PHY_MODE_SGMII>; + }; + port1: port@1 { + reg = <9>; + phy-handle = <&phy1>; + phys = <&serdes_hsio 9 SERDES1G(3) PHY_MODE_SGMII>; + }; + port2: port@2 { + reg = <6>; + phy-handle = <&phy2>; + phys = <&serdes_hsio 6 SERDES1G(4) PHY_MODE_SGMII>; + }; + port3: port@3 { + reg = <4>; + phy-handle = <&phy3>; + phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>; + }; + port4: port@4 { + reg = <3>; + phy-handle = <&phy4>; + }; + port5: port@5 { + reg = <2>; + phy-handle = <&phy5>; + }; + port6: port@6 { + reg = <1>; + phy-handle = <&phy6>; + }; + port7: port@7 { + reg = <0>; + phy-handle = <&phy7>; + }; + }; +}; diff --git a/arch/mips/dts/ocelot_pcb123.dts b/arch/mips/dts/ocelot_pcb123.dts index a4fa37001f..1b0156e503 100644 --- a/arch/mips/dts/ocelot_pcb123.dts +++ b/arch/mips/dts/ocelot_pcb123.dts @@ -38,20 +38,38 @@ &mdio0 { status = "okay"; -}; - -&port0 { - phy-handle = <&phy0>; -}; -&port1 { - phy-handle = <&phy1>; -}; - -&port2 { - phy-handle = <&phy2>; + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; }; -&port3 { - phy-handle = <&phy3>; +&switch { + ethernet-ports { + port0: port@0 { + reg = <2>; + phy-handle = <&phy2>; + }; + port1: port@1 { + reg = <3>; + phy-handle = <&phy3>; + }; + port2: port@2 { + reg = <0>; + phy-handle = <&phy0>; + }; + port3: port@3 { + reg = <1>; + phy-handle = <&phy1>; + }; + }; }; diff --git a/include/dt-bindings/mscc/ocelot_data.h b/include/dt-bindings/mscc/ocelot_data.h new file mode 100644 index 0000000000..7a5a1bf36e --- /dev/null +++ b/include/dt-bindings/mscc/ocelot_data.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Microsemi Corporation + */ + +#ifndef _OCELOT_DATA_H_ +#define _OCELOT_DATA_H_ + +#define SERDES1G(x) (x) +#define SERDES1G_MAX SERDES1G(7) +#define SERDES6G(x) (SERDES1G_MAX + 1 + (x)) +#define SERDES6G_MAX SERDES6G(11) +#define SERDES_MAX (SERDES6G_MAX + 1) + +/* similar with phy_interface_t */ +#define PHY_MODE_SGMII 2 +#define PHY_MODE_QSGMII 4 + +#endif