From: Tom Rini Date: Mon, 4 May 2020 11:28:14 +0000 (-0400) Subject: Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians... X-Git-Tag: v2020.07-rc2~17 X-Git-Url: https://git.librecmc.org/?p=oweals%2Fu-boot.git;a=commitdiff_plain;h=04da42770b0cc3bea8841972bfc9568299ece826;hp=1d5d0275d7684005643952b4591eb5899f55beaf Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - dts clean up to use -u-boot for px30, rk3399 boards - dts sycn from upstream kernel for rk3328, rk3399 - add rockchip rng driver - new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB --- diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2c123bd6da..c57a6460c6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ + rk3328-roc-cc.dtb \ rk3328-rock64.dtb dtb-$(CONFIG_ROCKCHIP_RK3368) += \ @@ -125,12 +126,14 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-leez-p710.dtb \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ + rk3399-nanopi-m4-2gb.dtb \ rk3399-nanopi-neo4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ rk3399-roc-pc.dtb \ + rk3399-roc-pc-mezzanine.dtb \ rk3399-rock-pi-4.dtb \ rk3399-rock960.dtb \ rk3399-rockpro64.dtb diff --git a/arch/arm/dts/cros-ec-keyboard.dtsi b/arch/arm/dts/cros-ec-keyboard.dtsi index 9c7fb0acae..4a0c1037fb 100644 --- a/arch/arm/dts/cros-ec-keyboard.dtsi +++ b/arch/arm/dts/cros-ec-keyboard.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Keyboard dts fragment for devices that use cros-ec-keyboard * * Copyright (c) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include @@ -22,6 +19,7 @@ MATRIX_KEY(0x00, 0x02, KEY_F1) MATRIX_KEY(0x00, 0x03, KEY_B) MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x05, KEY_RO) MATRIX_KEY(0x00, 0x06, KEY_N) MATRIX_KEY(0x00, 0x08, KEY_EQUAL) MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) @@ -34,6 +32,7 @@ MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) MATRIX_KEY(0x01, 0x09, KEY_F9) MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + MATRIX_KEY(0x01, 0x0c, KEY_HENKAN) MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) MATRIX_KEY(0x02, 0x01, KEY_TAB) @@ -45,6 +44,7 @@ MATRIX_KEY(0x02, 0x07, KEY_102ND) MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) MATRIX_KEY(0x02, 0x09, KEY_F8) + MATRIX_KEY(0x02, 0x0a, KEY_YEN) MATRIX_KEY(0x03, 0x01, KEY_GRAVE) MATRIX_KEY(0x03, 0x02, KEY_F2) @@ -52,7 +52,9 @@ MATRIX_KEY(0x03, 0x04, KEY_F5) MATRIX_KEY(0x03, 0x06, KEY_6) MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x09, KEY_F13) MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN) MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) MATRIX_KEY(0x04, 0x01, KEY_A) diff --git a/arch/arm/dts/cros-ec-sbs.dtsi b/arch/arm/dts/cros-ec-sbs.dtsi index dfe5ea6ca2..71f5c5ecce 100644 --- a/arch/arm/dts/cros-ec-sbs.dtsi +++ b/arch/arm/dts/cros-ec-sbs.dtsi @@ -1,8 +1,45 @@ -// SPDX-License-Identifier: GPL-2.0 /* * Smart battery dts fragment for devices that use cros-ec-sbs * * Copyright (c) 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ &i2c_tunnel { diff --git a/arch/arm/dts/px30-evb-u-boot.dtsi b/arch/arm/dts/px30-evb-u-boot.dtsi index a2a2c07dcc..61b1433af9 100644 --- a/arch/arm/dts/px30-evb-u-boot.dtsi +++ b/arch/arm/dts/px30-evb-u-boot.dtsi @@ -1,84 +1,10 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 Rockchip Electronics Co., Ltd */ -/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdmmc; - }; +#include "px30-u-boot.dtsi" - chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; - }; -}; - -&dmc { - u-boot,dm-pre-reloc; -}; - -&uart2 { - clock-frequency = <24000000>; - u-boot,dm-pre-reloc; -}; - -&uart5 { - clock-frequency = <24000000>; - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; - - /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ - u-boot,spl-fifo-mode; -}; - -&emmc { - u-boot,dm-pre-reloc; - - /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ - u-boot,spl-fifo-mode; -}; - -&grf { - u-boot,dm-pre-reloc; -}; - -&pmugrf { - u-boot,dm-pre-reloc; -}; - -&xin24m { - u-boot,dm-pre-reloc; -}; - -&cru { - u-boot,dm-pre-reloc; -}; - -&pmucru { - u-boot,dm-pre-reloc; -}; - -&saradc { - u-boot,dm-pre-reloc; +&rng { status = "okay"; }; - -&gpio0 { - u-boot,dm-pre-reloc; -}; - -&gpio1 { - u-boot,dm-pre-reloc; -}; - -&gpio2 { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts index d886f17242..4134e2ee13 100644 --- a/arch/arm/dts/px30-evb.dts +++ b/arch/arm/dts/px30-evb.dts @@ -8,7 +8,6 @@ #include #include #include "px30.dtsi" -#include "px30-evb-u-boot.dtsi" / { model = "Rockchip PX30 EVB"; diff --git a/arch/arm/dts/px30-firefly-u-boot.dtsi b/arch/arm/dts/px30-firefly-u-boot.dtsi index bb782b4e2d..aea9f4d6e5 100644 --- a/arch/arm/dts/px30-firefly-u-boot.dtsi +++ b/arch/arm/dts/px30-firefly-u-boot.dtsi @@ -1,84 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 Rockchip Electronics Co., Ltd */ -/ { - aliases { - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; - }; -}; - -&dmc { - u-boot,dm-pre-reloc; -}; - -&uart2 { - clock-frequency = <24000000>; - u-boot,dm-pre-reloc; -}; - -&uart5 { - clock-frequency = <24000000>; - u-boot,dm-pre-reloc; -}; - -&sdmmc { - u-boot,dm-pre-reloc; - - /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ - u-boot,spl-fifo-mode; -}; - -&emmc { - u-boot,dm-pre-reloc; - - /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ - u-boot,spl-fifo-mode; -}; - -&grf { - u-boot,dm-pre-reloc; -}; - -&pmugrf { - u-boot,dm-pre-reloc; -}; - -&xin24m { - u-boot,dm-pre-reloc; -}; - -&cru { - u-boot,dm-pre-reloc; -}; - -&pmucru { - u-boot,dm-pre-reloc; -}; - -&saradc { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&gpio0 { - u-boot,dm-pre-reloc; -}; - -&gpio1 { - u-boot,dm-pre-reloc; -}; - -&gpio2 { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; +#include "px30-u-boot.dtsi" diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi new file mode 100644 index 0000000000..029c8fbd8d --- /dev/null +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; + + rng: rng@ff0b0000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xff0b0000 0x0 0x4000>; + status = "disabled"; + }; +}; + +&dmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; + +&uart5 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&emmc { + u-boot,dm-pre-reloc; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&xin24m { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&pmucru { + u-boot,dm-pre-reloc; +}; + +&saradc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio0 { + u-boot,dm-pre-reloc; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 4a827063c5..4bfa0c2330 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -6,6 +6,45 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr3-666.dtsi" +/{ + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc5v0_host_xhci: vcc5v0-host-xhci-drv { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_host_xhci"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&gmac2io { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gmac2phy { + /* Integrated PHY unsupported by U-boot */ + status = "broken"; +}; + &usb_host0_xhci { vbus-supply = <&vcc5v0_host_xhci>; status = "okay"; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index a2ee838fcd..6abc6f4a86 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd */ /dts-v1/; @@ -11,40 +11,51 @@ compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; chosen { - stdout-path = &uart2; + stdout-path = "serial2:1500000n8"; }; - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - vcc3v3_sdmmc: sdmmc-pwren { + dc_12v: dc-12v { compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + regulator-name = "dc_12v"; regulator-always-on; regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; }; - vcc5v0_otg: vcc5v0-otg-drv { + vcc_sd: sdmmc-regulator { compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; }; - vcc5v0_host_xhci: vcc5v0-host-xhci-drv { + vcc_sys: vcc-sys { compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc5v0_host_xhci"; - gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; }; vcc_phy: vcc-phy-regulator { @@ -55,96 +66,60 @@ }; }; -&saradc { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; - status = "okay"; +&cpu0 { + cpu-supply = <&vdd_arm>; }; &emmc { bus-width = <8>; cap-mmc-highspeed; - supports-emmc; - disable-wp; non-removable; - num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; status = "okay"; }; -&gmac2io { +&gmac2phy { phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - tx_delay = <0x26>; - rx_delay = <0x11>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; + clock_in_out = "output"; + assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; -&usb_host0_ohci { - status = "okay"; -}; - -&usb20_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; }; &i2c1 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; status = "okay"; rk805: pmic@18 { compatible = "rockchip,rk805"; - status = "okay"; reg = <0x18>; interrupt-parent = <&gpio2>; interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; rockchip,system-power-controller; wakeup-source; - gpio-controller; - #gpio-cells = <2>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; regulators { vdd_logic: DCDC_REG1 { regulator-name = "vdd_logic"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <6001>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1000000>; @@ -155,19 +130,18 @@ regulator-name = "vdd_arm"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <6001>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; + regulator-suspend-microvolt = <950000>; }; }; vcc_ddr: DCDC_REG3 { regulator-name = "vcc_ddr"; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; }; @@ -177,32 +151,32 @@ regulator-name = "vcc_io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3300000>; }; }; - vdd_18: LDO_REG1 { - regulator-name = "vdd_18"; + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; }; }; - vcc_18emmc: LDO_REG2 { - regulator-name = "vcc_18emmc"; + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; @@ -213,8 +187,8 @@ regulator-name = "vdd_10"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1000000>; @@ -227,9 +201,71 @@ &pinctrl { pmic { pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { rockchip,pins = - <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio2_a6 */ + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi new file mode 100644 index 0000000000..e929d86e30 --- /dev/null +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd + */ + +#include "rk3328-u-boot.dtsi" +#include "rk3328-sdram-ddr4-666.dtsi" +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&pinctrl { + u-boot,dm-spl; +}; + +&sdmmc0m1_gpio { + u-boot,dm-spl; +}; + +&pcfg_pull_up_4ma { + u-boot,dm-spl; +}; + +&usb_host0_xhci { + vbus-supply = <&vcc_host1_5v>; + status = "okay"; +}; + +/* + * This makes XHCI responsible for toggling VBUS. This is needed to work + * around an issue where either XHCI only works with USB 2.0 or OTG doesn't + * work, depending on how VBUS is configured. Having USB 3.0 seems better. + */ +&vcc_host1_5v { + /delete-property/ regulator-always-on; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts new file mode 100644 index 0000000000..8d553c9218 --- /dev/null +++ b/arch/arm/dts/rk3328-roc-cc.dts @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Firefly roc-rk3328-cc"; + compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_sdio: sdmmcio-regulator { + compatible = "regulator-gpio"; + gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3300000 0x0>; + regulator-name = "vcc_sdio"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "firefly:blue:power"; + linux,default-trigger = "heartbeat"; + gpios = <&rk805 1 GPIO_ACTIVE_LOW>; + default-state = "on"; + mode = <0x23>; + }; + + user { + label = "firefly:yellow:user"; + linux,default-trigger = "mmc1"; + gpios = <&rk805 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + mode = <0x05>; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,aal; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,rxpbl = <0x4>; + snps,txpbl = <0x4>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_sdio>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index e5946d2d2d..8318bf4e60 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -12,5 +12,16 @@ }; &usb_host0_xhci { + vbus-supply = <&vcc_host_5v>; status = "okay"; }; + +/* + * This makes XHCI responsible for toggling VBUS. This is needed to work + * around an issue where either XHCI only works with USB 2.0 or OTG doesn't + * work, depending on how VBUS is configured. Having USB 3.0 seems better. + */ +&vcc_host_5v { + /delete-property/ regulator-always-on; + /delete-property/ regulator-boot-on; +}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index a78eb4ac6f..ebf3eb222e 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -43,6 +43,17 @@ vin-supply = <&vcc_sys>; }; + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + vcc_sys: vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -51,6 +62,56 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + + leds { + compatible = "gpio-leds"; + + power { + gpios = <&rk805 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + standby { + gpios = <&rk805 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "rockchip,rk3328"; + dais = <&i2s1_p0 + &spdif_p0>; + }; + + spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port { + dit_p0_0: endpoint { + remote-endpoint = <&spdif_p0_0>; + }; + }; + }; +}; + +&codec { + mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + port@0 { + codec_p0_0: endpoint { + remote-endpoint = <&i2s1_p0_0>; + }; + }; }; &cpu0 { @@ -98,16 +159,26 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + &i2c1 { status = "okay"; - rk805: rk805@18 { + rk805: pmic@18 { compatible = "rockchip,rk805"; reg = <0x18>; interrupt-parent = <&gpio2>; interrupts = <6 IRQ_TYPE_LEVEL_LOW>; #clock-cells = <1>; clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; rockchip,system-power-controller; @@ -169,7 +240,7 @@ }; vcc_18: LDO_REG1 { - regulator-name = "vdd_18"; + regulator-name = "vcc_18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -181,7 +252,7 @@ }; vcc18_emmc: LDO_REG2 { - regulator-name = "vcc_18emmc"; + regulator-name = "vcc18_emmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -207,6 +278,18 @@ }; }; +&i2s1 { + status = "okay"; + + i2s1_p0: port { + i2s1_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&codec_p0_0>; + }; + }; +}; + &io_domains { status = "okay"; @@ -220,6 +303,12 @@ }; &pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; @@ -245,6 +334,17 @@ status = "okay"; }; +&spdif { + pinctrl-0 = <&spdifm0_tx>; + status = "okay"; + + spdif_p0: port { + spdif_p0_0: endpoint { + remote-endpoint = <&dit_p0_0>; + }; + }; +}; + &spi0 { status = "okay"; @@ -257,10 +357,28 @@ }; }; +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + &uart2 { status = "okay"; }; +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + &usb20_otg { dr_mode = "host"; status = "okay"; @@ -273,3 +391,11 @@ &usb_host0_ohci { status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index 6d5b3ec06e..c69e13e11e 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -62,3 +62,7 @@ /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ u-boot,spl-fifo-mode; }; + +&usb20_otg { + hnp-srp-disable; +}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 060c84e6c0..945387e579 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd */ #include @@ -8,6 +8,9 @@ #include #include #include +#include +#include +#include / { compatible = "rockchip,rk3328"; @@ -24,9 +27,8 @@ i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; - mmc0 = &emmc; - mmc1 = &sdmmc; - mmc2 = &sdmmc_ext; + ethernet0 = &gmac2io; + ethernet1 = &gmac2phy; }; cpus { @@ -35,29 +37,71 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; enable-method = "psci"; -// clocks = <&cru ARMCLK>; + next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; }; + cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; }; + cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; }; + cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + }; + + l2: l2-cache0 { + compatible = "cache"; }; }; @@ -65,39 +109,72 @@ compatible = "operating-points-v2"; opp-shared; - opp@408000000 { + opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <950000>; clock-latency-ns = <40000>; opp-suspend; }; - opp@600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <950000>; clock-latency-ns = <40000>; }; - opp@816000000 { + opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1000000>; clock-latency-ns = <40000>; }; - opp@1008000000 { + opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1100000>; clock-latency-ns = <40000>; }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1225000>; clock-latency-ns = <40000>; }; - opp@1296000000 { + opp-1296000000 { opp-hz = /bits/ 64 <1296000000>; opp-microvolt = <1300000>; clock-latency-ns = <40000>; }; }; + amba: bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac: dmac@ff1f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff1f0000 0x0 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + }; + + analog_sound: analog-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "Analog"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = , @@ -107,8 +184,29 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "HDMI"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + psci { - compatible = "arm,psci-1.0"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; @@ -134,8 +232,8 @@ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 11>, <&dmac 12>; - #dma-cells = <2>; dma-names = "tx", "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -146,8 +244,8 @@ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 14>, <&dmac 15>; - #dma-cells = <2>; dma-names = "tx", "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -158,16 +256,8 @@ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac 0>, <&dmac 1>; - #dma-cells = <2>; dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2s2m0_mclk - &i2s2m0_sclk - &i2s2m0_lrcktx - &i2s2m0_lrckrx - &i2s2m0_sdo - &i2s2m0_sdi>; - pinctrl-1 = <&i2s2m0_sleep>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -178,10 +268,31 @@ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; clock-names = "mclk", "hclk"; dmas = <&dmac 10>; - #dma-cells = <1>; dma-names = "tx"; pinctrl-names = "default"; pinctrl-0 = <&spdifm2_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm: pdm@ff040000 { + compatible = "rockchip,pdm"; + reg = <0x0 0xff040000 0x0 0x1000>; + clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac 16>; + dma-names = "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pdmm0_clk + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + pinctrl-1 = <&pdmm0_clk_sleep + &pdmm0_sdi0_sleep + &pdmm0_sdi1_sleep + &pdmm0_sdi2_sleep + &pdmm0_sdi3_sleep>; status = "disabled"; }; @@ -193,6 +304,39 @@ compatible = "rockchip,rk3328-io-voltage-domain"; status = "disabled"; }; + + grf_gpio: grf-gpio { + compatible = "rockchip,rk3328-grf-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + power: power-controller { + compatible = "rockchip,rk3328-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hevc@RK3328_PD_HEVC { + reg = ; + }; + pd_video@RK3328_PD_VIDEO { + reg = ; + }; + pd_vpu@RK3328_PD_VPU { + reg = ; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + }; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x5c8>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; }; uart0: serial@ff110000 { @@ -201,12 +345,12 @@ interrupts = ; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; dmas = <&dmac 2>, <&dmac 3>; - #dma-cells = <2>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + reg-io-width = <4>; + reg-shift = <2>; status = "disabled"; }; @@ -215,13 +359,13 @@ reg = <0x0 0xff120000 0x0 0x100>; interrupts = ; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "sclk_uart", "pclk_uart"; - reg-shift = <2>; - reg-io-width = <4>; + clock-names = "baudclk", "apb_pclk"; dmas = <&dmac 4>, <&dmac 5>; - #dma-cells = <2>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; + reg-io-width = <4>; + reg-shift = <2>; status = "disabled"; }; @@ -231,22 +375,17 @@ interrupts = ; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; dmas = <&dmac 6>, <&dmac 7>; - #dma-cells = <2>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart2m1_xfer>; + reg-io-width = <4>; + reg-shift = <2>; status = "disabled"; }; - pmu: power-management@ff140000 { - compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff140000 0x0 0x1000>; - }; - i2c0: i2c@ff150000 { - compatible = "rockchip,rk3328-i2c"; + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff150000 0x0 0x1000>; interrupts = ; #address-cells = <1>; @@ -259,7 +398,7 @@ }; i2c1: i2c@ff160000 { - compatible = "rockchip,rk3328-i2c"; + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff160000 0x0 0x1000>; interrupts = ; #address-cells = <1>; @@ -272,7 +411,7 @@ }; i2c2: i2c@ff170000 { - compatible = "rockchip,rk3328-i2c"; + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff170000 0x0 0x1000>; interrupts = ; #address-cells = <1>; @@ -285,7 +424,7 @@ }; i2c3: i2c@ff180000 { - compatible = "rockchip,rk3328-i2c"; + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff180000 0x0 0x1000>; interrupts = ; #address-cells = <1>; @@ -306,7 +445,6 @@ clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; clock-names = "spiclk", "apb_pclk"; dmas = <&dmac 8>, <&dmac 9>; - #dma-cells = <2>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; @@ -317,28 +455,141 @@ compatible = "snps,dw-wdt"; reg = <0x0 0xff1a0000 0x0 0x100>; interrupts = ; + clocks = <&cru PCLK_WDT>; + }; + + pwm0: pwm@ff1b0000 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0000 0x0 0x10>; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + #pwm-cells = <3>; status = "disabled"; }; - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + pwm1: pwm@ff1b0010 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0010 0x0 0x10>; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; - dmac: dmac@ff1f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff1f0000 0x0 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; + pwm2: pwm@ff1b0020 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0020 0x0 0x10>; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@ff1b0030 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0030 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pwmir_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + sustainable-power = <1000>; + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + }; + }; + + }; + + tsadc: tsadc@ff250000 { + compatible = "rockchip,rk3328-tsadc"; + reg = <0x0 0xff250000 0x0 0x100>; + interrupts = ; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <50000>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <100000>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + efuse: efuse@ff260000 { + compatible = "rockchip,rk3328-efuse"; + reg = <0x0 0xff260000 0x0 0x50>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru SCLK_EFUSE>; + clock-names = "pclk_efuse"; + rockchip,efuse-size = <0x20>; + + /* Data cells */ + efuse_id: id@7 { + reg = <0x07 0x10>; + }; + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + logic_leakage: logic-leakage@19 { + reg = <0x19 0x1>; + }; + efuse_cpu_version: cpu-version@1a { + reg = <0x1a 0x1>; + bits = <3 3>; }; }; - saradc: saradc@ff280000 { - compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; + saradc: adc@ff280000 { + compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; reg = <0x0 0xff280000 0x0 0x100>; interrupts = ; #io-channel-cells = <1>; @@ -349,6 +600,169 @@ status = "disabled"; }; + gpu: gpu@ff300000 { + compatible = "rockchip,rk3328-mali", "arm,mali-450"; + reg = <0x0 0xff300000 0x0 0x40000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; + resets = <&cru SRST_GPU_A>; + }; + + h265e_mmu: iommu@ff330200 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff330200 0 0x100>; + interrupts = ; + interrupt-names = "h265e_mmu"; + clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vepu_mmu: iommu@ff340800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff340800 0x0 0x40>; + interrupts = ; + interrupt-names = "vepu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vpu: video-codec@ff350000 { + compatible = "rockchip,rk3328-vpu"; + reg = <0x0 0xff350000 0x0 0x800>; + interrupts = ; + interrupt-names = "vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3328_PD_VPU>; + }; + + vpu_mmu: iommu@ff350800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff350800 0x0 0x40>; + interrupts = ; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3328_PD_VPU>; + }; + + rkvdec_mmu: iommu@ff360480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; + interrupts = ; + interrupt-names = "rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vop: vop@ff370000 { + compatible = "rockchip,rk3328-vop"; + reg = <0x0 0xff370000 0x0 0x3efc>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vop_mmu>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + + vop_mmu: iommu@ff373f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff373f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + hdmi: hdmi@ff3c0000 { + compatible = "rockchip,rk3328-dw-hdmi"; + reg = <0x0 0xff3c0000 0x0 0x20000>; + reg-io-width = <4>; + interrupts = , + ; + clocks = <&cru PCLK_HDMI>, + <&cru SCLK_HDMI_SFC>, + <&cru SCLK_RTC32K>; + clock-names = "iahb", + "isfr", + "cec"; + phys = <&hdmiphy>; + phy-names = "hdmi"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + hdmi_in: port { + hdmi_in_vop: endpoint { + remote-endpoint = <&vop_out_hdmi>; + }; + }; + }; + }; + + codec: codec@ff410000 { + compatible = "rockchip,rk3328-codec"; + reg = <0x0 0xff410000 0x0 0x1000>; + clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; + clock-names = "pclk", "mclk"; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + hdmiphy: phy@ff430000 { + compatible = "rockchip,rk3328-hdmi-phy"; + reg = <0x0 0xff430000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; + clock-names = "sysclk", "refoclk", "refpclk"; + clock-output-names = "hdmi_phy"; + #clock-cells = <0>; + nvmem-cells = <&efuse_cpu_version>; + nvmem-cell-names = "cpu-version"; + #phy-cells = <0>; + status = "disabled"; + }; + cru: clock-controller@ff440000 { compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; reg = <0x0 0xff440000 0x0 0x1000>; @@ -356,6 +770,12 @@ #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = + /* + * CPLL should run at 1200, but that is to high for + * the initial dividers of most of its children. + * We need set cpll child clk div first, + * and then set the cpll frequency. + */ <&cru DCLK_LCDC>, <&cru SCLK_PDM>, <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, <&cru SCLK_UART1>, <&cru SCLK_UART2>, @@ -371,15 +791,7 @@ <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, <&cru HCLK_PERI>, <&cru PCLK_PERI>, - <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, - <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, - <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, - <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, - <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, - <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, - <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; + <&cru SCLK_RTC32K>; assigned-clock-parents = <&cru HDMIPHY>, <&cru PLL_APLL>, <&cru PLL_GPLL>, <&xin24m>, @@ -400,55 +812,85 @@ <150000000>, <75000000>, <75000000>, <150000000>, <75000000>, <75000000>, - <300000000>, <100000000>, - <300000000>, <200000000>, - <400000000>, <500000000>, - <200000000>, <300000000>, - <300000000>, <250000000>, - <200000000>, <100000000>, - <24000000>, <100000000>, - <150000000>, <50000000>, - <32768>, <32768>; + <32768>; }; - sdmmc: rksdmmc@ff500000 { + usb2phy_grf: syscon@ff450000 { + compatible = "rockchip,rk3328-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xff450000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2-phy@100 { + compatible = "rockchip,rk3328-usb2phy"; + reg = <0x100 0x10>; + clocks = <&xin24m>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&u2phy>; + status = "disabled"; + + u2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + }; + + sdmmc: mmc@ff500000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff500000 0x0 0x4000>; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; status = "disabled"; }; - sdio: dwmmc@ff510000 { + sdio: mmc@ff510000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff510000 0x0 0x4000>; - max-frequency = <150000000>; + interrupts = ; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; - interrupts = ; + max-frequency = <150000000>; status = "disabled"; }; - emmc: rksdmmc@ff520000 { + emmc: mmc@ff520000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff520000 0x0 0x4000>; - max-frequency = <150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; status = "disabled"; }; gmac2io: ethernet@ff540000 { compatible = "rockchip,rk3328-gmac"; reg = <0x0 0xff540000 0x0 0x10000>; - rockchip,grf = <&grf>; interrupts = ; interrupt-names = "macirq"; clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, @@ -461,13 +903,56 @@ "pclk_mac"; resets = <&cru SRST_GMAC2IO_A>; reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + snps,txpbl = <0x4>; status = "disabled"; }; + gmac2phy: ethernet@ff550000 { + compatible = "rockchip,rk3328-gmac"; + reg = <0x0 0xff550000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, + <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, + <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, + <&cru SCLK_MAC2PHY_OUT>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_macphy"; + resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; + reset-names = "stmmaceth", "mac-phy"; + phy-mode = "rmii"; + phy-handle = <&phy>; + snps,txpbl = <0x4>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: phy@0 { + compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clocks = <&cru SCLK_MAC2PHY_OUT>; + resets = <&cru SRST_MACPHY>; + pinctrl-names = "default"; + pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; + phy-is-integrated; + }; + }; + }; + usb_host0_ehci: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0x0 0xff5c0000 0x0 0x10000>; interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; status = "disabled"; }; @@ -475,31 +960,38 @@ compatible = "generic-ohci"; reg = <0x0 0xff5d0000 0x0 0x10000>; interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; status = "disabled"; }; + /* + * U-boot Specific Change + * + * The OTG controller must come after the USB host pair for it + * to work. This is likely due to lack of support for the USB + * PHYs. This must be manually changed after each device tree + * sync. There is no clean way to handle this in -u-boot.dtsi + * files. + */ usb20_otg: usb@ff580000 { compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x0 0xff580000 0x0 0x40000>; interrupts = ; - hnp-srp-disable; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; status = "disabled"; }; - sdmmc_ext: rksdmmc@ff5f0000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff5f0000 0x0 0x4000>; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = ; - status = "disabled"; - }; - - gic: interrupt-controller@ffb70000 { + gic: interrupt-controller@ff811000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; @@ -647,654 +1139,576 @@ i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = - <2 24 RK_FUNC_1 &pcfg_pull_none>, - <2 25 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = - <2 4 RK_FUNC_2 &pcfg_pull_none>, - <2 5 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, + <2 RK_PA5 2 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = - <2 13 RK_FUNC_1 &pcfg_pull_none>, - <2 14 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = - <0 5 RK_FUNC_2 &pcfg_pull_none>, - <0 6 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, + <0 RK_PA6 2 &pcfg_pull_none>; }; i2c3_gpio: i2c3-gpio { rockchip,pins = - <0 5 RK_FUNC_GPIO &pcfg_pull_none>, - <0 6 RK_FUNC_GPIO &pcfg_pull_none>; + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; hdmi_i2c { hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, + <0 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + pdm-0 { + pdmm0_clk: pdmm0-clk { + rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; + }; + + pdmm0_fsync: pdmm0-fsync { + rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; + }; + + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; + }; + + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; + }; + + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; + }; + + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; + }; + + pdmm0_clk_sleep: pdmm0-clk-sleep { + rockchip,pins = + <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { + rockchip,pins = + <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { + rockchip,pins = + <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { + rockchip,pins = + <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_fsync_sleep: pdmm0-fsync-sleep { rockchip,pins = - <0 5 RK_FUNC_1 &pcfg_pull_none>, - <0 6 RK_FUNC_1 &pcfg_pull_none>; + <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = - <1 9 RK_FUNC_1 &pcfg_pull_up>, - <1 8 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, + <1 RK_PB0 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = - <1 11 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = - <1 10 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; }; uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = - <1 10 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = - <3 4 RK_FUNC_4 &pcfg_pull_up>, - <3 6 RK_FUNC_4 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, + <3 RK_PA6 4 &pcfg_pull_none>; }; uart1_cts: uart1-cts { - rockchip,pins = - <3 7 RK_FUNC_4 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; }; uart1_rts: uart1-rts { - rockchip,pins = - <3 5 RK_FUNC_4 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; }; uart1_rts_gpio: uart1-rts-gpio { - rockchip,pins = - <3 5 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; uart2-0 { uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - <1 0 RK_FUNC_2 &pcfg_pull_up>, - <1 1 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, + <1 RK_PA1 2 &pcfg_pull_none>; }; }; uart2-1 { uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - <2 0 RK_FUNC_1 &pcfg_pull_up>, - <2 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, + <2 RK_PA1 1 &pcfg_pull_none>; }; }; spi0-0 { spi0m0_clk: spi0m0-clk { - rockchip,pins = - <2 8 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; }; spi0m0_cs0: spi0m0-cs0 { - rockchip,pins = - <2 11 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; }; spi0m0_tx: spi0m0-tx { - rockchip,pins = - <2 9 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; }; spi0m0_rx: spi0m0-rx { - rockchip,pins = - <2 10 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; }; spi0m0_cs1: spi0m0-cs1 { - rockchip,pins = - <2 12 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; }; }; spi0-1 { spi0m1_clk: spi0m1-clk { - rockchip,pins = - <3 23 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; }; spi0m1_cs0: spi0m1-cs0 { - rockchip,pins = - <3 26 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; }; spi0m1_tx: spi0m1-tx { - rockchip,pins = - <3 25 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; }; spi0m1_rx: spi0m1-rx { - rockchip,pins = - <3 24 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; }; spi0m1_cs1: spi0m1-cs1 { - rockchip,pins = - <3 27 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; }; }; spi0-2 { spi0m2_clk: spi0m2-clk { - rockchip,pins = - <3 0 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; }; spi0m2_cs0: spi0m2-cs0 { - rockchip,pins = - <3 8 RK_FUNC_3 &pcfg_pull_up>; + rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; }; spi0m2_tx: spi0m2-tx { - rockchip,pins = - <3 1 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; }; spi0m2_rx: spi0m2-rx { - rockchip,pins = - <3 2 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; }; }; i2s1 { i2s1_mclk: i2s1-mclk { - rockchip,pins = - <2 15 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; }; i2s1_sclk: i2s1-sclk { - rockchip,pins = - <2 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; }; i2s1_lrckrx: i2s1-lrckrx { - rockchip,pins = - <2 16 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; }; i2s1_lrcktx: i2s1-lrcktx { - rockchip,pins = - <2 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; }; i2s1_sdi: i2s1-sdi { - rockchip,pins = - <2 19 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; }; i2s1_sdo: i2s1-sdo { - rockchip,pins = - <2 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; }; i2s1_sdio1: i2s1-sdio1 { - rockchip,pins = - <2 20 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; }; i2s1_sdio2: i2s1-sdio2 { - rockchip,pins = - <2 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; }; i2s1_sdio3: i2s1-sdio3 { - rockchip,pins = - <2 22 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; }; i2s1_sleep: i2s1-sleep { rockchip,pins = - <2 15 RK_FUNC_GPIO &pcfg_input_high>, - <2 16 RK_FUNC_GPIO &pcfg_input_high>, - <2 17 RK_FUNC_GPIO &pcfg_input_high>, - <2 18 RK_FUNC_GPIO &pcfg_input_high>, - <2 19 RK_FUNC_GPIO &pcfg_input_high>, - <2 20 RK_FUNC_GPIO &pcfg_input_high>, - <2 21 RK_FUNC_GPIO &pcfg_input_high>, - <2 22 RK_FUNC_GPIO &pcfg_input_high>, - <2 23 RK_FUNC_GPIO &pcfg_input_high>; + <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; }; }; i2s2-0 { i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = - <1 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; }; i2s2m0_sclk: i2s2m0-sclk { - rockchip,pins = - <1 22 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; }; i2s2m0_lrckrx: i2s2m0-lrckrx { - rockchip,pins = - <1 26 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; }; i2s2m0_lrcktx: i2s2m0-lrcktx { - rockchip,pins = - <1 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; }; i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = - <1 24 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; }; i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = - <1 25 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; }; i2s2m0_sleep: i2s2m0-sleep { rockchip,pins = - <1 21 RK_FUNC_GPIO &pcfg_input_high>, - <1 22 RK_FUNC_GPIO &pcfg_input_high>, - <1 26 RK_FUNC_GPIO &pcfg_input_high>, - <1 23 RK_FUNC_GPIO &pcfg_input_high>, - <1 24 RK_FUNC_GPIO &pcfg_input_high>, - <1 25 RK_FUNC_GPIO &pcfg_input_high>; + <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; }; }; i2s2-1 { i2s2m1_mclk: i2s2m1-mclk { - rockchip,pins = - <1 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; }; i2s2m1_sclk: i2s2m1-sclk { - rockchip,pins = - <3 0 RK_FUNC_6 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; }; i2s2m1_lrckrx: i2sm1-lrckrx { - rockchip,pins = - <3 8 RK_FUNC_6 &pcfg_pull_none>; + rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; }; i2s2m1_lrcktx: i2s2m1-lrcktx { - rockchip,pins = - <3 8 RK_FUNC_4 &pcfg_pull_none>; + rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; }; i2s2m1_sdi: i2s2m1-sdi { - rockchip,pins = - <3 2 RK_FUNC_6 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; }; i2s2m1_sdo: i2s2m1-sdo { - rockchip,pins = - <3 1 RK_FUNC_6 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; }; i2s2m1_sleep: i2s2m1-sleep { rockchip,pins = - <1 21 RK_FUNC_GPIO &pcfg_input_high>, - <3 0 RK_FUNC_GPIO &pcfg_input_high>, - <3 8 RK_FUNC_GPIO &pcfg_input_high>, - <3 2 RK_FUNC_GPIO &pcfg_input_high>, - <3 1 RK_FUNC_GPIO &pcfg_input_high>; + <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; }; }; spdif-0 { spdifm0_tx: spdifm0-tx { - rockchip,pins = - <0 27 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; }; }; spdif-1 { spdifm1_tx: spdifm1-tx { - rockchip,pins = - <2 17 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; }; }; spdif-2 { spdifm2_tx: spdifm2-tx { - rockchip,pins = - <0 2 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; }; }; sdmmc0-0 { sdmmc0m0_pwren: sdmmc0m0-pwren { - rockchip,pins = - <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; }; sdmmc0m0_gpio: sdmmc0m0-gpio { - rockchip,pins = - <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; sdmmc0-1 { sdmmc0m1_pwren: sdmmc0m1-pwren { - rockchip,pins = - <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; + rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; }; sdmmc0m1_gpio: sdmmc0m1-gpio { - rockchip,pins = - <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; sdmmc0 { sdmmc0_clk: sdmmc0-clk { - rockchip,pins = - <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; }; sdmmc0_cmd: sdmmc0-cmd { - rockchip,pins = - <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; }; sdmmc0_dectn: sdmmc0-dectn { - rockchip,pins = - <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; }; sdmmc0_wrprt: sdmmc0-wrprt { - rockchip,pins = - <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; }; sdmmc0_bus1: sdmmc0-bus1 { - rockchip,pins = - <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; }; sdmmc0_bus4: sdmmc0-bus4 { - rockchip,pins = - <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, - <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, - <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, - <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, + <1 RK_PA1 1 &pcfg_pull_up_8ma>, + <1 RK_PA2 1 &pcfg_pull_up_8ma>, + <1 RK_PA3 1 &pcfg_pull_up_8ma>; }; sdmmc0_gpio: sdmmc0-gpio { rockchip,pins = - <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; sdmmc0ext { sdmmc0ext_clk: sdmmc0ext-clk { - rockchip,pins = - <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; + rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; }; sdmmc0ext_cmd: sdmmc0ext-cmd { - rockchip,pins = - <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; + rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; }; sdmmc0ext_wrprt: sdmmc0ext-wrprt { - rockchip,pins = - <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; + rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; }; sdmmc0ext_dectn: sdmmc0ext-dectn { - rockchip,pins = - <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; + rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; }; sdmmc0ext_bus1: sdmmc0ext-bus1 { - rockchip,pins = - <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; + rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; }; sdmmc0ext_bus4: sdmmc0ext-bus4 { rockchip,pins = - <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, - <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, - <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, - <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; + <3 RK_PA4 3 &pcfg_pull_up_4ma>, + <3 RK_PA5 3 &pcfg_pull_up_4ma>, + <3 RK_PA6 3 &pcfg_pull_up_4ma>, + <3 RK_PA7 3 &pcfg_pull_up_4ma>; }; sdmmc0ext_gpio: sdmmc0ext-gpio { rockchip,pins = - <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; sdmmc1 { sdmmc1_clk: sdmmc1-clk { - rockchip,pins = - <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; }; sdmmc1_cmd: sdmmc1-cmd { - rockchip,pins = - <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; }; sdmmc1_pwren: sdmmc1-pwren { - rockchip,pins = - <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; }; sdmmc1_wrprt: sdmmc1-wrprt { - rockchip,pins = - <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; }; sdmmc1_dectn: sdmmc1-dectn { - rockchip,pins = - <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; }; sdmmc1_bus1: sdmmc1-bus1 { - rockchip,pins = - <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; }; sdmmc1_bus4: sdmmc1-bus4 { - rockchip,pins = - <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, - <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, - <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, - <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, + <1 RK_PB7 1 &pcfg_pull_up_8ma>, + <1 RK_PC0 1 &pcfg_pull_up_8ma>, + <1 RK_PC1 1 &pcfg_pull_up_8ma>; }; sdmmc1_gpio: sdmmc1-gpio { rockchip,pins = - <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; }; }; emmc { emmc_clk: emmc-clk { - rockchip,pins = - <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; + rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; }; emmc_cmd: emmc-cmd { - rockchip,pins = - <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; + rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; }; emmc_pwren: emmc-pwren { - rockchip,pins = - <3 22 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; }; emmc_rstnout: emmc-rstnout { - rockchip,pins = - <3 20 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; }; emmc_bus1: emmc-bus1 { - rockchip,pins = - <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; + rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; }; emmc_bus4: emmc-bus4 { rockchip,pins = - <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; + <0 RK_PA7 2 &pcfg_pull_up_12ma>, + <2 RK_PD4 2 &pcfg_pull_up_12ma>, + <2 RK_PD5 2 &pcfg_pull_up_12ma>, + <2 RK_PD6 2 &pcfg_pull_up_12ma>; }; emmc_bus8: emmc-bus8 { rockchip,pins = - <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, - <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, - <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, - <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, - <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; + <0 RK_PA7 2 &pcfg_pull_up_12ma>, + <2 RK_PD4 2 &pcfg_pull_up_12ma>, + <2 RK_PD5 2 &pcfg_pull_up_12ma>, + <2 RK_PD6 2 &pcfg_pull_up_12ma>, + <2 RK_PD7 2 &pcfg_pull_up_12ma>, + <3 RK_PC0 2 &pcfg_pull_up_12ma>, + <3 RK_PC1 2 &pcfg_pull_up_12ma>, + <3 RK_PC2 2 &pcfg_pull_up_12ma>; }; }; pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = - <2 4 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = - <2 5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = - <2 6 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; }; }; pwmir { pwmir_pin: pwmir-pin { - rockchip,pins = - <2 2 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - gmac-0 { - rgmiim0_pins: rgmiim0-pins { - rockchip,pins = - /* mac_txclk */ - <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_rxclk */ - <0 10 RK_FUNC_1 &pcfg_pull_none>, - /* mac_mdio */ - <0 11 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txen */ - <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_clk */ - <0 24 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxdv */ - <0 25 RK_FUNC_1 &pcfg_pull_none>, - /* mac_mdc */ - <0 19 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd1 */ - <0 14 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd0 */ - <0 15 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txd1 */ - <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_rxd3 */ - <0 20 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd2 */ - <0 21 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txd3 */ - <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_txd2 */ - <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; - }; - - rmiim0_pins: rmiim0-pins { - rockchip,pins = - /* mac_mdio */ - <0 11 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txen */ - <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_clk */ - <0 24 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxer */ - <0 13 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxdv */ - <0 25 RK_FUNC_1 &pcfg_pull_none>, - /* mac_mdc */ - <0 19 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd1 */ - <0 14 RK_FUNC_1 &pcfg_pull_none>, - /* mac_rxd0 */ - <0 15 RK_FUNC_1 &pcfg_pull_none>, - /* mac_txd1 */ - <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; + rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; }; }; @@ -1302,157 +1716,128 @@ rgmiim1_pins: rgmiim1-pins { rockchip,pins = /* mac_txclk */ - <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PB4 2 &pcfg_pull_none_8ma>, /* mac_rxclk */ - <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB5 2 &pcfg_pull_none_4ma>, /* mac_mdio */ - <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC3 2 &pcfg_pull_none_4ma>, /* mac_txen */ - <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PD1 2 &pcfg_pull_none_8ma>, /* mac_clk */ - <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC5 2 &pcfg_pull_none_4ma>, /* mac_rxdv */ - <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC6 2 &pcfg_pull_none_4ma>, /* mac_mdc */ - <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC7 2 &pcfg_pull_none_4ma>, /* mac_rxd1 */ - <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB2 2 &pcfg_pull_none_4ma>, /* mac_rxd0 */ - <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB3 2 &pcfg_pull_none_4ma>, /* mac_txd1 */ - <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PB0 2 &pcfg_pull_none_8ma>, /* mac_txd0 */ - <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PB1 2 &pcfg_pull_none_8ma>, /* mac_rxd3 */ - <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB6 2 &pcfg_pull_none_4ma>, /* mac_rxd2 */ - <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB7 2 &pcfg_pull_none_4ma>, /* mac_txd3 */ - <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PC0 2 &pcfg_pull_none_8ma>, /* mac_txd2 */ - <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PC1 2 &pcfg_pull_none_8ma>, /* mac_txclk */ - <0 8 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB0 1 &pcfg_pull_none_8ma>, /* mac_txen */ - <0 12 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none_8ma>, /* mac_clk */ - <0 24 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PD0 1 &pcfg_pull_none_4ma>, /* mac_txd1 */ - <0 16 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC0 1 &pcfg_pull_none_8ma>, /* mac_txd0 */ - <0 17 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC1 1 &pcfg_pull_none_8ma>, /* mac_txd3 */ - <0 23 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC7 1 &pcfg_pull_none_8ma>, /* mac_txd2 */ - <0 22 RK_FUNC_1 &pcfg_pull_none>; + <0 RK_PC6 1 &pcfg_pull_none_8ma>; }; rmiim1_pins: rmiim1-pins { rockchip,pins = /* mac_mdio */ - <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC3 2 &pcfg_pull_none_2ma>, /* mac_txen */ - <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PD1 2 &pcfg_pull_none_12ma>, /* mac_clk */ - <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC5 2 &pcfg_pull_none_2ma>, /* mac_rxer */ - <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PD0 2 &pcfg_pull_none_2ma>, /* mac_rxdv */ - <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC6 2 &pcfg_pull_none_2ma>, /* mac_mdc */ - <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PC7 2 &pcfg_pull_none_2ma>, /* mac_rxd1 */ - <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB2 2 &pcfg_pull_none_2ma>, /* mac_rxd0 */ - <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, + <1 RK_PB3 2 &pcfg_pull_none_2ma>, /* mac_txd1 */ - <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PB0 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ - <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, + <1 RK_PB1 2 &pcfg_pull_none_12ma>, /* mac_mdio */ - <0 11 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB3 1 &pcfg_pull_none>, /* mac_txen */ - <0 12 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none>, /* mac_clk */ - <0 24 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PD0 1 &pcfg_pull_none>, /* mac_mdc */ - <0 19 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC3 1 &pcfg_pull_none>, /* mac_txd1 */ - <0 16 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC0 1 &pcfg_pull_none>, /* mac_txd0 */ - <0 17 RK_FUNC_1 &pcfg_pull_none>; + <0 RK_PC1 1 &pcfg_pull_none>; }; }; gmac2phy { - fephyled_speed100: fephyled-speed100 { - rockchip,pins = - <0 31 RK_FUNC_1 &pcfg_pull_none>; - }; - fephyled_speed10: fephyled-speed10 { - rockchip,pins = - <0 30 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; }; fephyled_duplex: fephyled-duplex { - rockchip,pins = - <0 30 RK_FUNC_2 &pcfg_pull_none>; - }; - - fephyled_rxm0: fephyled-rxm0 { - rockchip,pins = - <0 29 RK_FUNC_1 &pcfg_pull_none>; - }; - - fephyled_txm0: fephyled-txm0 { - rockchip,pins = - <0 29 RK_FUNC_2 &pcfg_pull_none>; - }; - - fephyled_linkm0: fephyled-linkm0 { - rockchip,pins = - <0 28 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; }; fephyled_rxm1: fephyled-rxm1 { - rockchip,pins = - <2 25 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; }; fephyled_txm1: fephyled-txm1 { - rockchip,pins = - <2 25 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; }; fephyled_linkm1: fephyled-linkm1 { - rockchip,pins = - <2 24 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; }; }; tsadc_pin { tsadc_int: tsadc-int { - rockchip,pins = - <2 13 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; }; tsadc_gpio: tsadc-gpio { - rockchip,pins = - <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; hdmi_pin { hdmi_cec: hdmi-cec { - rockchip,pins = - <0 3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; }; hdmi_hpd: hdmi-hpd { - rockchip,pins = - <0 4 RK_FUNC_1 &pcfg_pull_down>; + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; }; }; @@ -1460,29 +1845,29 @@ dvp_d2d9_m0:dvp-d2d9-m0 { rockchip,pins = /* cif_d0 */ - <3 4 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA4 2 &pcfg_pull_none>, /* cif_d1 */ - <3 5 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA5 2 &pcfg_pull_none>, /* cif_d2 */ - <3 6 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA6 2 &pcfg_pull_none>, /* cif_d3 */ - <3 7 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA7 2 &pcfg_pull_none>, /* cif_d4 */ - <3 8 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PB0 2 &pcfg_pull_none>, /* cif_d5m0 */ - <3 9 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PB1 2 &pcfg_pull_none>, /* cif_d6m0 */ - <3 10 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PB2 2 &pcfg_pull_none>, /* cif_d7m0 */ - <3 11 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PB3 2 &pcfg_pull_none>, /* cif_href */ - <3 1 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA1 2 &pcfg_pull_none>, /* cif_vsync */ - <3 0 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA0 2 &pcfg_pull_none>, /* cif_clkoutm0 */ - <3 3 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA3 2 &pcfg_pull_none>, /* cif_clkin */ - <3 2 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PA2 2 &pcfg_pull_none>; }; }; @@ -1490,29 +1875,29 @@ dvp_d2d9_m1:dvp-d2d9-m1 { rockchip,pins = /* cif_d0 */ - <3 4 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA4 2 &pcfg_pull_none>, /* cif_d1 */ - <3 5 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA5 2 &pcfg_pull_none>, /* cif_d2 */ - <3 6 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA6 2 &pcfg_pull_none>, /* cif_d3 */ - <3 7 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA7 2 &pcfg_pull_none>, /* cif_d4 */ - <3 8 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PB0 2 &pcfg_pull_none>, /* cif_d5m1 */ - <2 16 RK_FUNC_4 &pcfg_pull_none>, + <2 RK_PC0 4 &pcfg_pull_none>, /* cif_d6m1 */ - <2 17 RK_FUNC_4 &pcfg_pull_none>, + <2 RK_PC1 4 &pcfg_pull_none>, /* cif_d7m1 */ - <2 18 RK_FUNC_4 &pcfg_pull_none>, + <2 RK_PC2 4 &pcfg_pull_none>, /* cif_href */ - <3 1 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA1 2 &pcfg_pull_none>, /* cif_vsync */ - <3 0 RK_FUNC_2 &pcfg_pull_none>, + <3 RK_PA0 2 &pcfg_pull_none>, /* cif_clkoutm1 */ - <2 15 RK_FUNC_4 &pcfg_pull_none>, + <2 RK_PB7 4 &pcfg_pull_none>, /* cif_clkin */ - <3 2 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PA2 2 &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index ccb33d34d1..e5659d7999 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -11,3 +11,15 @@ u-boot,spl-boot-order = &sdhci, &sdmmc; }; }; + +&rng { + status = "okay"; +}; + +&i2c0 { + u-boot,dm-pre-reloc; +}; + +&rk808 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 4129e902a8..694b0d08d6 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -1,86 +1,18 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd */ /dts-v1/; #include -#include #include "rk3399.dtsi" / { model = "Rockchip RK3399 Evaluation Board"; - compatible = "rockchip,rk3399-evb", "rockchip,rk3399", - "google,rk3399evb-rev2"; - - chosen { - stdout-path = &uart2; - }; - - vdd_center: vdd-center { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 25000 1>; - regulator-name = "vdd_center"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-init-microvolt = <950000>; - regulator-always-on; - regulator-boot-on; - status = "okay"; - }; - - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vccsys"; - regulator-boot-on; - regulator-always-on; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_host: vcc5v0-host-en { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; - }; - - vcc5v0_typec0: vcc5v0-typec0-en { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_typec0"; - gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - vcc5v0_typec1: vcc5v0-typec1-en { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_typec1"; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; + compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; backlight: backlight { compatible = "pwm-backlight"; - power-supply = <&vccsys>; - enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 @@ -116,18 +48,98 @@ 248 249 250 251 252 253 254 255>; default-brightness-level = <200>; pwms = <&pwm0 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - pwm-delay-us = <10000>; - status = "disabled"; }; - panel:panel { - compatible = "simple-panel"; - power-supply = <&vcc33_lcd>; + edp_panel: edp-panel { + compatible ="lg,lp079qx1-sp0v"; backlight = <&backlight>; - /*enable-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;*/ - status = "disabled"; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + power-supply = <&vcc3v3_s0>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vdd_center: vdd-center { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 25000 0>; + regulator-name = "vdd_center"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + status = "okay"; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; }; }; @@ -135,24 +147,253 @@ status = "okay"; }; -&pwm0 { +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; status = "okay"; }; -&pwm2 { +&i2c0 { status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-name = "vcc3v0_tp"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; }; -&pwm3 { +&pwm0 { status = "okay"; }; -&saradc { +&pwm2 { status = "okay"; }; -&sdmmc { - bus-width = <4>; +&pwm3 { status = "okay"; }; @@ -164,117 +405,76 @@ status = "okay"; }; -&uart2 { - status = "okay"; +&pcie_phy { + status = "disabled"; }; -&usb_host0_ehci { - status = "okay"; +&pcie0 { + ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "disabled"; }; -&usb_host0_ohci { +&u2phy0 { status = "okay"; }; -&usbdrd3_0 { - vbus-supply = <&vcc5v0_typec0>; +&u2phy0_host { + phy-supply = <&vcc5v0_host>; status = "okay"; }; -&usb_host1_ehci { +&u2phy1 { status = "okay"; }; -&usb_host1_ohci { +&u2phy1_host { + phy-supply = <&vcc5v0_host>; status = "okay"; }; -&usbdrd3_1 { - vbus-supply = <&vcc5v0_typec1>; +&uart2 { status = "okay"; }; -&i2c0 { +&usb_host0_ehci { status = "okay"; - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <100>; - u-boot,dm-pre-reloc; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - clock-output-names = "xin32k", "wifibt_32kin"; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - reg = <0x1b>; - rockchip,system-power-controller; - #clock-cells = <1>; - u-boot,dm-pre-reloc; - status = "okay"; +}; - vcc12-supply = <&vcc3v3_sys>; +&usb_host0_ohci { + status = "okay"; +}; - regulators { - vcc33_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_lcd"; - }; - }; - }; +&usb_host1_ehci { + status = "okay"; }; -&mipi_dsi { - status = "disabled"; - rockchip,panel = <&panel>; - display-timings { - timing0 { - bits-per-pixel = <24>; - clock-frequency = <160000000>; - hfront-porch = <120>; - hsync-len = <20>; - hback-porch = <21>; - hactive = <1200>; - vfront-porch = <21>; - vsync-len = <3>; - vback-porch = <18>; - vactive = <1920>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; +&usb_host1_ohci { + status = "okay"; }; &pinctrl { pmic { pmic_int_l: pmic-int-l { rockchip,pins = - <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; }; + }; - pmic_dvs2: pmic-dvs2 { + usb2 { + vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = - <1 18 RK_FUNC_GPIO &pcfg_pull_down>; + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; -&gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x28>; - rx_delay = <0x11>; +&vopb { + status = "okay"; +}; + +&vopb_mmu { status = "okay"; }; diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts index 6b059bd7a0..ebe2ee77ba 100644 --- a/arch/arm/dts/rk3399-ficus.dts +++ b/arch/arm/dts/rk3399-ficus.dts @@ -146,6 +146,12 @@ }; }; +&spi1 { + /* On both Low speed and High speed expansion */ + cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>; + status = "okay"; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index 89c67fd24c..d63faf38cc 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -1,19 +1,20 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. */ /dts-v1/; +#include #include -#include #include "rk3399.dtsi" +#include "rk3399-opp.dtsi" / { model = "Firefly-RK3399 Board"; compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; chosen { - stdout-path = &uart2; + stdout-path = "serial2:1500000n8"; }; backlight: backlight { @@ -63,6 +64,48 @@ #clock-cells = <0>; }; + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; + + work-led { + label = "work"; + default-state = "on"; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + }; + + diy-led { + label = "diy"; + default-state = "off"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + }; + }; + rt5640-sound { compatible = "simple-audio-card"; simple-audio-card,name = "rockchip,rt5640-codec"; @@ -102,15 +145,27 @@ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&pcie_drv>; + pinctrl-0 = <&pcie_pwr_en>; regulator-name = "vcc3v3_pcie"; regulator-always-on; regulator-boot-on; + vin-supply = <&dc_12v>; }; vcc3v3_sys: vcc3v3-sys { @@ -120,32 +175,29 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; }; + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; + pinctrl-0 = <&vcc5v0_host_en>; regulator-name = "vcc5v0_host"; regulator-always-on; + vin-supply = <&vcc_sys>; }; - vcc5v0_sys: vcc5v0-sys { + vcc_sys: vcc-sys { compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; + regulator-name = "vcc_sys"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; + vin-supply = <&dc_12v>; }; vdd_log: vdd-log { @@ -156,16 +208,7 @@ regulator-boot-on; regulator-min-microvolt = <430000>; regulator-max-microvolt = <1400000>; - regulator-init-microvolt = <950000>; - }; - - vccadc_ref: vccadc-ref { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_sys>; }; }; @@ -201,15 +244,22 @@ assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clock-parents = <&clkin_gmac>; clock_in_out = "input"; - phy-supply = <&vcc_phy>; + phy-supply = <&vcc_lan>; phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x33>; - rx_delay = <0x45>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; status = "okay"; }; @@ -231,16 +281,16 @@ rockchip,system-power-controller; wakeup-source; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; vcc12-supply = <&vcc3v3_sys>; vddio-supply = <&vcc1v8_pmu>; @@ -301,12 +351,12 @@ }; }; - vcc3v0_tp: LDO_REG2 { - regulator-name = "vcc3v0_tp"; + vcc2v8_dvp: LDO_REG2 { + regulator-name = "vcc2v8_dvp"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; regulator-state-mem { regulator-off-in-suspend; }; @@ -324,8 +374,8 @@ }; }; - vcc_sd: LDO_REG4 { - regulator-name = "vcc_sd"; + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; @@ -382,7 +432,7 @@ }; }; - vcc3v3_s3: SWITCH_REG1 { + vcc3v3_s3: vcc_lan: SWITCH_REG1 { regulator-name = "vcc3v3_s3"; regulator-always-on; regulator-boot-on; @@ -412,7 +462,7 @@ regulator-ramp-delay = <1000>; regulator-always-on; regulator-boot-on; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc_sys>; regulator-state-mem { regulator-off-in-suspend; @@ -429,7 +479,7 @@ regulator-ramp-delay = <1000>; regulator-always-on; regulator-boot-on; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc_sys>; regulator-state-mem { regulator-off-in-suspend; @@ -476,19 +526,16 @@ &i2s0 { rockchip,playback-channels = <8>; rockchip,capture-channels = <8>; - #sound-dai-cells = <0>; status = "okay"; }; &i2s1 { rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; status = "okay"; }; &i2s2 { - #sound-dai-cells = <0>; status = "okay"; }; @@ -497,7 +544,7 @@ bt656-supply = <&vcc1v8_dvp>; audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sd>; + sdmmc-supply = <&vcc_sdio>; gpio1830-supply = <&vcc_3v0>; }; @@ -509,7 +556,7 @@ ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; num-lanes = <4>; pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn>; + pinctrl-0 = <&pcie_clkreqn_cpm>; status = "okay"; }; @@ -532,7 +579,7 @@ }; pcie { - pcie_drv: pcie-drv { + pcie_pwr_en: pcie-pwr-en { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -570,10 +617,26 @@ }; usb2 { - host_vbus_drv: host-vbus-drv { + vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_gpio: work_led-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_gpio: diy_led-gpio { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm0 { @@ -585,24 +648,70 @@ }; &saradc { - vref-supply = <&vccadc_ref>; + vref-supply = <&vcca1v8_s3>; status = "okay"; }; +&sdio0 { + /* WiFi & BT combo module Ampak AP6356S */ + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + + /* Power supply */ + vqmmc-supply = &vcc1v8_s3; /* IO line */ + vmmc-supply = &vcc_sdio; /* card's power */ + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + brcm,drive-strength = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + &sdmmc { bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; status = "okay"; }; &sdhci { bus-width = <8>; - keep-power-in-suspend; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; non-removable; status = "okay"; }; +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + &tsadc { /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-mode = <1>; @@ -662,3 +771,37 @@ &usb_host1_ohci { status = "okay"; }; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts index 1ee0dc0d9f..e6c1c94c8d 100644 --- a/arch/arm/dts/rk3399-gru-bob.dts +++ b/arch/arm/dts/rk3399-gru-bob.dts @@ -18,11 +18,11 @@ "google,bob", "google,gru", "rockchip,rk3399"; edp_panel: edp-panel { - compatible = "boe,nv101wxmn51", "simple-panel"; + compatible = "boe,nv101wxmn51"; backlight = <&backlight>; power-supply = <&pp3300_disp>; - ports { + port { panel_in_edp: endpoint { remote-endpoint = <&edp_out_panel>; }; @@ -68,12 +68,22 @@ &spi0 { status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&h1_int_od_l>; + spi-max-frequency = <800000>; + }; }; &pinctrl { tpm { h1_int_od_l: h1-int-od-l { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/dts/rk3399-gru-chromebook.dtsi b/arch/arm/dts/rk3399-gru-chromebook.dtsi index c6495adcca..1384dabbdf 100644 --- a/arch/arm/dts/rk3399-gru-chromebook.dtsi +++ b/arch/arm/dts/rk3399-gru-chromebook.dtsi @@ -194,20 +194,25 @@ backlight: backlight { compatible = "pwm-backlight"; - brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - 45 46 47 48 49 50 51 52 53 54 55 56 57 58 - 59 60 61 62 63 64 65 66 67 68 69 70 71 72 - 73 74 75 76 77 78 79 80 81 82 83 84 85 86 - 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; - default-brightness-level = <51>; enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; power-supply = <&pp3300_disp>; pinctrl-names = "default"; pinctrl-0 = <&bl_en>; pwm-delay-us = <10000>; }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>; + + wake_on_bt: wake-on-bt { + label = "Wake-on-Bluetooth"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; }; &ppvar_bigcpu { @@ -232,7 +237,6 @@ &edp { status = "okay"; - rockchip,panel = <&edp_panel>; ports { edp_out: port@1 { reg = <1>; @@ -287,11 +291,9 @@ ap_i2c_tp: &i2c5 { #pwm-cells = <1>; }; - usbc_extcon1: extcon@1 { + usbc_extcon1: extcon1 { compatible = "google,extcon-usbc-cros-ec"; google,usb-port-id = <1>; - - #extcon-cells = <0>; }; }; @@ -361,27 +363,27 @@ ap_i2c_tp: &i2c5 { &pinctrl { discrete-regulators { pp1500_en: pp1500-en { - rockchip,pins = ; }; pp1800_audio_en: pp1800-audio-en { - rockchip,pins = ; }; pp3000_en: pp3000-en { - rockchip,pins = ; }; pp3300_disp_en: pp3300-disp-en { - rockchip,pins = ; }; wlan_module_pd_l: wlan-module-pd-l { - rockchip,pins = ; }; }; @@ -389,10 +391,10 @@ ap_i2c_tp: &i2c5 { &wifi { wifi_perst_l: wifi-perst-l { - rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; }; wlan_host_wake_l: wlan-host-wake-l { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/dts/rk3399-gru-kevin.dts b/arch/arm/dts/rk3399-gru-kevin.dts index 2cc7c47d6a..2bbef9fcbe 100644 --- a/arch/arm/dts/rk3399-gru-kevin.dts +++ b/arch/arm/dts/rk3399-gru-kevin.dts @@ -39,11 +39,25 @@ }; edp_panel: edp-panel { - compatible = "sharp,lq123p1jx31", "simple-panel"; + compatible = "sharp,lq123p1jx31"; backlight = <&backlight>; power-supply = <&pp3300_disp>; - ports { + panel-timing { + clock-frequency = <266666667>; + hactive = <2400>; + hfront-porch = <48>; + hback-porch = <84>; + hsync-len = <32>; + hsync-active = <0>; + vactive = <1600>; + vfront-porch = <3>; + vback-porch = <120>; + vsync-len = <10>; + vsync-active = <0>; + }; + + port { panel_in_edp: endpoint { remote-endpoint = <&edp_out_panel>; }; @@ -118,13 +132,17 @@ map0 { trip = <&ppvar_bigcpu_alert>; cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <4096>; }; map1 { trip = <&ppvar_bigcpu_alert>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <1024>; }; }; @@ -286,24 +304,24 @@ ap_i2c_dig: &i2c2 { digitizer { /* Has external pullup */ cpu1_dig_irq_l: cpu1-dig-irq-l { - rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; /* Has external pullup */ cpu1_dig_pdct_l: cpu1-dig-pdct-l { - rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; discrete-regulators { cpu3_pen_pwr_en: cpu3-pen-pwr-en { - rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pen { cpu1_pen_eject: cpu1-pen-eject { - rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index 0e2e047180..7ac88392f2 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -11,13 +11,7 @@ / { chosen { - u-boot,dm-pre-reloc; stdout-path = "serial2:115200n8"; - u-boot,spl-boot-order = &spi_flash; - }; - - config { - u-boot,spl-payload-offset = <0x40000>; }; /* @@ -268,17 +262,11 @@ pp5000_usb_a_vbus: pp5000 { }; - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>; - - wake_on_bt: wake-on-bt { - label = "Wake-on-Bluetooth"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; + ap_rtc_clk: ap-rtc-clk { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; }; max98357a: max98357a { @@ -549,8 +537,7 @@ ap_i2c_audio: &i2c8 { pinctrl-names = "default", "sleep"; pinctrl-1 = <&spi1_sleep>; - spi_flash: spiflash@0 { - u-boot,dm-pre-reloc; + spiflash@0 { compatible = "jedec,spi-nor"; reg = <0>; @@ -565,16 +552,12 @@ ap_i2c_audio: &i2c8 { &spi5 { status = "okay"; - spi-activate-delay = <100>; - spi-max-frequency = <3000000>; - spi-deactivate-delay = <200>; cros_ec: ec@0 { compatible = "google,cros-ec-spi"; reg = <0>; interrupt-parent = <&gpio0>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - ec-interrupt = <&gpio0 1 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; @@ -586,11 +569,9 @@ ap_i2c_audio: &i2c8 { #size-cells = <0>; }; - usbc_extcon0: extcon@0 { + usbc_extcon0: extcon0 { compatible = "google,extcon-usbc-cros-ec"; google,usb-port-id = <0>; - - #extcon-cells = <0>; }; }; }; @@ -692,29 +673,29 @@ ap_i2c_audio: &i2c8 { backlight-enable { bl_en: bl-en { - rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; cros-ec { ec_ap_int_l: ec-ap-int-l { - rockchip,pins = ; + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; }; }; discrete-regulators { sd_io_pwr_en: sd-io-pwr-en { - rockchip,pins = ; }; sd_pwr_1800_sel: sd-pwr-1800-sel { - rockchip,pins = ; }; sd_slot_pwr_en: sd-slot-pwr-en { - rockchip,pins = ; }; }; @@ -722,17 +703,17 @@ ap_i2c_audio: &i2c8 { codec { /* Has external pullup */ headset_int_l: headset-int-l { - rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; }; mic_int: mic-int { - rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; }; }; max98357a { sdmode_en: sdmode-en { - rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; }; }; @@ -743,7 +724,7 @@ ap_i2c_audio: &i2c8 { * to hack this as gpio, so the EP could be able to * de-assert it along and make ClockPM(CPM) work. */ - rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -754,20 +735,20 @@ ap_i2c_audio: &i2c8 { */ sdmmc_bus4: sdmmc-bus4 { rockchip,pins = - <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>, - <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>, - <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>, - <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>; + <4 RK_PB0 1 &pcfg_pull_none_8ma>, + <4 RK_PB1 1 &pcfg_pull_none_8ma>, + <4 RK_PB2 1 &pcfg_pull_none_8ma>, + <4 RK_PB3 1 &pcfg_pull_none_8ma>; }; sdmmc_clk: sdmmc-clk { rockchip,pins = - <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>; + <4 RK_PB4 1 &pcfg_pull_none_8ma>; }; sdmmc_cmd: sdmmc-cmd { rockchip,pins = - <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>; + <4 RK_PB5 1 &pcfg_pull_none_8ma>; }; /* @@ -781,12 +762,12 @@ ap_i2c_audio: &i2c8 { */ sdmmc_cd: sdmmc-cd { rockchip,pins = - <0 7 RK_FUNC_1 &pcfg_pull_none>; + <0 RK_PA7 1 &pcfg_pull_none>; }; /* This is where we actually hook up CD; has external pull */ sdmmc_cd_gpio: sdmmc-cd-gpio { - rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -796,47 +777,47 @@ ap_i2c_audio: &i2c8 { * Pull down SPI1 CLK/CS/RX/TX during suspend, to * prevent leakage. */ - rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>, - <1 10 RK_FUNC_GPIO &pcfg_pull_down>, - <1 7 RK_FUNC_GPIO &pcfg_pull_down>, - <1 8 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; }; }; touchscreen { touch_int_l: touch-int-l { - rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; }; touch_reset_l: touch-reset-l { - rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; trackpad { ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { - rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>; + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; }; trackpad_int_l: trackpad-int-l { - rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; wifi: wifi { wlan_module_reset_l: wlan-module-reset-l { - rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; bt_host_wake_l: bt-host-wake-l { /* Kevin has an external pull up, but Gru does not */ - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; write-protect { ap_fw_wp: ap-fw-wp { - rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/arch/arm/dts/rk3399-khadas-edge.dtsi b/arch/arm/dts/rk3399-khadas-edge.dtsi index 4944d78a0a..e87a044774 100644 --- a/arch/arm/dts/rk3399-khadas-edge.dtsi +++ b/arch/arm/dts/rk3399-khadas-edge.dtsi @@ -654,9 +654,12 @@ sd-uhs-sdr104; vqmmc-supply = <&vcc1v8_s3>; vmmc-supply = <&vccio_sd>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; brcmf: wifi@1 { + reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; interrupts = ; diff --git a/arch/arm/dts/rk3399-leez-p710.dts b/arch/arm/dts/rk3399-leez-p710.dts index 32baa57b94..73be38a537 100644 --- a/arch/arm/dts/rk3399-leez-p710.dts +++ b/arch/arm/dts/rk3399-leez-p710.dts @@ -42,14 +42,14 @@ regulator-max-microvolt = <5000000>; }; - vcc5v0_sys: vcc5v0-sys { + vcc3v3_lan: vcc3v3-lan { compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; + regulator-name = "vcc3v3_lan"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc5v_adp>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vim-supply = <&vcc3v3_sys>; }; vcc3v3_sys: vcc3v3-sys { @@ -83,14 +83,14 @@ vin-supply = <&vcc5v0_sys>; }; - vcc3v3_lan: vcc3v3-lan { + vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lan"; + regulator-name = "vcc5v0_sys"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vim-supply = <&vcc3v3_sys>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc5v_adp>; }; vdd_log: vdd-log { @@ -510,6 +510,14 @@ }; }; +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; @@ -522,14 +530,6 @@ status = "okay"; }; -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - &tcphy0 { status = "okay"; }; diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts index 84433cf02b..e0d75617bb 100644 --- a/arch/arm/dts/rk3399-nanopc-t4.dts +++ b/arch/arm/dts/rk3399-nanopc-t4.dts @@ -52,13 +52,58 @@ pinctrl-names = "default"; pinctrl-0 = <&ir_rx>; }; + + fan: pwm-fan { + compatible = "pwm-fan"; + /* + * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels + * work out to 0, ~1200, ~3000, and 5000RPM respectively. + */ + cooling-levels = <0 12 18 255>; + #cooling-cells = <2>; + fan-supply = <&vcc12v0_sys>; + pwms = <&pwm1 0 50000 0>; + }; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&pcie0 { + num-lanes = <4>; + vpcie3v3-supply = <&vcc3v3_sys>; }; &pinctrl { ir { ir_rx: ir-rx { /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */ - rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi new file mode 100644 index 0000000000..a2f9786473 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + * Copyright (C) 2020 Deepak Das + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-ddr3-1866.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts new file mode 100644 index 0000000000..60358ab8c7 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPi M4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi M4"; + compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2: vcc5v0-usb2 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb2"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb2>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi index d325e11728..c88018a0ef 100644 --- a/arch/arm/dts/rk3399-nanopi4.dtsi +++ b/arch/arm/dts/rk3399-nanopi4.dtsi @@ -48,7 +48,7 @@ }; /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + vcc1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; regulator-always-on; regulator-boot-on; @@ -71,6 +71,27 @@ vin-supply = <&vcc3v3_sys>; }; + /* + * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only + * drives the enable pin, but we can't quite model that. + */ + vcca0v9_s3: vcca0v9-s3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcca0v9_s3"; + vin-supply = <&vcc1v8_s3>; + }; + + /* As above, actually supplied by vcc3v3_sys */ + vcca1v8_s3: vcca1v8-s3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_s3"; + vin-supply = <&vcc1v8_s3>; + }; + vbus_typec: vbus-typec { compatible = "regulator-fixed"; regulator-min-microvolt = <5000000>; @@ -148,15 +169,28 @@ assigned-clocks = <&cru SCLK_RMII_SRC>; clock_in_out = "input"; pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; + pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; + phy-handle = <&rtl8211e>; phy-mode = "rgmii"; phy-supply = <&vcc3v3_s3>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; tx_delay = <0x28>; rx_delay = <0x11>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; + }; }; &gpu { @@ -171,6 +205,10 @@ status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <160>; @@ -446,6 +484,10 @@ status = "okay"; }; +&i2s2 { + status = "okay"; +}; + &io_domains { bt656-supply = <&vcc_1v8>; audio-supply = <&vcca1v8_codec>; @@ -464,7 +506,9 @@ &pcie0 { ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; max-link-speed = <2>; - num-lanes = <4>; + num-lanes = <2>; + vpcie0v9-supply = <&vcca0v9_s3>; + vpcie1v8-supply = <&vcca1v8_s3>; status = "okay"; }; @@ -481,6 +525,16 @@ }; }; + phy { + phy_intb: phy-intb { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rstb: phy-rstb { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { cpu_b_sleep: cpu-b-sleep { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts index cf37b96a6b..f9f7246d4d 100644 --- a/arch/arm/dts/rk3399-orangepi.dts +++ b/arch/arm/dts/rk3399-orangepi.dts @@ -136,13 +136,13 @@ vin-supply = <&vcc_sys>; }; - vcc5v0_typec0: vcc5v0-typec0-regulator { + vbus_typec: vbus-typec-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec0_en>; - regulator-name = "vcc5v0_typec0"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vbus_typec"; vin-supply = <&vcc_sys>; }; @@ -202,14 +202,27 @@ clock_in_out = "input"; phy-supply = <&vcc3v3_s3>; phy-mode = "rgmii"; + phy-handle = <&rtl8211e>; pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; + pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; tx_delay = <0x28>; rx_delay = <0x11>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; + }; }; &gpu { @@ -419,6 +432,8 @@ compatible = "silergy,syr827"; reg = <0x40>; fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -436,6 +451,8 @@ compatible = "silergy,syr828"; reg = <0x41>; fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; regulator-name = "vdd_gpu"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; @@ -472,6 +489,7 @@ compatible = "asahi-kasei,ak09911"; reg = <0x0c>; vdd-supply = <&vcc3v3_s3>; + vid-supply = <&vcc3v3_s3>; }; mpu6500@68 { @@ -504,6 +522,16 @@ pinctrl-0 = <&light_int_l>; vdd-supply = <&vcc3v3_s3>; }; + + fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&chg_cc_int_l>; + vbus-supply = <&vbus_typec>; + }; }; &io_domains { @@ -526,7 +554,25 @@ }; }; + phy { + phy_intb: phy-intb { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rstb: phy-rstb { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; @@ -536,7 +582,7 @@ sd { sdmmc0_pwr_h: sdmmc0-pwr-h { rockchip,pins = - ; + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -546,7 +592,7 @@ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; - vcc5v0_typec0_en: vcc5v0-typec0-en { + vcc5v0_typec_en: vcc5v0-typec-en { rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; @@ -595,6 +641,12 @@ rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + fusb302 { + chg_cc_int_l: chg-cc-int-l { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; }; &pwm0 { @@ -631,9 +683,12 @@ pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; brcmf: wifi@1 { + reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; interrupts = ; @@ -676,7 +731,7 @@ status = "okay"; u2phy0_otg: otg-port { - phy-supply = <&vcc5v0_typec0>; + phy-supply = <&vbus_typec>; status = "okay"; }; @@ -707,12 +762,14 @@ bluetooth { compatible = "brcm,bcm43438-bt"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; }; }; diff --git a/arch/arm/dts/rk3399-puma-u-boot.dtsi b/arch/arm/dts/rk3399-puma-u-boot.dtsi index 52f62b5d39..3ad1139833 100644 --- a/arch/arm/dts/rk3399-puma-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-u-boot.dtsi @@ -13,7 +13,7 @@ chosen { stdout-path = "serial0:115200n8"; u-boot,spl-boot-order = \ - "same-as-spl", &spiflash, &sdhci, &sdmmc; + "same-as-spl", &norflash, &sdhci, &sdmmc; }; aliases { @@ -21,4 +21,33 @@ spi1 = &spi5; }; + /* + * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module + * eMMC and SPI flash powered-down initially (in fact it keeps the + * reset signal asserted). Even though it is an enable signal, we + * model this as a regulator. + */ + bios_enable: bios_enable { + compatible = "regulator-fixed"; + u-boot,dm-pre-reloc; + regulator-name = "bios_enable"; + enable-active-high; + gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&norflash { + u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 558b6337df..07694b196f 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -1,30 +1,74 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH */ #include #include "rk3399.dtsi" +#include "rk3399-opp.dtsi" / { - model = "Theobroma Systems RK3399-Q7 SoM"; - compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399"; - leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_puma>; + pinctrl-0 = <&led_pin_module>; - module_led { + module-led { label = "module_led"; gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; + panic-indicator; }; + }; - sd_card_led { - label = "sd_card_led"; - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; + /* + * Overwrite the opp-table for CPUB as this board uses a different + * regulator (FAN53555) that only allows 10mV steps and therefore + * can't reach the operation point target voltages from rk3399-opp.dtsi + */ + /delete-node/ opp-table1; + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <830000>; + opp-suspend; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <880000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <950000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1030000>; + }; + opp06 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1100000>; + }; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1200000>; + }; + opp08 { + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1230000>; + turbo-mode; }; }; @@ -35,79 +79,14 @@ #clock-cells = <0>; }; - dw_hdmi_audio: dw-hdmi-audio { - status = "enabled"; - compatible = "rockchip,dw-hdmi-audio"; - #sound-dai-cells = <0>; - }; - - hdmi_codec: hdmi-codec { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "HDMI-CODEC"; - - simple-audio-card,cpu { - sound-dai = <&i2s2>; - }; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - }; - - hdmi_sound: hdmi-sound { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,hdmi"; - - simple-audio-card,cpu { - sound-dai = <&i2s2>; - }; - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - }; - - usbhub_enable: usbhub_enable { - compatible = "regulator-fixed"; - regulator-name = "usbhub_enable"; - enable-active-low; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - /* - * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module - * eMMC and SPI flash powered-down initially (in fact it keeps the - * reset signal asserted). Even though it is an enable signal, we - * model this as a regulator. - */ - bios_enable: bios_enable { - compatible = "regulator-fixed"; - u-boot,dm-pre-reloc; - regulator-name = "bios_enable"; - enable-active-high; - gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vccadc_ref: vccadc-ref { + vcc1v2_phy: vcc1v2-phy { compatible = "regulator-fixed"; - regulator-name = "vcc1v8_sys"; + regulator-name = "vcc1v2_phy"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; }; vcc3v3_sys: vcc3v3-sys { @@ -117,16 +96,18 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; }; - vcc5v0_otg: vcc5v0-otg-regulator { + vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + enable-active-low; pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc5v0_otg"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; regulator-always-on; + vin-supply = <&vcc5v0_sys>; }; vcc5v0_sys: vcc5v0-sys { @@ -137,48 +118,55 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; +}; - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <950000>; - }; +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; }; &emmc_phy { status = "okay"; + drive-impedance-ohm = <33>; }; &gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <2 10000 50000>; assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc1v2_phy>; + phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; tx_delay = <0x10>; rx_delay = <0x10>; status = "okay"; }; -&hdmi { - #sound-dai-cells = <0>; +&gpu { + mali-supply = <&vdd_gpu>; status = "okay"; }; @@ -188,37 +176,17 @@ i2c-scl-falling-time-ns = <4>; clock-frequency = <400000>; - vdd_gpu: vdd_gpu { - status = "okay"; - compatible = "fcs,fan53555"; - reg = <0x60>; - vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "fan53555-reg"; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1230000>; - regulator-ramp-delay = <1000>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-initial-state = <3>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - rk808: pmic@1b { compatible = "rockchip,rk808"; reg = <0x1b>; interrupt-parent = <&gpio1>; - interrupts = <22 IRQ_TYPE_LEVEL_LOW>; // TODO check interrupt? + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; rockchip,system-power-controller; wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; vcc1-supply = <&vcc5v0_sys>; vcc2-supply = <&vcc5v0_sys>; @@ -235,44 +203,44 @@ regulators { vdd_center: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vdd_center"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1350000>; regulator-ramp-delay = <6001>; - regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vdd_cpu_l: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vdd_cpu_l"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1350000>; regulator-ramp-delay = <6001>; - regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; regulator-always-on; regulator-boot-on; - regulator-name = "vcc_ddr"; regulator-state-mem { regulator-on-in-suspend; }; }; vcc_1v8: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; @@ -280,32 +248,32 @@ }; vcc_ldo1: LDO_REG1 { - regulator-boot-on; + regulator-name = "vcc_ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc_ldo1"; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc1v8_hdmi: LDO_REG2 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc1v8_hdmi"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_hdmi"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc1v8_pmu: LDO_REG3 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc1v8_pmu"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; @@ -313,11 +281,11 @@ }; vcc_sd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc_sd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; - regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3000000>; @@ -325,79 +293,105 @@ }; vcc_ldo5: LDO_REG5 { - regulator-boot-on; + regulator-name = "vcc_ldo5"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - regulator-name = "vcc_ldo5"; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc_ldo6: LDO_REG6 { - regulator-boot-on; + regulator-name = "vcc_ldo6"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; - regulator-name = "vcc_ldo6"; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc0v9_hdmi: LDO_REG7 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc0v9_hdmi"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; - regulator-name = "vcc0v9_hdmi"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc_efuse: LDO_REG8 { - regulator-always-on; - regulator-boot-on; + regulator-name = "vcc_efuse"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-name = "vcc_efuse"; + regulator-always-on; + regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; regulator-always-on; regulator-boot-on; - regulator-name = "vcc3v3_s3"; regulator-state-mem { regulator-off-in-suspend; }; }; vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; regulator-always-on; regulator-boot-on; - regulator-name = "vcc3v3_s0"; regulator-state-mem { regulator-off-in-suspend; }; }; }; }; + + vdd_gpu: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1230000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&i2c7 { + status = "okay"; + clock-frequency = <400000>; + + fan: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #cooling-cells = <2>; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; }; &i2c8 { status = "okay"; clock-frequency = <400000>; - vdd_cpu_b: vdd_cpu_b { - status = "okay"; + vdd_cpu_b: regulator@60 { compatible = "fcs,fan53555"; reg = <0x60>; - vsel-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; vin-supply = <&vcc5v0_sys>; - regulator-compatible = "fan53555-reg"; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1230000>; @@ -405,48 +399,36 @@ fcs,suspend-voltage-selector = <1>; regulator-always-on; regulator-boot-on; - regulator-initial-state = <3>; - regulator-state-mem { - regulator-off-in-suspend; - }; }; }; &i2s0 { + pinctrl-0 = <&i2s0_2ch_bus>; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; status = "okay"; - rockchip,i2s-broken-burst-len; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - #sound-dai-cells = <0>; }; -&i2s2 { - #sound-dai-cells = <0>; - status = "okay"; +/* + * As Q7 does not specify neither a global nor a RX clock for I2S these + * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO. + * Therefore we have to redefine the i2s0_2ch_bus definition to prevent + * conflicts. + */ +&i2s0_2ch_bus { + rockchip,pins = + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>; }; &io_domains { status = "okay"; - - bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */ - audio-supply = <&vcc_1v8>; /* audio_gpio3d4a_ms */ - sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ - gpio1830-supply = <&vcc_1v8>; /* gpio1833_gpio4cd_ms */ -}; - -&pcie0 { - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; - ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; + bt656-supply = <&vcc_1v8>; + audio-supply = <&vcc_1v8>; + sdmmc-supply = <&vcc_sd>; + gpio1830-supply = <&vcc_1v8>; }; &pmu_io_domains { @@ -454,195 +436,99 @@ pmu1830-supply = <&vcc_1v8>; }; -&pwm0 { - status = "okay"; -}; - &pwm2 { status = "okay"; }; -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - supports-emmc; - non-removable; - keep-power-in-suspend; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - clock-frequency = <150000000>; - max-frequency = <40000000>; - supports-sd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - num-slots = <1>; - vqmmc-supply = <&vcc_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "disabled"; -}; - -&usb_host0_ohci { - status = "disabled"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usb_host1_ehci { - status = "disabled"; -}; - -&usb_host1_ohci { - status = "disabled"; -}; - -&usbdrd3_1 { - status = "okay"; - tsd,usb-port-power = "usbhub_enable"; -}; - -&vopb { - status = "okay"; -}; - -&gpio1 { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - &pinctrl { - /* Pins that are not explicitely used by any devices */ - pinctrl-names = "default"; - pinctrl-0 = <&puma_pin_hog>; - - hog { - puma_pin_hog: puma_pin_hog { + i2c8 { + i2c8_xfer_a: i2c8-xfer { rockchip,pins = - /* We need pull-ups on Q7 buttons */ - , /* LID_BTN# */ - , /* BATLOW# */ - , /* SLP_BTN# */ - ; /* BIOS_DISABLE# */ + <1 RK_PC4 1 &pcfg_pull_up>, + <1 RK_PC5 1 &pcfg_pull_up>; }; }; - pmic { - pmic_int_l: pmic-int-l { + leds { + led_pin_module: led-module-gpio { rockchip,pins = - ; + <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - leds_pins_puma: led_pins@0 { - rockchip,pins = - , - ; - }; - - usb2 { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = - ; - }; - - host_vbus_drv: host-vbus-drv { + pmic { + pmic_int_l: pmic-int-l { rockchip,pins = - ; + <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; }; }; - i2c8 { - i2c8_xfer_a: i2c8-xfer { + usb2 { + vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = - , - ; + <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; -&i2c1 { +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; status = "okay"; - clock-frequency = <400000>; }; -&i2c2 { - status = "okay"; - clock-frequency = <400000>; + +&sdmmc { + vqmmc-supply = <&vcc_sd>; }; -&i2c4 { + +&spi1 { status = "okay"; - clock-frequency = <400000>; + + norflash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; }; -&i2c6 { + +&tcphy1 { status = "okay"; - clock-frequency = <400000>; }; -&i2c6_xfer { - /* Enable pull-ups, the pins would float otherwise. */ - rockchip,pins = - , - ; +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; }; -&i2c7 { +&u2phy1 { status = "okay"; - clock-frequency = <400000>; - rtc_twi: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; + u2phy1_otg: otg-port { + status = "okay"; }; - fan: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - cooling-min-state = <0>; - cooling-max-state = <9>; - #cooling-cells = <2>; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; }; }; -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; +&usbdrd3_1 { status = "okay"; }; - -&spi1 { +&usbdrd_dwc3_1 { status = "okay"; + dr_mode = "host"; +}; - #address-cells = <1>; - #size-cells = <0>; - - spiflash: w25q32dw@0 { - u-boot,dm-pre-reloc; - - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <49500000>; - spi-cpol; - spi-cpha; - }; +&usb_host1_ehci { + status = "okay"; }; -&spi5 { +&usb_host1_ohci { status = "okay"; }; diff --git a/arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi new file mode 100644 index 0000000000..f50c18dd3d --- /dev/null +++ b/arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "rk3399-roc-pc-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-roc-pc-mezzanine.dts b/arch/arm/dts/rk3399-roc-pc-mezzanine.dts new file mode 100644 index 0000000000..2acb3d500f --- /dev/null +++ b/arch/arm/dts/rk3399-roc-pc-mezzanine.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + * Copyright (c) 2019 Markus Reichl + */ + +/dts-v1/; +#include "rk3399-roc-pc.dtsi" + +/ { + model = "Firefly ROC-RK3399-PC Mezzanine Board"; + compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399"; + + vcc3v3_ngff: vcc3v3-ngff { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_ngff"; + enable-active-high; + gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_ngff_en>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_pcie: vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + enable-active-high; + gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_en>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_perst>; + vpcie3v3-supply = <&vcc3v3_pcie>; + vpcie1v8-supply = <&vcc1v8_pmu>; + vpcie0v9-supply = <&vcca_0v9>; + status = "okay"; +}; + +&pinctrl { + ngff { + vcc3v3_ngff_en: vcc3v3-ngff-en { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_pcie_en: vcc3v3-pcie-en { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_perst: pcie-perst { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_ngff>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index 5746442981..141dd0b306 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -14,9 +14,45 @@ chosen { u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; + + vcc_hub_en: vcc_hub_en-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_rst>; + regulator-name = "vcc_hub_en"; + regulator-always-on; + }; +}; + +/* + * should be placed inside mp8859, but not until mp8859 has + * its own dt-binding. + */ +&dc_12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc_vbus_typec0>; }; &vdd_log { regulator-min-microvolt = <430000>; regulator-init-microvolt = <950000>; }; + +&vcc5v0_host { + regulator-always-on; +}; + +&vcc_sys { + regulator-always-on; +}; + +&vcc_sdio { + regulator-always-on; +}; diff --git a/arch/arm/dts/rk3399-roc-pc.dts b/arch/arm/dts/rk3399-roc-pc.dts index 6a909e4eef..cd41954253 100644 --- a/arch/arm/dts/rk3399-roc-pc.dts +++ b/arch/arm/dts/rk3399-roc-pc.dts @@ -8,6 +8,5 @@ / { model = "Firefly ROC-RK3399-PC Board"; - compatible = "libretech,roc-rk3399-pc", "firefly,roc-rk3399-pc", - "rockchip,rk3399"; + compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; }; diff --git a/arch/arm/dts/rk3399-roc-pc.dtsi b/arch/arm/dts/rk3399-roc-pc.dtsi index 9a1ce3a4ae..9f225e9c3d 100644 --- a/arch/arm/dts/rk3399-roc-pc.dtsi +++ b/arch/arm/dts/rk3399-roc-pc.dtsi @@ -110,20 +110,6 @@ regulator-max-microvolt = <5000000>; }; - /* - * should be placed inside mp8859, but not until mp8859 has - * its own dt-binding. - */ - dc_12v: mp8859-dcdc1 { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <&vcc_vbus_typec0>; - }; - /* switched by pmic_sleep */ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; @@ -176,7 +162,6 @@ pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_host_en &hub_rst>; regulator-name = "vcc5v0_host"; - regulator-always-on; vin-supply = <&vcc_sys>; }; @@ -198,7 +183,6 @@ pinctrl-names = "default"; pinctrl-0 = <&vcc_sys_en>; regulator-name = "vcc_sys"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -392,7 +376,6 @@ vcc_sdio: LDO_REG4 { regulator-name = "vcc_sdio"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; @@ -549,6 +532,24 @@ vbus-supply = <&vcc_vbus_typec0>; status = "okay"; }; + + mp8859: regulator@66 { + compatible = "mps,mp8859"; + reg = <0x66>; + dc_12v: mp8859_dcdc { + regulator-name = "dc_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_vbus_typec0>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + }; }; &i2s0 { diff --git a/arch/arm/dts/rk3399-rock-pi-4.dts b/arch/arm/dts/rk3399-rock-pi-4.dts index 4a543f2117..3923ec01ef 100644 --- a/arch/arm/dts/rk3399-rock-pi-4.dts +++ b/arch/arm/dts/rk3399-rock-pi-4.dts @@ -25,6 +25,15 @@ #clock-cells = <0>; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + vcc12v_dcin: dc-12v { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -44,6 +53,16 @@ vin-supply = <&vcc12v_dcin>; }; + vcc_0v9: vcc-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -157,12 +176,22 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { + ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>; status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; @@ -444,13 +473,60 @@ pmu1830-supply = <&vcc_3v0>; }; +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <4>; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + pinctrl-names = "default"; + vpcie0v9-supply = <&vcc_0v9>; + vpcie1v8-supply = <&vcc_1v8>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + sdio0 { + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>, + <2 RK_PC5 1 &pcfg_pull_up_20ma>, + <2 RK_PC6 1 &pcfg_pull_up_20ma>, + <2 RK_PC7 1 &pcfg_pull_up_20ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; @@ -476,6 +552,16 @@ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm2 { @@ -488,6 +574,32 @@ vref-supply = <&vcc_1v8>; }; +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; @@ -551,6 +663,23 @@ }; }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; +}; + &uart2 { status = "okay"; }; diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts index 12285c51cc..437a75f31a 100644 --- a/arch/arm/dts/rk3399-rock960.dts +++ b/arch/arm/dts/rk3399-rock960.dts @@ -114,6 +114,55 @@ }; }; +&spi0 { + /* On Low speed expansion (LS-SPI0) */ + status = "okay"; +}; + +&spi4 { + /* On High speed expansion (HS-SPI1) */ + status = "okay"; +}; + +&thermal_zones { + cpu_thermal: cpu { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&tsadc 0>; + sustainable-power = <1550>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <65000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_alert1: cpu_alert1 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + + trip = <&cpu_alert1>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + &usbdrd_dwc3_0 { dr_mode = "otg"; }; diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi index c7d48d41e1..ba7c75c9f2 100644 --- a/arch/arm/dts/rk3399-rock960.dtsi +++ b/arch/arm/dts/rk3399-rock960.dtsi @@ -76,6 +76,15 @@ regulator-always-on; vin-supply = <&vcc5v0_sys>; }; + + vcc_0v9: vcc-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; }; &cpu_l0 { @@ -384,6 +393,8 @@ num-lanes = <4>; pinctrl-names = "default"; pinctrl-0 = <&pcie_clkreqn_cpm>; + vpcie0v9-supply = <&vcc_0v9>; + vpcie1v8-supply = <&vcca_1v8>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; }; @@ -531,7 +542,7 @@ cap-mmc-highspeed; cap-sd-highspeed; clock-frequency = <100000000>; - clock-freq-min-max = <100000 100000000>; + max-frequency = <100000000>; cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; disable-wp; sd-uhs-sdr104; diff --git a/arch/arm/dts/rk3399-rockpro64.dts b/arch/arm/dts/rk3399-rockpro64.dts index e544deb61d..4b42717800 100644 --- a/arch/arm/dts/rk3399-rockpro64.dts +++ b/arch/arm/dts/rk3399-rockpro64.dts @@ -2,752 +2,29 @@ /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. * Copyright (c) 2018 Akash Gajjar + * Copyright (c) 2019 Katsuhiro Suzuki */ /dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" +#include "rk3399-rockpro64.dtsi" / { - model = "Pine64 RockPro64"; - compatible = "pine64,rockpro64", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; - - work-led { - label = "work"; - default-state = "on"; - gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - }; - - diy-led { - label = "diy"; - default-state = "off"; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - fan-supply = <&vcc12v_dcin>; - pwms = <&pwm1 0 50000 0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwr_en>; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_typec: vcc5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vcc5v0_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1700000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio3>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcca_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_touch: LDO_REG2 { - regulator-name = "vcc3v0_touch"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_gpio>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_gpio>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; + model = "Pine64 RockPro64 v2.1"; + compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399"; }; &i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb0: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc5v0_typec>; - status = "okay"; - }; -}; + es8316: codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc1v8_dvp>; - audio-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pcie0 { - ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_perst>; - vpcie12v-supply = <&vcc12v_dcin>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pinctrl { - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fusb302x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - work_led_gpio: work_led-gpio { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - diy_led_gpio: diy_led-gpio { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_perst: pcie-perst { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0_typec_en { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s1_p0_0>; + }; }; }; }; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&spi1 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-rockpro64.dtsi b/arch/arm/dts/rk3399-rockpro64.dtsi new file mode 100644 index 0000000000..9bca258012 --- /dev/null +++ b/arch/arm/dts/rk3399-rockpro64.dtsi @@ -0,0 +1,797 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2018 Akash Gajjar + */ + +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; + + work-led { + label = "work"; + default-state = "on"; + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + diy-led { + label = "diy"; + default-state = "off"; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + fan-supply = <&vcc12v_dcin>; + pwms = <&pwm1 0 50000 0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "audio-graph-card"; + label = "rockchip,rk3399"; + dais = <&i2s1_p0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1700000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_typec>; + status = "okay"; + }; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; + + i2s1_p0: port { + i2s1_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_perst>; + vpcie12v-supply = <&vcc12v_dcin>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + work_led_gpio: work_led-gpio { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_gpio: diy_led-gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_perst: pcie-perst { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 8b857ccfc7..9bb130a92a 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -25,6 +25,12 @@ clock-names = "pclk_ddr_mon"; }; + rng: rng@ff8b8000 { + compatible = "rockchip,cryptov1-rng"; + reg = <0x0 0xff8b8000 0x0 0x1000>; + status = "disabled"; + }; + dmc: dmc { u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-dmc"; @@ -79,6 +85,7 @@ }; &sdhci { + max-frequency = <200000000>; u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 6b7c136ab8..74f2c3d490 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd */ #include @@ -19,6 +19,7 @@ #size-cells = <2>; aliases { + ethernet0 = &gmac; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -67,53 +68,102 @@ cpu_l0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <485>; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + capacity-dmips-mhz = <485>; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + capacity-dmips-mhz = <485>; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_l3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + capacity-dmips-mhz = <485>; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_b0: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x100>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <436>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; cpu_b1: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x101>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <436>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + }; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vopl_out>, <&vopb_out>; }; pmu_a53 { @@ -147,7 +197,7 @@ #clock-cells = <0>; }; - amba { + amba: bus { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -183,7 +233,7 @@ #size-cells = <2>; #interrupt-cells = <1>; aspm-no-l0s; - bus-range = <0x0 0x1>; + bus-range = <0x0 0x1f>; clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; clock-names = "aclk", "aclk-perf", @@ -200,10 +250,12 @@ linux,pci-domain = <0>; max-link-speed = <1>; msi-map = <0x0 &its 0x0 0x1000>; - phys = <&pcie_phy>; - phy-names = "pcie-phy"; - ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 - 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; + phys = <&pcie_phy 0>, <&pcie_phy 1>, + <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", + "pcie-phy-2", "pcie-phy-3"; + ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 + 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, @@ -236,10 +288,11 @@ resets = <&cru SRST_A_GMAC>; reset-names = "stmmaceth"; rockchip,grf = <&grf>; + snps,txpbl = <0x4>; status = "disabled"; }; - sdio0: dwmmc@fe310000 { + sdio0: mmc@fe310000 { compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; @@ -255,12 +308,14 @@ status = "disabled"; }; - sdmmc: dwmmc@fe320000 { + sdmmc: mmc@fe320000 { compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; interrupts = ; max-frequency = <150000000>; + assigned-clocks = <&cru HCLK_SD>; + assigned-clock-rates = <200000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; @@ -278,7 +333,6 @@ arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; - max-frequency = <200000000>; clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; clock-names = "clk_xin", "clk_ahb"; clock-output-names = "emmc_cardclock"; @@ -286,6 +340,7 @@ phys = <&emmc_phy>; phy-names = "phy_arasan"; power-domains = <&power RK3399_PD_EMMC>; + disable-cqe-dcmd; status = "disabled"; }; @@ -295,11 +350,8 @@ interrupts = ; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, <&u2phy0>; - clock-names = "usbhost", "arbiter", - "utmi"; phys = <&u2phy0_host>; phy-names = "usb"; - power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; @@ -309,11 +361,8 @@ interrupts = ; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, <&u2phy0>; - clock-names = "usbhost", "arbiter", - "utmi"; phys = <&u2phy0_host>; phy-names = "usb"; - power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; @@ -323,11 +372,8 @@ interrupts = ; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, <&u2phy1>; - clock-names = "usbhost", "arbiter", - "utmi"; phys = <&u2phy1_host>; phy-names = "usb"; - power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; @@ -337,15 +383,12 @@ interrupts = ; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, <&u2phy1>; - clock-names = "usbhost", "arbiter", - "utmi"; phys = <&u2phy1_host>; phy-names = "usb"; - power-domains = <&power RK3399_PD_PERIHP>; status = "disabled"; }; - usbdrd3_0: dwc3_typec0: usb@fe800000 { + usbdrd3_0: usb@fe800000 { compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>; #size-cells = <2>; @@ -364,6 +407,9 @@ compatible = "snps,dwc3"; reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = ; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, + <&cru SCLK_USB3OTG0_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; dr_mode = "otg"; phys = <&u2phy0_otg>, <&tcphy0_usb3>; phy-names = "usb2-phy", "usb3-phy"; @@ -378,7 +424,7 @@ }; }; - dwc3_typec1: usbdrd3_1: usb@fe900000 { + usbdrd3_1: usb@fe900000 { compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>; #size-cells = <2>; @@ -397,6 +443,9 @@ compatible = "snps,dwc3"; reg = <0x0 0xfe900000 0x0 0x100000>; interrupts = ; + clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, + <&cru SCLK_USB3OTG1_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; dr_mode = "otg"; phys = <&u2phy1_otg>, <&tcphy1_usb3>; phy-names = "usb2-phy", "usb3-phy"; @@ -464,6 +513,7 @@ its: interrupt-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x0 0xfee20000 0x0 0x20000>; }; @@ -612,7 +662,6 @@ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; interrupts = ; - clock-frequency = <24000000>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -639,6 +688,8 @@ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 10>, <&dmac_peri 11>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; #address-cells = <1>; @@ -652,6 +703,8 @@ clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 12>, <&dmac_peri 13>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; #address-cells = <1>; @@ -665,6 +718,8 @@ clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 14>, <&dmac_peri 15>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; #address-cells = <1>; @@ -678,6 +733,8 @@ clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 18>, <&dmac_peri 19>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; #address-cells = <1>; @@ -691,8 +748,11 @@ clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_bus 8>, <&dmac_bus 9>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -727,13 +787,18 @@ map0 { trip = <&cpu_alert0>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu_alert1>; cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -761,7 +826,7 @@ map0 { trip = <&gpu_alert0>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -980,22 +1045,11 @@ <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; }; - pd_perihp@RK3399_PD_PERIHP { - reg = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru ACLK_PERIHP>; - pm_qos = <&qos_perihp>, - <&qos_pcie>, - <&qos_usb_host0>, - <&qos_usb_host1>; - - pd_sd@RK3399_PD_SD { - reg = ; - clocks = <&cru HCLK_SDMMC>, - <&cru SCLK_SDMMC>; - pm_qos = <&qos_sd>; - }; + pd_sd@RK3399_PD_SD { + reg = ; + clocks = <&cru HCLK_SDMMC>, + <&cru SCLK_SDMMC>; + pm_qos = <&qos_sd>; }; pd_sdioaudio@RK3399_PD_SDIOAUDIO { reg = ; @@ -1070,6 +1124,8 @@ pmugrf: syscon@ff320000 { compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; pmu_io_domains: io-domains { compatible = "rockchip,rk3399-pmu-io-voltage-domain"; @@ -1192,6 +1248,62 @@ status = "disabled"; }; + vpu: video-codec@ff650000 { + compatible = "rockchip,rk3399-vpu"; + reg = <0x0 0xff650000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3399_PD_VCODEC>; + }; + + vpu_mmu: iommu@ff650800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff650800 0x0 0x40>; + interrupts = ; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3399_PD_VCODEC>; + }; + + vdec_mmu: iommu@ff660480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; + interrupts = ; + interrupt-names = "vdec_mmu"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + iep_mmu: iommu@ff670800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff670800 0x0 0x40>; + interrupts = ; + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga: rga@ff680000 { + compatible = "rockchip,rk3399-rga"; + reg = <0x0 0xff680000 0x0 0x10000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3399_PD_RGA>; + }; + efuse0: efuse@ff690000 { compatible = "rockchip,rk3399-efuse"; reg = <0x0 0xff690000 0x0 0x80>; @@ -1342,8 +1454,9 @@ compatible = "rockchip,rk3399-pcie-phy"; clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; - #phy-cells = <0>; + #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; + drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; @@ -1592,11 +1705,11 @@ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; interrupts = ; interrupt-names = "isp0_mmu"; - clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; + clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; clock-names = "aclk", "iface"; #iommu-cells = <0>; + power-domains = <&power RK3399_PD_ISP0>; rockchip,disable-mmu-reset; - status = "disabled"; }; isp1_mmu: iommu@ff924000 { @@ -1604,11 +1717,11 @@ reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; interrupts = ; interrupt-names = "isp1_mmu"; - clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; + clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; clock-names = "aclk", "iface"; #iommu-cells = <0>; + power-domains = <&power RK3399_PD_ISP1>; rockchip,disable-mmu-reset; - status = "disabled"; }; hdmi_sound: hdmi-sound { @@ -1660,21 +1773,29 @@ }; mipi_dsi: mipi@ff960000 { - compatible = "rockchip,rk3399_mipi_dsi"; + compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = ; - clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, - <&cru SCLK_DPHY_TX0_CFG>; - clock-names = "ref", "pclk", "phy_cfg"; + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, + <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; + clock-names = "ref", "pclk", "phy_cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + resets = <&cru SRST_P_MIPI_DSI0>; + reset-names = "apb"; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; + ports { - reg = <1>; - mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; + mipi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_mipi>; @@ -1698,6 +1819,8 @@ resets = <&cru SRST_P_MIPI_DSI1>; reset-names = "apb"; rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; ports { @@ -1765,6 +1888,7 @@ ; interrupt-names = "gpu", "job", "mmu"; clocks = <&cru ACLK_GPU>; + #cooling-cells = <2>; power-domains = <&power RK3399_PD_GPU>; status = "disabled"; }; @@ -1929,14 +2053,14 @@ clock { clk_32k: clk-32k { - rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; }; edp { edp_hpd: edp-hpd { rockchip,pins = - <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; + <4 RK_PC7 2 &pcfg_pull_none>; }; }; @@ -1944,382 +2068,409 @@ rgmii_pins: rgmii-pins { rockchip,pins = /* mac_txclk */ - <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PC1 1 &pcfg_pull_none_13ma>, /* mac_rxclk */ - <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB6 1 &pcfg_pull_none>, /* mac_mdio */ - <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB5 1 &pcfg_pull_none>, /* mac_txen */ - <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PB4 1 &pcfg_pull_none_13ma>, /* mac_clk */ - <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB3 1 &pcfg_pull_none>, /* mac_rxdv */ - <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB1 1 &pcfg_pull_none>, /* mac_mdc */ - <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB0 1 &pcfg_pull_none>, /* mac_rxd1 */ - <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA7 1 &pcfg_pull_none>, /* mac_rxd0 */ - <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA6 1 &pcfg_pull_none>, /* mac_txd1 */ - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PA5 1 &pcfg_pull_none_13ma>, /* mac_txd0 */ - <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PA4 1 &pcfg_pull_none_13ma>, /* mac_rxd3 */ - <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA3 1 &pcfg_pull_none>, /* mac_rxd2 */ - <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA2 1 &pcfg_pull_none>, /* mac_txd3 */ - <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PA1 1 &pcfg_pull_none_13ma>, /* mac_txd2 */ - <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>; + <3 RK_PA0 1 &pcfg_pull_none_13ma>; }; rmii_pins: rmii-pins { rockchip,pins = /* mac_mdio */ - <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB5 1 &pcfg_pull_none>, /* mac_txen */ - <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PB4 1 &pcfg_pull_none_13ma>, /* mac_clk */ - <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB3 1 &pcfg_pull_none>, /* mac_rxer */ - <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB2 1 &pcfg_pull_none>, /* mac_rxdv */ - <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB1 1 &pcfg_pull_none>, /* mac_mdc */ - <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PB0 1 &pcfg_pull_none>, /* mac_rxd1 */ - <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA7 1 &pcfg_pull_none>, /* mac_rxd0 */ - <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, + <3 RK_PA6 1 &pcfg_pull_none>, /* mac_txd1 */ - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, + <3 RK_PA5 1 &pcfg_pull_none_13ma>, /* mac_txd0 */ - <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>; + <3 RK_PA4 1 &pcfg_pull_none_13ma>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = - <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; + <1 RK_PB7 2 &pcfg_pull_none>, + <1 RK_PC0 2 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { rockchip,pins = - <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PA2 1 &pcfg_pull_none>, + <4 RK_PA1 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { rockchip,pins = - <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, - <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>; + <2 RK_PA1 2 &pcfg_pull_none_12ma>, + <2 RK_PA0 2 &pcfg_pull_none_12ma>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { rockchip,pins = - <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC1 1 &pcfg_pull_none>, + <4 RK_PC0 1 &pcfg_pull_none>; }; }; i2c4 { i2c4_xfer: i2c4-xfer { rockchip,pins = - <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PB4 1 &pcfg_pull_none>, + <1 RK_PB3 1 &pcfg_pull_none>; }; }; i2c5 { i2c5_xfer: i2c5-xfer { rockchip,pins = - <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>, - <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PB3 2 &pcfg_pull_none>, + <3 RK_PB2 2 &pcfg_pull_none>; }; }; i2c6 { i2c6_xfer: i2c6-xfer { rockchip,pins = - <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; + <2 RK_PB2 2 &pcfg_pull_none>, + <2 RK_PB1 2 &pcfg_pull_none>; }; }; i2c7 { i2c7_xfer: i2c7-xfer { rockchip,pins = - <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; + <2 RK_PB0 2 &pcfg_pull_none>, + <2 RK_PA7 2 &pcfg_pull_none>; }; }; i2c8 { i2c8_xfer: i2c8-xfer { rockchip,pins = - <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PC5 1 &pcfg_pull_none>, + <1 RK_PC4 1 &pcfg_pull_none>; }; }; i2s0 { + i2s0_2ch_bus: i2s0-2ch-bus { + rockchip,pins = + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none>; + }; + i2s0_8ch_bus: i2s0-8ch-bus { rockchip,pins = - <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>, - <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD4 1 &pcfg_pull_none>, + <3 RK_PD5 1 &pcfg_pull_none>, + <3 RK_PD6 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none>; }; }; i2s1 { i2s1_2ch_bus: i2s1-2ch-bus { rockchip,pins = - <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, - <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PA3 1 &pcfg_pull_none>, + <4 RK_PA4 1 &pcfg_pull_none>, + <4 RK_PA5 1 &pcfg_pull_none>, + <4 RK_PA6 1 &pcfg_pull_none>, + <4 RK_PA7 1 &pcfg_pull_none>; }; }; sdio0 { sdio0_bus1: sdio0-bus1 { rockchip,pins = - <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PC4 1 &pcfg_pull_up>; }; sdio0_bus4: sdio0-bus4 { rockchip,pins = - <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PC4 1 &pcfg_pull_up>, + <2 RK_PC5 1 &pcfg_pull_up>, + <2 RK_PC6 1 &pcfg_pull_up>, + <2 RK_PC7 1 &pcfg_pull_up>; }; sdio0_cmd: sdio0-cmd { rockchip,pins = - <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PD0 1 &pcfg_pull_up>; }; sdio0_clk: sdio0-clk { rockchip,pins = - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + <2 RK_PD1 1 &pcfg_pull_none>; }; sdio0_cd: sdio0-cd { rockchip,pins = - <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PD2 1 &pcfg_pull_up>; }; sdio0_pwr: sdio0-pwr { rockchip,pins = - <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PD3 1 &pcfg_pull_up>; }; sdio0_bkpwr: sdio0-bkpwr { rockchip,pins = - <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PD4 1 &pcfg_pull_up>; }; sdio0_wp: sdio0-wp { rockchip,pins = - <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; + <0 RK_PA3 1 &pcfg_pull_up>; }; sdio0_int: sdio0-int { rockchip,pins = - <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; + <0 RK_PA4 1 &pcfg_pull_up>; }; }; sdmmc { sdmmc_bus1: sdmmc-bus1 { rockchip,pins = - <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; + <4 RK_PB0 1 &pcfg_pull_up>; }; sdmmc_bus4: sdmmc-bus4 { rockchip,pins = - <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, - <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, - <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, - <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; + <4 RK_PB0 1 &pcfg_pull_up>, + <4 RK_PB1 1 &pcfg_pull_up>, + <4 RK_PB2 1 &pcfg_pull_up>, + <4 RK_PB3 1 &pcfg_pull_up>; }; sdmmc_clk: sdmmc-clk { rockchip,pins = - <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PB4 1 &pcfg_pull_none>; }; sdmmc_cmd: sdmmc-cmd { rockchip,pins = - <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; + <4 RK_PB5 1 &pcfg_pull_up>; }; sdmmc_cd: sdmmc-cd { rockchip,pins = - <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; + <0 RK_PA7 1 &pcfg_pull_up>; }; sdmmc_wp: sdmmc-wp { rockchip,pins = - <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; + <0 RK_PB0 1 &pcfg_pull_up>; }; }; sleep { ap_pwroff: ap-pwroff { - rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; }; ddrio_pwroff: ddrio-pwroff { - rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; }; }; spdif { spdif_bus: spdif-bus { rockchip,pins = - <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC5 1 &pcfg_pull_none>; }; spdif_bus_1: spdif-bus-1 { rockchip,pins = - <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; + <3 RK_PC0 3 &pcfg_pull_none>; }; }; spi0 { spi0_clk: spi0-clk { rockchip,pins = - <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA6 2 &pcfg_pull_up>; }; spi0_cs0: spi0-cs0 { rockchip,pins = - <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA7 2 &pcfg_pull_up>; }; spi0_cs1: spi0-cs1 { rockchip,pins = - <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PB0 2 &pcfg_pull_up>; }; spi0_tx: spi0-tx { rockchip,pins = - <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA5 2 &pcfg_pull_up>; }; spi0_rx: spi0-rx { rockchip,pins = - <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA4 2 &pcfg_pull_up>; }; }; spi1 { spi1_clk: spi1-clk { rockchip,pins = - <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>; + <1 RK_PB1 2 &pcfg_pull_up>; }; spi1_cs0: spi1-cs0 { rockchip,pins = - <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>; + <1 RK_PB2 2 &pcfg_pull_up>; }; spi1_rx: spi1-rx { rockchip,pins = - <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; + <1 RK_PA7 2 &pcfg_pull_up>; }; spi1_tx: spi1-tx { rockchip,pins = - <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; + <1 RK_PB0 2 &pcfg_pull_up>; }; }; spi2 { spi2_clk: spi2-clk { rockchip,pins = - <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PB3 1 &pcfg_pull_up>; }; spi2_cs0: spi2-cs0 { rockchip,pins = - <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PB4 1 &pcfg_pull_up>; }; spi2_rx: spi2-rx { rockchip,pins = - <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PB1 1 &pcfg_pull_up>; }; spi2_tx: spi2-tx { rockchip,pins = - <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>; + <2 RK_PB2 1 &pcfg_pull_up>; }; }; spi3 { spi3_clk: spi3-clk { rockchip,pins = - <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>; + <1 RK_PC1 1 &pcfg_pull_up>; }; spi3_cs0: spi3-cs0 { rockchip,pins = - <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>; + <1 RK_PC2 1 &pcfg_pull_up>; }; spi3_rx: spi3-rx { rockchip,pins = - <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>; + <1 RK_PB7 1 &pcfg_pull_up>; }; spi3_tx: spi3-tx { rockchip,pins = - <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>; + <1 RK_PC0 1 &pcfg_pull_up>; }; }; spi4 { spi4_clk: spi4-clk { rockchip,pins = - <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA2 2 &pcfg_pull_up>; }; spi4_cs0: spi4-cs0 { rockchip,pins = - <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA3 2 &pcfg_pull_up>; }; spi4_rx: spi4-rx { rockchip,pins = - <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA0 2 &pcfg_pull_up>; }; spi4_tx: spi4-tx { rockchip,pins = - <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>; + <3 RK_PA1 2 &pcfg_pull_up>; }; }; spi5 { spi5_clk: spi5-clk { rockchip,pins = - <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>; + <2 RK_PC6 2 &pcfg_pull_up>; }; spi5_cs0: spi5-cs0 { rockchip,pins = - <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>; + <2 RK_PC7 2 &pcfg_pull_up>; }; spi5_rx: spi5-rx { rockchip,pins = - <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>; + <2 RK_PC4 2 &pcfg_pull_up>; }; spi5_tx: spi5-tx { rockchip,pins = - <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>; + <2 RK_PC5 2 &pcfg_pull_up>; + }; + }; + + testclk { + test_clkout0: test-clkout0 { + rockchip,pins = + <0 RK_PA0 1 &pcfg_pull_none>; + }; + + test_clkout1: test-clkout1 { + rockchip,pins = + <2 RK_PD1 2 &pcfg_pull_none>; + }; + + test_clkout2: test-clkout2 { + rockchip,pins = + <0 RK_PB0 3 &pcfg_pull_none>; }; }; @@ -2329,168 +2480,168 @@ }; otp_out: otp-out { - rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { rockchip,pins = - <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; + <2 RK_PC0 1 &pcfg_pull_up>, + <2 RK_PC1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { rockchip,pins = - <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; + <2 RK_PC2 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { rockchip,pins = - <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; + <2 RK_PC3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { rockchip,pins = - <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PB4 2 &pcfg_pull_up>, + <3 RK_PB5 2 &pcfg_pull_none>; }; }; uart2a { uart2a_xfer: uart2a-xfer { rockchip,pins = - <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>, - <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; + <4 RK_PB0 2 &pcfg_pull_up>, + <4 RK_PB1 2 &pcfg_pull_none>; }; }; uart2b { uart2b_xfer: uart2b-xfer { rockchip,pins = - <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, - <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; + <4 RK_PC0 2 &pcfg_pull_up>, + <4 RK_PC1 2 &pcfg_pull_none>; }; }; uart2c { uart2c_xfer: uart2c-xfer { rockchip,pins = - <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>, - <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC3 1 &pcfg_pull_up>, + <4 RK_PC4 1 &pcfg_pull_none>; }; }; uart3 { uart3_xfer: uart3-xfer { rockchip,pins = - <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PB6 2 &pcfg_pull_up>, + <3 RK_PB7 2 &pcfg_pull_none>; }; uart3_cts: uart3-cts { rockchip,pins = - <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PC0 2 &pcfg_pull_none>; }; uart3_rts: uart3-rts { rockchip,pins = - <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; + <3 RK_PC1 2 &pcfg_pull_none>; }; }; uart4 { uart4_xfer: uart4-xfer { rockchip,pins = - <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>, - <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PA7 1 &pcfg_pull_up>, + <1 RK_PB0 1 &pcfg_pull_none>; }; }; uarthdcp { uarthdcp_xfer: uarthdcp-xfer { rockchip,pins = - <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>, - <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; + <4 RK_PC5 2 &pcfg_pull_up>, + <4 RK_PC6 2 &pcfg_pull_none>; }; }; pwm0 { pwm0_pin: pwm0-pin { rockchip,pins = - <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC2 1 &pcfg_pull_none>; + }; + + pwm0_pin_pull_down: pwm0-pin-pull-down { + rockchip,pins = + <4 RK_PC2 1 &pcfg_pull_down>; }; vop0_pwm_pin: vop0-pwm-pin { rockchip,pins = - <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + <4 RK_PC2 2 &pcfg_pull_none>; + }; + + vop1_pwm_pin: vop1-pwm-pin { + rockchip,pins = + <4 RK_PC2 3 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { rockchip,pins = - <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC6 1 &pcfg_pull_none>; }; - vop1_pwm_pin: vop1-pwm-pin { + pwm1_pin_pull_down: pwm1-pin-pull-down { rockchip,pins = - <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; + <4 RK_PC6 1 &pcfg_pull_down>; }; }; pwm2 { pwm2_pin: pwm2-pin { rockchip,pins = - <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PC3 1 &pcfg_pull_none>; }; pwm2_pin_pull_down: pwm2-pin-pull-down { rockchip,pins = - <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>; + <1 RK_PC3 1 &pcfg_pull_down>; }; }; pwm3a { pwm3a_pin: pwm3a-pin { rockchip,pins = - <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + <0 RK_PA6 1 &pcfg_pull_none>; }; }; pwm3b { pwm3b_pin: pwm3b-pin { rockchip,pins = - <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; + <1 RK_PB6 1 &pcfg_pull_none>; }; }; hdmi { hdmi_i2c_xfer: hdmi-i2c-xfer { rockchip,pins = - <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, - <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; + <4 RK_PC1 3 &pcfg_pull_none>, + <4 RK_PC0 3 &pcfg_pull_none>; }; hdmi_cec: hdmi-cec { rockchip,pins = - <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; + <4 RK_PC7 1 &pcfg_pull_none>; }; }; pcie { - pcie_clkreqn: pci-clkreqn { - rockchip,pins = - <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; - }; - - pcie_clkreqnb: pci-clkreqnb { - rockchip,pins = - <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; - }; - pcie_clkreqn_cpm: pci-clkreqn-cpm { rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/board/firefly/roc-pc-rk3399/MAINTAINERS b/board/firefly/roc-pc-rk3399/MAINTAINERS index 7564dd252d..68a5b757d1 100644 --- a/board/firefly/roc-pc-rk3399/MAINTAINERS +++ b/board/firefly/roc-pc-rk3399/MAINTAINERS @@ -1,6 +1,8 @@ ROC-RK3399-PC M: Levin Du +M: Suniel Mahesh S: Maintained F: board/firefly/roc-pc-rk3399 F: include/configs/roc-pc-rk3399.h F: configs/roc-pc-rk3399_defconfig +F: configs/roc-pc-mezzanine-rk3399_defconfig diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c index de9185a7ce..0fe1914c0f 100644 --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c @@ -10,7 +10,6 @@ #include #include #include -#include #ifndef CONFIG_SPL_BUILD int board_early_init_f(void) @@ -34,26 +33,13 @@ out: #if defined(CONFIG_TPL_BUILD) -#define PMUGRF_BASE 0xff320000 #define GPIO0_BASE 0xff720000 int board_early_init_f(void) { struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE; - struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; - /** - * 1. Glow yellow LED, termed as low power - * 2. Poll for on board power key press - * 3. Once 2 done, off yellow and glow red LED, termed as full power - * 4. Continue booting... - */ - spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1); - - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), GPIO_PULL_NORMAL); - while (readl(&gpio0->ext_port) & 0x20); - - spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0); + /* Turn on red LED, indicating full power mode */ spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); return 0; diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index c661d2e06a..89becf41c5 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig +ROC-RK3328-CC +M: Loic Devulder +M: Chen-Yu Tsai +S: Maintained +F: configs/roc-cc-rk3328_defconfig +F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi + ROCK64-RK3328 M: Matwey V. Kornilov S: Maintained diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 0834254f6d..792df1087f 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -42,6 +42,13 @@ S: Maintained F: configs/nanopi-m4-rk3399_defconfig F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi +NANOPI-M4-2GB +M: Jagan Teki +M: Deepak Das +S: Maintained +F: configs/nanopi-m4-2gb-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi + NANOPI-NEO4 M: Jagan Teki S: Maintained diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index f8d66745dc..b2fda44ec2 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -85,6 +85,8 @@ CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y CONFIG_ROCKCHIP_SDRAM_COMMON=y CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 5bbdc00214..7667bb037b 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -61,7 +61,6 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 3f74be3b3c..7f14e18b1b 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -39,6 +39,8 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig new file mode 100644 index 0000000000..93c8db979c --- /dev/null +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_KEYBOARD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig new file mode 100644 index 0000000000..933a1c6967 --- /dev/null +++ b/configs/roc-cc-rk3328_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SMBIOS_PRODUCT_NAME="roc-rk3328-cc" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_SMBIOS_MANUFACTURER="firefly" diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig new file mode 100644 index 0000000000..5a694edc03 --- /dev/null +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_ROC_PC_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_TPL_GPIO_SUPPORT=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_KEYBOARD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 826c7a6917..7d096d38c6 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -60,7 +60,6 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 9b699b9ae5..70c8798ed2 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -52,10 +52,12 @@ Two RK3308 boards are supported: - EVB RK3308 - use evb-rk3308 configuration - ROC-CC-RK3308 - use roc-cc-rk3308 configuration -Two RK3328 board are supported: +Three RK3328 boards are supported: - EVB RK3328 - use evb-rk3328_defconfig - Pine64 Rock64 board - use rock64-rk3328_defconfig + - Firefly / Libre Computer Project ROC-RK3328-CC board - + use roc-cc-rk3328_defconfig Size RK3399 boards are supported (aarch64): diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 1f62376595..d822acace1 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -996,6 +996,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) break; case ACLK_VOP1: case HCLK_VOP1: + case HCLK_SD: /** * assigned-clocks handling won't require for vopl, so * return 0 to satisfy clk_set_defaults during device probe. diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig index edb6152bb9..e4b22d79eb 100644 --- a/drivers/rng/Kconfig +++ b/drivers/rng/Kconfig @@ -31,4 +31,12 @@ config RNG_STM32MP1 help Enable STM32MP1 rng driver. +config RNG_ROCKCHIP + bool "Enable random number generator for rockchip crypto rng" + depends on ARCH_ROCKCHIP && DM_RNG + default n + help + Enable random number generator for rockchip.This driver is + support rng module of crypto v1 and crypto v2. + endif diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile index 6a8a66779b..44a0003917 100644 --- a/drivers/rng/Makefile +++ b/drivers/rng/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o obj-$(CONFIG_RNG_MESON) += meson-rng.o obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o +obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c new file mode 100644 index 0000000000..47fb140077 --- /dev/null +++ b/drivers/rng/rockchip_rng.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ +#include +#include +#include +#include +#include +#include +#include + +#define RK_HW_RNG_MAX 32 + +#define _SBF(s, v) ((v) << (s)) + +/* start of CRYPTO V1 register define */ +#define CRYPTO_V1_CTRL 0x0008 +#define CRYPTO_V1_RNG_START BIT(8) +#define CRYPTO_V1_RNG_FLUSH BIT(9) + +#define CRYPTO_V1_TRNG_CTRL 0x0200 +#define CRYPTO_V1_OSC_ENABLE BIT(16) +#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x) + +#define CRYPTO_V1_TRNG_DOUT_0 0x0204 +/* end of CRYPTO V1 register define */ + +/* start of CRYPTO V2 register define */ +#define CRYPTO_V2_RNG_CTL 0x0400 +#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) +#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) +#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) +#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03) +#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00) +#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01) +#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02) +#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) +#define CRYPTO_V2_RNG_ENABLE BIT(1) +#define CRYPTO_V2_RNG_START BIT(0) +#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404 +#define CRYPTO_V2_RNG_DOUT_0 0x0410 +/* end of CRYPTO V2 register define */ + +#define RK_RNG_TIME_OUT 50000 /* max 50ms */ + +struct rk_rng_soc_data { + int (*rk_rng_read)(struct udevice *dev, void *data, size_t len); +}; + +struct rk_rng_platdata { + fdt_addr_t base; + struct rk_rng_soc_data *soc_data; +}; + +static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size) +{ + u32 count = RK_HW_RNG_MAX / sizeof(u32); + u32 reg, tmp_len; + + if (size > RK_HW_RNG_MAX) + return -EINVAL; + + while (size && count) { + reg = readl(addr); + tmp_len = min(size, sizeof(u32)); + memcpy(buf, ®, tmp_len); + addr += sizeof(u32); + buf += tmp_len; + size -= tmp_len; + count--; + } + + return 0; +} + +static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len) +{ + struct rk_rng_platdata *pdata = dev_get_priv(dev); + u32 reg = 0; + int retval; + + if (len > RK_HW_RNG_MAX) + return -EINVAL; + + /* enable osc_ring to get entropy, sample period is set as 100 */ + writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100), + pdata->base + CRYPTO_V1_TRNG_CTRL); + + rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START, + CRYPTO_V1_RNG_START); + + retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg, + !(reg & CRYPTO_V1_RNG_START), + RK_RNG_TIME_OUT); + if (retval) + goto exit; + + rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len); + +exit: + /* close TRNG */ + rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START); + + return 0; +} + +static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len) +{ + struct rk_rng_platdata *pdata = dev_get_priv(dev); + u32 reg = 0; + int retval; + + if (len > RK_HW_RNG_MAX) + return -EINVAL; + + /* enable osc_ring to get entropy, sample period is set as 100 */ + writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT); + + reg |= CRYPTO_V2_RNG_256_BIT_LEN; + reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0; + reg |= CRYPTO_V2_RNG_ENABLE; + reg |= CRYPTO_V2_RNG_START; + + rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg); + + retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg, + !(reg & CRYPTO_V2_RNG_START), + RK_RNG_TIME_OUT); + if (retval) + goto exit; + + rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len); + +exit: + /* close TRNG */ + rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff); + + return retval; +} + +static int rockchip_rng_read(struct udevice *dev, void *data, size_t len) +{ + unsigned char *buf = data; + unsigned int i; + int ret = -EIO; + + struct rk_rng_platdata *pdata = dev_get_priv(dev); + + if (!len) + return 0; + + if (!pdata->soc_data || !pdata->soc_data->rk_rng_read) + return -EINVAL; + + for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) { + ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX); + if (ret) + goto exit; + } + + if (len % RK_HW_RNG_MAX) + ret = pdata->soc_data->rk_rng_read(dev, buf, + len % RK_HW_RNG_MAX); + +exit: + return ret; +} + +static int rockchip_rng_ofdata_to_platdata(struct udevice *dev) +{ + struct rk_rng_platdata *pdata = dev_get_priv(dev); + + memset(pdata, 0x00, sizeof(*pdata)); + + pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev); + if (!pdata->base) + return -ENOMEM; + + return 0; +} + +static int rockchip_rng_probe(struct udevice *dev) +{ + struct rk_rng_platdata *pdata = dev_get_priv(dev); + + pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev); + + return 0; +} + +static const struct rk_rng_soc_data rk_rng_v1_soc_data = { + .rk_rng_read = rk_v1_rng_read, +}; + +static const struct rk_rng_soc_data rk_rng_v2_soc_data = { + .rk_rng_read = rk_v2_rng_read, +}; + +static const struct dm_rng_ops rockchip_rng_ops = { + .read = rockchip_rng_read, +}; + +static const struct udevice_id rockchip_rng_match[] = { + { + .compatible = "rockchip,cryptov1-rng", + .data = (ulong)&rk_rng_v1_soc_data, + }, + { + .compatible = "rockchip,cryptov2-rng", + .data = (ulong)&rk_rng_v2_soc_data, + }, + {}, +}; + +U_BOOT_DRIVER(rockchip_rng) = { + .name = "rockchip-rng", + .id = UCLASS_RNG, + .of_match = rockchip_rng_match, + .ops = &rockchip_rng_ops, + .probe = rockchip_rng_probe, + .ofdata_to_platdata = rockchip_rng_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct rk_rng_platdata), +}; diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index f4444b9c34..71d3faf169 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include "rk_mipi.h" diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index 74ebe770a9..cfaa37797e 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include "rk_mipi.h" diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index cf84b886e7..99b16cd95e 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -997,7 +997,7 @@ static int rk_edp_ofdata_to_platdata(struct udevice *dev) { struct rk_edp_priv *priv = dev_get_priv(dev); - priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev); + priv->regs = dev_read_addr_ptr(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); return 0; diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index 79e24baf53..c92c2e3c6c 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -161,8 +161,7 @@ int rk_lvds_enable(struct udevice *dev, int panel_bpp, int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing) { - if (fdtdec_decode_display_timing - (gd->fdt_blob, dev_of_offset(dev), 0, timing)) { + if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) { debug("%s: Failed to decode display timing\n", __func__); return -EINVAL; } @@ -173,13 +172,11 @@ int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing) static int rk_lvds_ofdata_to_platdata(struct udevice *dev) { struct rk_lvds_priv *priv = dev_get_priv(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); int ret; - priv->regs = (void *)devfdt_get_addr(dev); + priv->regs = dev_read_addr_ptr(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - ret = fdtdec_get_int(blob, node, "rockchip,output", -1); + ret = dev_read_s32_default(dev, "rockchip,output", -1); if (ret != -1) { priv->output = ret; debug("LVDS output : %d\n", ret); @@ -188,7 +185,7 @@ static int rk_lvds_ofdata_to_platdata(struct udevice *dev) priv->output = LVDS_OUTPUT_RGB; } - ret = fdtdec_get_int(blob, node, "rockchip,data-mapping", -1); + ret = dev_read_s32_default(dev, "rockchip,data-mapping", -1); if (ret != -1) { priv->format = ret; debug("LVDS data-mapping : %d\n", ret); @@ -197,7 +194,7 @@ static int rk_lvds_ofdata_to_platdata(struct udevice *dev) priv->format = LVDS_FORMAT_JEIDA; } - ret = fdtdec_get_int(blob, node, "rockchip,data-width", -1); + ret = dev_read_s32_default(dev, "rockchip,data-width", -1); if (ret != -1) { debug("LVDS data-width : %d\n", ret); if (ret == 24) { diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index f9280e8607..f1c21bb8d7 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include "rk_mipi.h" @@ -29,8 +28,7 @@ int rk_mipi_read_timing(struct udevice *dev, { int ret; - ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), - 0, timing); + ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timing); if (ret) { debug("%s: Failed to decode display timing (ret=%d)\n", __func__, ret); @@ -77,7 +75,7 @@ static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val) int rk_mipi_dsi_enable(struct udevice *dev, const struct display_timing *timing) { - int node, timing_node; + ofnode node, timing_node; int val; struct rk_mipi_priv *priv = dev_get_priv(dev); uintptr_t regs = priv->regs; @@ -120,10 +118,10 @@ int rk_mipi_dsi_enable(struct udevice *dev, rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0); /* Set dpi color coding depth 24 bit */ - timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev), - "display-timings"); - node = fdt_first_subnode(gd->fdt_blob, timing_node); - val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1); + timing_node = ofnode_find_subnode(dev->node, "display-timings"); + node = ofnode_first_subnode(timing_node); + + val = ofnode_read_u32_default(node, "bits-per-pixel", -1); switch (val) { case 16: rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1); diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h index cde61ed883..555b4ff660 100644 --- a/include/dt-bindings/clock/rk3328-cru.h +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Elaine */ #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H @@ -90,119 +91,118 @@ #define SCLK_MAC2IO_EXT 102 /* dclk gates */ -#define DCLK_LCDC 180 -#define DCLK_HDMIPHY 181 -#define HDMIPHY 182 -#define USB480M 183 -#define DCLK_LCDC_SRC 184 +#define DCLK_LCDC 120 +#define DCLK_HDMIPHY 121 +#define HDMIPHY 122 +#define USB480M 123 +#define DCLK_LCDC_SRC 124 /* aclk gates */ -#define ACLK_AXISRAM 190 -#define ACLK_VOP_PRE 191 -#define ACLK_USB3OTG 192 -#define ACLK_RGA_PRE 193 -#define ACLK_DMAC 194 -#define ACLK_GPU 195 -#define ACLK_BUS_PRE 196 -#define ACLK_PERI_PRE 197 -#define ACLK_RKVDEC_PRE 198 -#define ACLK_RKVDEC 199 -#define ACLK_RKVENC 200 -#define ACLK_VPU_PRE 201 -#define ACLK_VIO_PRE 202 -#define ACLK_VPU 203 -#define ACLK_VIO 204 -#define ACLK_VOP 205 -#define ACLK_GMAC 206 -#define ACLK_H265 207 -#define ACLK_H264 208 -#define ACLK_MAC2PHY 209 -#define ACLK_MAC2IO 210 -#define ACLK_DCF 211 -#define ACLK_TSP 212 -#define ACLK_PERI 213 -#define ACLK_RGA 214 -#define ACLK_IEP 215 -#define ACLK_CIF 216 -#define ACLK_HDCP 217 +#define ACLK_AXISRAM 130 +#define ACLK_VOP_PRE 131 +#define ACLK_USB3OTG 132 +#define ACLK_RGA_PRE 133 +#define ACLK_DMAC 134 +#define ACLK_GPU 135 +#define ACLK_BUS_PRE 136 +#define ACLK_PERI_PRE 137 +#define ACLK_RKVDEC_PRE 138 +#define ACLK_RKVDEC 139 +#define ACLK_RKVENC 140 +#define ACLK_VPU_PRE 141 +#define ACLK_VIO_PRE 142 +#define ACLK_VPU 143 +#define ACLK_VIO 144 +#define ACLK_VOP 145 +#define ACLK_GMAC 146 +#define ACLK_H265 147 +#define ACLK_H264 148 +#define ACLK_MAC2PHY 149 +#define ACLK_MAC2IO 150 +#define ACLK_DCF 151 +#define ACLK_TSP 152 +#define ACLK_PERI 153 +#define ACLK_RGA 154 +#define ACLK_IEP 155 +#define ACLK_CIF 156 +#define ACLK_HDCP 157 /* pclk gates */ -#define PCLK_GPIO0 300 -#define PCLK_GPIO1 301 -#define PCLK_GPIO2 302 -#define PCLK_GPIO3 303 -#define PCLK_GRF 304 -#define PCLK_I2C0 305 -#define PCLK_I2C1 306 -#define PCLK_I2C2 307 -#define PCLK_I2C3 308 -#define PCLK_SPI 309 -#define PCLK_UART0 310 -#define PCLK_UART1 311 -#define PCLK_UART2 312 -#define PCLK_TSADC 313 -#define PCLK_PWM 314 -#define PCLK_TIMER 315 -#define PCLK_BUS_PRE 316 -#define PCLK_PERI_PRE 317 -#define PCLK_HDMI_CTRL 318 -#define PCLK_HDMI_PHY 319 -#define PCLK_GMAC 320 -#define PCLK_H265 321 -#define PCLK_MAC2PHY 322 -#define PCLK_MAC2IO 323 -#define PCLK_USB3PHY_OTG 324 -#define PCLK_USB3PHY_PIPE 325 -#define PCLK_USB3_GRF 326 -#define PCLK_USB2_GRF 327 -#define PCLK_HDMIPHY 328 -#define PCLK_DDR 329 -#define PCLK_PERI 330 -#define PCLK_HDMI 331 -#define PCLK_HDCP 332 -#define PCLK_DCF 333 -#define PCLK_SARADC 334 +#define PCLK_GPIO0 200 +#define PCLK_GPIO1 201 +#define PCLK_GPIO2 202 +#define PCLK_GPIO3 203 +#define PCLK_GRF 204 +#define PCLK_I2C0 205 +#define PCLK_I2C1 206 +#define PCLK_I2C2 207 +#define PCLK_I2C3 208 +#define PCLK_SPI 209 +#define PCLK_UART0 210 +#define PCLK_UART1 211 +#define PCLK_UART2 212 +#define PCLK_TSADC 213 +#define PCLK_PWM 214 +#define PCLK_TIMER 215 +#define PCLK_BUS_PRE 216 +#define PCLK_PERI_PRE 217 +#define PCLK_HDMI_CTRL 218 +#define PCLK_HDMI_PHY 219 +#define PCLK_GMAC 220 +#define PCLK_H265 221 +#define PCLK_MAC2PHY 222 +#define PCLK_MAC2IO 223 +#define PCLK_USB3PHY_OTG 224 +#define PCLK_USB3PHY_PIPE 225 +#define PCLK_USB3_GRF 226 +#define PCLK_USB2_GRF 227 +#define PCLK_HDMIPHY 228 +#define PCLK_DDR 229 +#define PCLK_PERI 230 +#define PCLK_HDMI 231 +#define PCLK_HDCP 232 +#define PCLK_DCF 233 +#define PCLK_SARADC 234 +#define PCLK_ACODECPHY 235 +#define PCLK_WDT 236 /* hclk gates */ -#define HCLK_PERI 408 -#define HCLK_TSP 409 -#define HCLK_GMAC 410 -#define HCLK_I2S0_8CH 411 -#define HCLK_I2S1_8CH 413 -#define HCLK_I2S2_2CH 413 -#define HCLK_SPDIF_8CH 414 -#define HCLK_VOP 415 -#define HCLK_NANDC 416 -#define HCLK_SDMMC 417 -#define HCLK_SDIO 418 -#define HCLK_EMMC 419 -#define HCLK_SDMMC_EXT 420 -#define HCLK_RKVDEC_PRE 421 -#define HCLK_RKVDEC 422 -#define HCLK_RKVENC 423 -#define HCLK_VPU_PRE 424 -#define HCLK_VIO_PRE 425 -#define HCLK_VPU 426 -#define HCLK_VIO 427 -#define HCLK_BUS_PRE 428 -#define HCLK_PERI_PRE 429 -#define HCLK_H264 430 -#define HCLK_CIF 431 -#define HCLK_OTG_PMU 432 -#define HCLK_OTG 433 -#define HCLK_HOST0 434 -#define HCLK_HOST0_ARB 435 -#define HCLK_CRYPTO_MST 436 -#define HCLK_CRYPTO_SLV 437 -#define HCLK_PDM 438 -#define HCLK_IEP 439 -#define HCLK_RGA 440 -#define HCLK_HDCP 441 +#define HCLK_PERI 308 +#define HCLK_TSP 309 +#define HCLK_GMAC 310 +#define HCLK_I2S0_8CH 311 +#define HCLK_I2S1_8CH 312 +#define HCLK_I2S2_2CH 313 +#define HCLK_SPDIF_8CH 314 +#define HCLK_VOP 315 +#define HCLK_NANDC 316 +#define HCLK_SDMMC 317 +#define HCLK_SDIO 318 +#define HCLK_EMMC 319 +#define HCLK_SDMMC_EXT 320 +#define HCLK_RKVDEC_PRE 321 +#define HCLK_RKVDEC 322 +#define HCLK_RKVENC 323 +#define HCLK_VPU_PRE 324 +#define HCLK_VIO_PRE 325 +#define HCLK_VPU 326 +#define HCLK_BUS_PRE 328 +#define HCLK_PERI_PRE 329 +#define HCLK_H264 330 +#define HCLK_CIF 331 +#define HCLK_OTG_PMU 332 +#define HCLK_OTG 333 +#define HCLK_HOST0 334 +#define HCLK_HOST0_ARB 335 +#define HCLK_CRYPTO_MST 336 +#define HCLK_CRYPTO_SLV 337 +#define HCLK_PDM 338 +#define HCLK_IEP 339 +#define HCLK_RGA 340 +#define HCLK_HDCP 341 #define CLK_NR_CLKS (HCLK_HDCP + 1) -#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1) - /* soft-reset indices */ #define SRST_CORE0_PO 0 #define SRST_CORE1_PO 1 diff --git a/include/dt-bindings/power/rk3328-power.h b/include/dt-bindings/power/rk3328-power.h new file mode 100644 index 0000000000..02e3d7fc1c --- /dev/null +++ b/include/dt-bindings/power/rk3328-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__ +#define __DT_BINDINGS_POWER_RK3328_POWER_H__ + +/** + * RK3328 idle id Summary. + */ +#define RK3328_PD_CORE 0 +#define RK3328_PD_GPU 1 +#define RK3328_PD_BUS 2 +#define RK3328_PD_MSCH 3 +#define RK3328_PD_PERI 4 +#define RK3328_PD_VIDEO 5 +#define RK3328_PD_HEVC 6 +#define RK3328_PD_SYS 7 +#define RK3328_PD_VPU 8 +#define RK3328_PD_VIO 9 + +#endif