dm: powerpc: T1040/T1042: add i2c DM support

This supports i2c DM for SoC T1040/T1042

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
index 093aaab834b7a9b1344465224996c53f40dba327..0a08a69f31ae3863850bacee005335c6926c32da 100644 (file)
--- a/arch/powerpc/dts/t104x.dtsi
+++ b/arch/powerpc/dts/t104x.dtsi
@@ -3,7 +3,7 @@
  * T104X Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2013 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /dts-v1/;
@@ -85,6 +85,8 @@
                        reg = <0x114000 0x1000>;
                        clock-frequency = <0>;
                };
+               /include/ "qoriq-i2c-0.dtsi"
+               /include/ "qoriq-i2c-1.dtsi"
        };
 
        pcie@ffe240000 {

diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c
index ab9e922a927d7e73fc3742a054c400d4025f8941..0b1aeed69e4214c0800baadf83b8d07ab388f33a 100644 (file)
--- a/board/freescale/t1040qds/diu.c
+++ b/board/freescale/t1040qds/diu.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
  */
 
@@ -48,7 +49,7 @@ void diu_set_pixel_clock(unsigned int pixclock)
 
        /* Program HDMI encoder */
        /* Switch channel to DIU */
-       select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
+       select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0);
 
        /* Set dispaly encoder */
        ret = diu_set_dvi_encoder(temp);
@@ -58,7 +59,7 @@ void diu_set_pixel_clock(unsigned int pixclock)
        }
 
        /* Switch channel to default */
-       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 
        /* Program pixel clock */
        out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,

diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index 92dd9237ec7f884e368fe03309c57b1de202af0c..9e253fdec27d079e08c5c6233065823570c724dc 100644 (file)
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -79,11 +80,24 @@ int checkboard(void)
        return 0;
 }
 
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
 {
        int ret;
 
+#ifdef CONFIG_DM_I2C
+       struct udevice *dev;
+
+       ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+       if (ret) {
+               printf("%s: Cannot find udev for a bus %d\n", __func__,
+                      bus_num);
+               return ret;
+       }
+
+       ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
        ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
        if (ret) {
                puts("PCA: failed to select proper channel\n");
                return ret;
@@ -154,7 +168,7 @@ int board_early_init_r(void)
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif
-       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 
        return 0;
 }

diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h
index d2f0203f17795eb4e3948393575f4ebbd1125962..781bcdefc93ec8518ecb4bb6c058d1dab01aef35 100644 (file)
--- a/board/freescale/t1040qds/t1040qds.h
+++ b/board/freescale/t1040qds/t1040qds.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #ifndef __T1040_QDS_H__
@@ -8,6 +9,6 @@
 
 void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, bd_t *bd);
-int select_i2c_ch_pca9547(u8 ch);
+int select_i2c_ch_pca9547(u8 ch, int bus_bum);
 
 #endif

diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index cda8251036e029e8d85ba8c6ed469220153ebaa6..ad8efb3503de6f28ee1c84f9c028c16c044f3336 100644 (file)
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -1,5 +1,6 @@
 /*
  * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -360,6 +361,8 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 /* I2C */
+
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL             /* Use FSL common I2C driver */
 #define CONFIG_SYS_FSL_I2C_SPEED       50000   /* I2C speed in Hz */
@@ -374,6 +377,9 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FSL_I2C2_OFFSET     0x118100
 #define CONFIG_SYS_FSL_I2C3_OFFSET     0x119000
 #define CONFIG_SYS_FSL_I2C4_OFFSET     0x119100
+#endif
+
+#define CONFIG_SYS_I2C_FSL             /* Use FSL common I2C driver */
 
 #define I2C_MUX_PCA_ADDR               0x77
 #define I2C_MUX_PCA_ADDR_PRI           0x77 /* Primary Mux*/
@@ -385,6 +391,7 @@ unsigned long get_board_ddr_clk(void);
 /* LDI/DVI Encoder for display */
 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
+#define CONFIG_SYS_I2C_DVI_BUS_NUM     0
 
 /*
  * RTC configuration

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index bc651186578078704dc9dadcf33246cde39d09bb..7d15910f659e981ca637c516189dd1bedc909c76 100644 (file)
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #ifndef __CONFIG_H
@@ -27,6 +28,7 @@
 #define CONFIG_SPL_SKIP_RELOCATE
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_DM_I2C
 #endif
 #define RESET_VECTOR_OFFSET            0x27FFC
 #define BOOT_PAGE_OFFSET               0x27000
@@ -459,8 +461,8 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 #endif
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL             /* Use FSL common I2C driver */
 #define CONFIG_SYS_FSL_I2C_SPEED       400000  /* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C2_SPEED      400000
 #define CONFIG_SYS_FSL_I2C3_SPEED      400000
@@ -473,7 +475,12 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 #define CONFIG_SYS_FSL_I2C2_OFFSET     0x118100
 #define CONFIG_SYS_FSL_I2C3_OFFSET     0x119000
 #define CONFIG_SYS_FSL_I2C4_OFFSET     0x119100
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER  0
+#endif
 
+#define CONFIG_SYS_I2C_FSL             /* Use FSL common I2C driver */
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR                0x70
 #define I2C_MUX_CH_DEFAULT      0x8
@@ -484,6 +491,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 /* LDI/DVI Encoder for display */
 #define CONFIG_SYS_I2C_LDI_ADDR                0x38
 #define CONFIG_SYS_I2C_DVI_ADDR                0x75
+#define CONFIG_SYS_I2C_DVI_BUS_NUM     0
 
 /*
  * RTC configuration