ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7

The iMX7 defines further DDRC ZQCTLx registers, however those were
thus far missing from the list of registers and not programmed. On
systems with LPDDR2 or DDR3, those registers must be programmed with
correct values, otherwise the DRAM may not work. However, existing
systems which worked without programming these registers before are
now setting those registers to 0, which is the default value, so no
functional change there.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/include/asm/arch-mx7/mx7-ddr.h b/arch/arm/include/asm/arch-mx7/mx7-ddr.h
index 37aaee0ad79166fd4d9621222eb5321ab61c87ef..bea5dd8ec5ef6b2df1295985acc2a53357b26563 100644 (file)
--- a/arch/arm/include/asm/arch-mx7/mx7-ddr.h
+++ b/arch/arm/include/asm/arch-mx7/mx7-ddr.h
@@ -39,7 +39,9 @@ struct ddrc {
        u32 dramtmg8;           /* 0x0120 */
        u32 reserved7[0x17];
        u32 zqctl0;             /* 0x0180 */
        u32 dramtmg8;           /* 0x0120 */
        u32 reserved7[0x17];
        u32 zqctl0;             /* 0x0180 */

-       u32 reserved8[0x03];
+       u32 zqctl1;             /* 0x0184 */
+       u32 zqctl2;             /* 0x0188 */
+       u32 zqstat;             /* 0x018c */

        u32 dfitmg0;            /* 0x0190 */
        u32 dfitmg1;            /* 0x0194 */
        u32 reserved9[0x02];
        u32 dfitmg0;            /* 0x0190 */
        u32 dfitmg1;            /* 0x0194 */
        u32 reserved9[0x02];

diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c
index d1e10a678870ef7a61d81533a0c7b553eb166f3a..45954ed1edc0dfe8c40f69a82bf1cced13ad1d5c 100644 (file)
--- a/arch/arm/mach-imx/mx7/ddr.c
+++ b/arch/arm/mach-imx/mx7/ddr.c
@@ -74,6 +74,7 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
        writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
        writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
        writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
        writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
        writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
        writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);

+       writel(ddrc_regs_val->zqctl1, &ddrc_regs->zqctl1);

        writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
        writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
        writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);
        writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
        writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
        writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);