ARM: at91: Rename sama5_sfr.h to at91_sfr.h

The Special Function Registers (SFR) are present in sam9x5 and
sam9x60 too, rename sama5_sfr to at91_sfr.h.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c
index 5c693df2ecf062bf28e7ab53dc976e6e6a5059d0..e68ae994078858e11d1dfe5e550b28e32fd3b883 100644 (file)
--- a/arch/arm/mach-at91/armv7/sama5d4_devices.c
+++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c
@@ -8,7 +8,7 @@
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/at91_sfr.h>
 #include <asm/arch/sama5d4.h>
 
 char *get_cpu_name()

diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c
index 13cfba0ba0c0e9153c442ec29846bfbf4624cd07..b14222460f3acd74f888774fdcaceaafd5ed6b9b 100644 (file)
--- a/arch/arm/mach-at91/atmel_sfr.c
+++ b/arch/arm/mach-at91/atmel_sfr.c
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
-#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/at91_sfr.h>
 
 #if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D4)
 void redirect_int_from_saic_to_aic(void)

diff --git a/arch/arm/mach-at91/include/mach/at91_sfr.h b/arch/arm/mach-at91/include/mach/at91_sfr.h
new file mode 100644 (file)
index 0000000..dc25905
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_sfr.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Special Function Register (SFR)
+ *
+ * Copyright (C) 2014 Atmel
+ *                   Bo Shen <voice.shen@atmel.com>
+ */
+
+#ifndef __AT91_SFR_H
+#define __AT91_SFR_H
+
+struct atmel_sfr {
+       u32 reserved1;  /* 0x00 */
+       u32 ddrcfg;     /* 0x04: DDR Configuration Register */
+       u32 reserved2;  /* 0x08 */
+       u32 reserved3;  /* 0x0c */
+       u32 ohciicr;    /* 0x10: OHCI Interrupt Configuration Register */
+       u32 ohciisr;    /* 0x14: OHCI Interrupt Status Register */
+       u32 reserved4[4];       /* 0x18 ~ 0x24 */
+       u32 secure;             /* 0x28: Security Configuration Register */
+       u32 reserved5[5];       /* 0x2c ~ 0x3c */
+       u32 ebicfg;             /* 0x40: EBI Configuration Register */
+       u32 reserved6[2];       /* 0x44 ~ 0x48 */
+       u32 sn0;                /* 0x4c */
+       u32 sn1;                /* 0x50 */
+       u32 aicredir;   /* 0x54 */
+       u32 l2cc_hramc; /* 0x58 */
+};
+
+/* Register Mapping*/
+#define AT91_SFR_UTMICKTRIM    0x30    /* UTMI Clock Trimming Register */
+
+/* Bit field in DDRCFG */
+#define ATMEL_SFR_DDRCFG_FDQIEN                0x00010000
+#define ATMEL_SFR_DDRCFG_FDQSIEN       0x00020000
+
+/* Bit field in EBICFG */
+#define AT91_SFR_EBICFG_DRIVE0         (0x3 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_LOW             (0x0 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_MEDIUM          (0x2 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_HIGH            (0x3 << 0)
+#define AT91_SFR_EBICFG_PULL0          (0x3 << 2)
+#define AT91_SFR_EBICFG_PULL0_UP               (0x0 << 2)
+#define AT91_SFR_EBICFG_PULL0_NONE             (0x1 << 2)
+#define AT91_SFR_EBICFG_PULL0_DOWN             (0x3 << 2)
+#define AT91_SFR_EBICFG_SCH0           (0x1 << 4)
+#define AT91_SFR_EBICFG_SCH0_OFF               (0x0 << 4)
+#define AT91_SFR_EBICFG_SCH0_ON                        (0x1 << 4)
+#define AT91_SFR_EBICFG_DRIVE1         (0x3 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_LOW             (0x0 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_MEDIUM          (0x2 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_HIGH            (0x3 << 8)
+#define AT91_SFR_EBICFG_PULL1          (0x3 << 10)
+#define AT91_SFR_EBICFG_PULL1_UP               (0x0 << 10)
+#define AT91_SFR_EBICFG_PULL1_NONE             (0x1 << 10)
+#define AT91_SFR_EBICFG_PULL1_DOWN             (0x3 << 10)
+#define AT91_SFR_EBICFG_SCH1           (0x1 << 12)
+#define AT91_SFR_EBICFG_SCH1_OFF               (0x0 << 12)
+#define AT91_SFR_EBICFG_SCH1_ON                        (0x1 << 12)
+
+#define AT91_UTMICKTRIM_FREQ           GENMASK(1, 0)
+
+/* Bit field in AICREDIR */
+#define ATMEL_SFR_AICREDIR_NSAIC       0x00000001
+
+#endif

diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h
deleted file mode 100644 (file)
index f9c412f..0000000
--- a/arch/arm/mach-at91/include/mach/sama5_sfr.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Special Function Register (SFR)
- *
- * Copyright (C) 2014 Atmel
- *                   Bo Shen <voice.shen@atmel.com>
- */
-
-#ifndef __SAMA5_SFR_H
-#define __SAMA5_SFR_H
-
-struct atmel_sfr {
-       u32 reserved1;  /* 0x00 */
-       u32 ddrcfg;     /* 0x04: DDR Configuration Register */
-       u32 reserved2;  /* 0x08 */
-       u32 reserved3;  /* 0x0c */
-       u32 ohciicr;    /* 0x10: OHCI Interrupt Configuration Register */
-       u32 ohciisr;    /* 0x14: OHCI Interrupt Status Register */
-       u32 reserved4[4];       /* 0x18 ~ 0x24 */
-       u32 secure;             /* 0x28: Security Configuration Register */
-       u32 reserved5[5];       /* 0x2c ~ 0x3c */
-       u32 ebicfg;             /* 0x40: EBI Configuration Register */
-       u32 reserved6[2];       /* 0x44 ~ 0x48 */
-       u32 sn0;                /* 0x4c */
-       u32 sn1;                /* 0x50 */
-       u32 aicredir;   /* 0x54 */
-       u32 l2cc_hramc; /* 0x58 */
-};
-
-/* Register Mapping*/
-#define AT91_SFR_UTMICKTRIM    0x30    /* UTMI Clock Trimming Register */
-
-/* Bit field in DDRCFG */
-#define ATMEL_SFR_DDRCFG_FDQIEN                0x00010000
-#define ATMEL_SFR_DDRCFG_FDQSIEN       0x00020000
-
-/* Bit field in EBICFG */
-#define AT91_SFR_EBICFG_DRIVE0         (0x3 << 0)
-#define AT91_SFR_EBICFG_DRIVE0_LOW             (0x0 << 0)
-#define AT91_SFR_EBICFG_DRIVE0_MEDIUM          (0x2 << 0)
-#define AT91_SFR_EBICFG_DRIVE0_HIGH            (0x3 << 0)
-#define AT91_SFR_EBICFG_PULL0          (0x3 << 2)
-#define AT91_SFR_EBICFG_PULL0_UP               (0x0 << 2)
-#define AT91_SFR_EBICFG_PULL0_NONE             (0x1 << 2)
-#define AT91_SFR_EBICFG_PULL0_DOWN             (0x3 << 2)
-#define AT91_SFR_EBICFG_SCH0           (0x1 << 4)
-#define AT91_SFR_EBICFG_SCH0_OFF               (0x0 << 4)
-#define AT91_SFR_EBICFG_SCH0_ON                        (0x1 << 4)
-#define AT91_SFR_EBICFG_DRIVE1         (0x3 << 8)
-#define AT91_SFR_EBICFG_DRIVE1_LOW             (0x0 << 8)
-#define AT91_SFR_EBICFG_DRIVE1_MEDIUM          (0x2 << 8)
-#define AT91_SFR_EBICFG_DRIVE1_HIGH            (0x3 << 8)
-#define AT91_SFR_EBICFG_PULL1          (0x3 << 10)
-#define AT91_SFR_EBICFG_PULL1_UP               (0x0 << 10)
-#define AT91_SFR_EBICFG_PULL1_NONE             (0x1 << 10)
-#define AT91_SFR_EBICFG_PULL1_DOWN             (0x3 << 10)
-#define AT91_SFR_EBICFG_SCH1           (0x1 << 12)
-#define AT91_SFR_EBICFG_SCH1_OFF               (0x0 << 12)
-#define AT91_SFR_EBICFG_SCH1_ON                        (0x1 << 12)
-
-#define AT91_UTMICKTRIM_FREQ           GENMASK(1, 0)
-
-/* Bit field in AICREDIR */
-#define ATMEL_SFR_AICREDIR_NSAIC       0x00000001
-
-#endif

diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c
index ab1dbcd879aeee19ffd834b88381501c94a47d4d..13563abb49ef87904c6f480e75d5cf961a41310d 100644 (file)
--- a/board/laird/wb50n/wb50n.c
+++ b/board/laird/wb50n/wb50n.c
@@ -4,7 +4,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/at91_sfr.h>
 #include <asm/arch/sama5d3_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>

diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
index e8506099fd323a4f54813818f682d84ecc134cdc..18af0bfeaad1601a39f221ed2ae9b284e7ffd95c 100644 (file)
--- a/drivers/clk/at91/clk-utmi.c
+++ b/drivers/clk/at91/clk-utmi.c
@@ -10,7 +10,7 @@
 #include <syscon.h>
 #include <linux/io.h>
 #include <mach/at91_pmc.h>
-#include <mach/sama5_sfr.h>
+#include <mach/at91_sfr.h>
 #include "pmc.h"
 
 /*