Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u...
authorTom Rini <trini@konsulko.com>
Thu, 30 Apr 2020 15:31:33 +0000 (11:31 -0400)
committerTom Rini <trini@konsulko.com>
Thu, 30 Apr 2020 15:34:01 +0000 (11:34 -0400)
Xilinx changes for v2020.07-rc2

mmc:
- Fix dt property handling via generic function

clk:
- Fix versal watchdog clock setting

nand:
- Fix zynq nand command comparison

xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose

zynq:
- Kconfig alignments
- Fix nand cse configuration

zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates

Signed-off-by: Tom Rini <trini@konsulko.com>
1  2 
configs/xilinx_zynq_virt_defconfig
configs/zynq_cse_nand_defconfig

index b264529feec46f63a0d37db8af243f10a4b61aba,6af4565451a959220b3bf971b5bd6eb83bbb67f9..7441e10d325a7f931ebf6ac0db0d3e4126979176
@@@ -2,7 -2,6 +2,7 @@@ CONFIG_ARM=
  CONFIG_SPL_SYS_DCACHE_OFF=y
  CONFIG_ARCH_ZYNQ=y
  CONFIG_SYS_TEXT_BASE=0x4000000
 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
  CONFIG_DM_GPIO=y
  CONFIG_SPL_STACK_R_ADDR=0x200000
  CONFIG_SPL=y
@@@ -20,6 -19,7 +20,6 @@@ CONFIG_SPL_STACK_R=
  CONFIG_SPL_FPGA_SUPPORT=y
  CONFIG_SPL_OS_BOOT=y
  CONFIG_SPL_SPI_LOAD=y
 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
  # CONFIG_BOOTM_NETBSD is not set
  CONFIG_CMD_IMLS=y
  CONFIG_CMD_THOR_DOWNLOAD=y
@@@ -32,12 -32,17 +32,17 @@@ CONFIG_CMD_FPGA_LOADP=
  CONFIG_CMD_GPIO=y
  CONFIG_CMD_I2C=y
  CONFIG_CMD_MMC=y
+ CONFIG_CMD_MTD=y
  CONFIG_CMD_NAND_LOCK_UNLOCK=y
  CONFIG_CMD_USB=y
  # CONFIG_CMD_SETEXPR is not set
  CONFIG_CMD_TFTPPUT=y
  CONFIG_CMD_CACHE=y
  CONFIG_CMD_EXT4_WRITE=y
+ CONFIG_CMD_MTDPARTS=y
+ CONFIG_CMD_MTDPARTS_SPREAD=y
+ CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+ CONFIG_CMD_UBI=y
  CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
  CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0"
  CONFIG_ENV_IS_IN_SPI_FLASH=y
index 19491c9e47eb7ce1b40ba6ccda68333f3b9edcdd,80a427d905d3bcab5eea390c98d6feaaf5ff5b66..6a01da2e4e1f263c3746042abbb4a8feaa400b09
@@@ -4,8 -4,8 +4,8 @@@ CONFIG_SYS_ICACHE_OFF=
  CONFIG_SYS_DCACHE_OFF=y
  CONFIG_ARCH_ZYNQ=y
  CONFIG_SYS_TEXT_BASE=0x100000
 -CONFIG_SYS_MALLOC_LEN=0x8000
  CONFIG_ENV_SIZE=0x190
- CONFIG_SYS_MALLOC_LEN=0x1000
++CONFIG_SYS_MALLOC_LEN=0x8000
  CONFIG_SPL_STACK_R_ADDR=0x200000
  CONFIG_SPL=y
  CONFIG_SYS_CUSTOM_LDSCRIPT=y