armv7R: K3: j721e: Add support for boot device detection
authorLokesh Vutla <lokeshvutla@ti.com>
Thu, 13 Jun 2019 04:59:43 +0000 (10:29 +0530)
committerTom Rini <trini@konsulko.com>
Sat, 27 Jul 2019 01:49:26 +0000 (21:49 -0400)
J721E allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
arch/arm/mach-k3/include/mach/hardware.h
arch/arm/mach-k3/include/mach/j721e_hardware.h [new file with mode: 0644]
arch/arm/mach-k3/include/mach/j721e_spl.h [new file with mode: 0644]
arch/arm/mach-k3/include/mach/spl.h
arch/arm/mach-k3/j721e_init.c

index b39f780d2694c8760d1e1bd498fd06c7b29bebd4..4e629822aa1892057edc63ef593a8da3bafbff5e 100644 (file)
@@ -9,4 +9,8 @@
 #ifdef CONFIG_SOC_K3_AM6
 #include "am6_hardware.h"
 #endif
+
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_hardware.h"
+#endif
 #endif /* _ASM_ARCH_HARDWARE_H_ */
diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h
new file mode 100644 (file)
index 0000000..8d42977
--- /dev/null
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: J721E SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __ASM_ARCH_J721E_HARDWARE_H
+#define __ASM_ARCH_J721E_HARDWARE_H
+
+#include <config.h>
+
+#define CTRL_MMR0_BASE                                 0x00100000
+#define CTRLMMR_MAIN_DEVSTAT                           (CTRL_MMR0_BASE + 0x30)
+
+#define MAIN_DEVSTAT_BOOT_MODE_B_MASK          BIT(0)
+#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT         0
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK                GENMASK(3, 1)
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT       1
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK       BIT(6)
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT          6
+
+#define WKUP_CTRL_MMR0_BASE                            0x43000000
+#define MCU_CTRL_MMR0_BASE                             0x40f00000
+
+#define CTRLMMR_WKUP_DEVSTAT                   (WKUP_CTRL_MMR0_BASE + 0x30)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK     GENMASK(5, 3)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT    3
+#define WKUP_DEVSTAT_MCU_OMLY_MASK             BIT(6)
+#define WKUP_DEVSTAT_MCU_ONLY_SHIFT            6
+
+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE                       0x4000
+
+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
+ * shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0                             0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL                  0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK               BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT              0
+#define CTRLMMR_LOCK_KICK1                             0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL                  0xd172bc5a
+
+#endif /* __ASM_ARCH_J721E_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h
new file mode 100644 (file)
index 0000000..2b52faf
--- /dev/null
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ *     Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#ifndef _ASM_ARCH_J721E_SPL_H_
+#define _ASM_ARCH_J721E_SPL_H_
+
+/* With BootMode B = 0 */
+#define BOOT_DEVICE_HYPERFLASH         0x00
+#define BOOT_DEVICE_OSPI               0x01
+#define BOOT_DEVICE_QSPI               0x02
+#define BOOT_DEVICE_SPI                        0x03
+#define BOOT_DEVICE_ETHERNET           0x04
+#define BOOT_DEVICE_I2C                        0x06
+#define BOOT_DEVICE_UART               0x07
+
+/* With BootMode B = 1 */
+#define BOOT_DEVICE_MMC2               0x10
+#define BOOT_DEVICE_MMC1               0x11
+#define BOOT_DEVICE_USB                        0x12
+#define BOOT_DEVICE_UFS                        0x13
+#define BOOT_DEVIE_GPMC                        0x14
+#define BOOT_DEVICE_PCIE               0x15
+#define BOOT_DEVICE_MMC2_2             0x16
+#define BOOT_DEVICE_RAM                        0x17
+
+#define BOOT_MODE_B_SHIFT              4
+#define BOOT_MODE_B_MASK               BIT(4)
+
+#endif
index 2d435aec17c44b2e3d2d7d4c297ced97b2324b90..a26c8ecdd5bd749b86f60780f59582e4215d796a 100644 (file)
@@ -9,4 +9,8 @@
 #ifdef CONFIG_SOC_K3_AM6
 #include "am6_spl.h"
 #endif
+
+#ifdef CONFIG_SOC_K3_J721E
+#include "j721e_spl.h"
+#endif
 #endif /* _ASM_ARCH_SPL_H_ */
index 14b48815276a6d84c427c59f3efecb562fb0b3bd..80e88dd185df2bfc00e008ebad555b652aab00e8 100644 (file)
@@ -10,6 +10,7 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <asm/armv7_mpu.h>
+#include <asm/arch/hardware.h>
 #include "common.h"
 
 #ifdef CONFIG_SPL_BUILD
@@ -31,4 +32,56 @@ void board_init_f(ulong dummy)
        /* Prepare console output */
        preloader_console_init();
 }
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+       switch (boot_device) {
+       case BOOT_DEVICE_MMC1:
+               return MMCSD_MODE_EMMCBOOT;
+       case BOOT_DEVICE_MMC2:
+               return MMCSD_MODE_FS;
+       default:
+               return MMCSD_MODE_RAW;
+       }
+}
+
+static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
+{
+
+       u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+                       WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+
+       bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
+                       BOOT_MODE_B_SHIFT;
+
+       if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
+               bootmode = BOOT_DEVICE_SPI;
+
+       if (bootmode == BOOT_DEVICE_MMC2) {
+               u32 port = (main_devstat &
+                           MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
+                          MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
+               if (port == 0x0)
+                       bootmode = BOOT_DEVICE_MMC1;
+       }
+
+       return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+       u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
+       u32 main_devstat;
+
+       if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
+               printf("ERROR: MCU only boot is not yet supported\n");
+               return BOOT_DEVICE_RAM;
+       }
+
+       /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
+       main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+
+       /* ToDo: Add support for backup boot media */
+       return __get_primary_bootmedia(main_devstat, wkup_devstat);
+}
 #endif