riscv: dts: Support four cores SMP
authorRick Chen <rick@andestech.com>
Thu, 14 Nov 2019 05:52:28 +0000 (13:52 +0800)
committerAndes <uboot@andestech.com>
Tue, 10 Dec 2019 00:23:10 +0000 (08:23 +0800)
commitf05b6569a936af61a4d448ddc899e7b8c0e5b3c8
tree7c9b4f815f6c5dea22ba6543ce3264c9b7e34160
parent444c46413fb691c7abbb2bec3ed498ab08fa36f8
riscv: dts: Support four cores SMP

Add CPU2 and CPU3 information in cpus node
to support four cores SMP booting.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
arch/riscv/dts/ae350_32.dts
arch/riscv/dts/ae350_64.dts