t210: do not enable PLLE and UPHY PLL HW PWRSEQ
authorJC Kuo <jckuo@nvidia.com>
Thu, 26 Mar 2020 23:10:09 +0000 (16:10 -0700)
committerTom Warren <twarren@nvidia.com>
Thu, 2 Apr 2020 21:30:01 +0000 (14:30 -0700)
commitd491dc09e4cfb7e513d3d6f448d811f1297753d9
treedf53d53d39048ade69bc6e351ee8c78b9aff5fc7
parent9eb15cbe5c94fca24519b5d89d934eeb34a68e5d
t210: do not enable PLLE and UPHY PLL HW PWRSEQ

This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.

Adds call to board_cleanup_before_linux to facilitate this.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
arch/arm/cpu/armv8/cpu.c
arch/arm/include/asm/arch-tegra/xusb-padctl.h
arch/arm/mach-tegra/board2.c
arch/arm/mach-tegra/tegra210/clock.c
arch/arm/mach-tegra/tegra210/xusb-padctl.c
arch/arm/mach-tegra/xusb-padctl-dummy.c