MMC: DWMMC: Correct the CLKDIV register value
authorRajeshwari S Shinde <rajeshwari.s@samsung.com>
Wed, 5 Feb 2014 05:18:15 +0000 (10:48 +0530)
committerPantelis Antoniou <panto@antoniou-consulting.com>
Fri, 7 Feb 2014 15:42:26 +0000 (17:42 +0200)
commitd3e016cc28684cd32d826a9414a0e89ccf80861a
tree8ed71c5f9ff24fded82a3f6730cd28744e17a2cc
parentdef816a2ba87c2a3507536e8cb226f0f85bdae2c
MMC: DWMMC: Correct the CLKDIV register value

This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL register, we need to use the same output clock value to
calculate the CLKDIV value.
as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)

Input parameter to mmc_clk is changed to dwmci_host, since
we need the same to read DWMCI_CLKSEL register.

This improves the read timing values for channel 0 on SMDK5250
from 0.288sec to 0.144sec

Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
arch/arm/include/asm/arch-exynos/dwmmc.h
drivers/mmc/dw_mmc.c
drivers/mmc/exynos_dw_mmc.c
include/dwmmc.h