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(parent: 3e0a0fb) | patch
armv8/ls1043a: Implement workaround for erratum A009660
authorMingkai Hu <mingkai.hu@nxp.com>
Tue, 2 Feb 2016 03:28:03 +0000 (11:28 +0800)
committerYork Sun <york.sun@nxp.com>
Wed, 24 Feb 2016 16:40:56 +0000 (08:40 -0800)
commitbbc8e053bad16366fc74943ce4c69a910c31b8b8
tree16ceab0d9a3f04295a2d9bdffbf0424d5cb99f36tree | snapshot
parent3e0a0fbbac48e47d45e234691fddb55194052bedcommit | diff
armv8/ls1043a: Implement workaround for erratum A009660

Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/soc.c diff | blob | history
arch/arm/include/asm/arch-fsl-layerscape/config.h diff | blob | history
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