PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
authorStefan Roese <sr@denx.de>
Fri, 28 Jul 2006 16:34:58 +0000 (18:34 +0200)
committerStefan Roese <sr@denx.de>
Fri, 28 Jul 2006 16:34:58 +0000 (18:34 +0200)
commita2c95a72247990dee9a03b26b4dc9fc0182c97ed
treecabdaa860480f895cccc6600f3454a751329c13c
parentfc6c4a67ae94adac02da6257a0f5adc3bd48ebec
PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006
CHANGELOG
board/amcc/yellowstone/yellowstone.c
board/amcc/yosemite/yosemite.c
cpu/ppc4xx/sdram.c
cpu/ppc4xx/spd_sdram.c
doc/README.440-DDR-performance [new file with mode: 0644]